SM24 Control Firmware
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Topics | Data Structures | Macros
Status and Control Registers
Defines and Type Definitions

Core Register type definitions. More...

Topics

 Nested Vectored Interrupt Controller (NVIC)
 Type definitions for the NVIC Registers.
 

Data Structures

union  APSR_Type
 Union type to access the Application Program Status Register (APSR). More...
 
union  IPSR_Type
 Union type to access the Interrupt Program Status Register (IPSR). More...
 
union  xPSR_Type
 Union type to access the Special-Purpose Program Status Registers (xPSR). More...
 
union  CONTROL_Type
 Union type to access the Control Registers (CONTROL). More...
 

Macros

#define NVIC_STIR_INTID_Pos   0U
 
#define NVIC_STIR_INTID_Msk   (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLBASE_Pos   29U
 
#define SCB_VTOR_TBLBASE_Msk   (1UL << SCB_VTOR_TBLBASE_Pos)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_AIRCR_VECTRESET_Pos   0U
 
#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_CCR_NONBASETHRDENA_Pos   0U
 
#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SysTick_CTRL_COUNTFLAG_Pos   16U
 
#define SysTick_CTRL_COUNTFLAG_Msk   (1UL << SysTick_CTRL_COUNTFLAG_Pos)
 
#define SysTick_CTRL_CLKSOURCE_Pos   2U
 
#define SysTick_CTRL_CLKSOURCE_Msk   (1UL << SysTick_CTRL_CLKSOURCE_Pos)
 
#define SysTick_CTRL_TICKINT_Pos   1U
 
#define SysTick_CTRL_TICKINT_Msk   (1UL << SysTick_CTRL_TICKINT_Pos)
 
#define SysTick_CTRL_ENABLE_Pos   0U
 
#define SysTick_CTRL_ENABLE_Msk   (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)
 
#define SysTick_LOAD_RELOAD_Pos   0U
 
#define SysTick_LOAD_RELOAD_Msk   (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)
 
#define SysTick_VAL_CURRENT_Pos   0U
 
#define SysTick_VAL_CURRENT_Msk   (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)
 
#define SysTick_CALIB_NOREF_Pos   31U
 
#define SysTick_CALIB_NOREF_Msk   (1UL << SysTick_CALIB_NOREF_Pos)
 
#define SysTick_CALIB_SKEW_Pos   30U
 
#define SysTick_CALIB_SKEW_Msk   (1UL << SysTick_CALIB_SKEW_Pos)
 
#define SysTick_CALIB_TENMS_Pos   0U
 
#define SysTick_CALIB_TENMS_Msk   (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)
 
#define DWT_CTRL_NUMCOMP_Pos   28U
 
#define DWT_CTRL_NUMCOMP_Msk   (0xFUL << DWT_CTRL_NUMCOMP_Pos)
 
#define DWT_CTRL_NOTRCPKT_Pos   27U
 
#define DWT_CTRL_NOTRCPKT_Msk   (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
 
#define DWT_CTRL_NOEXTTRIG_Pos   26U
 
#define DWT_CTRL_NOEXTTRIG_Msk   (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
 
#define DWT_CTRL_NOCYCCNT_Pos   25U
 
#define DWT_CTRL_NOCYCCNT_Msk   (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
 
#define DWT_CTRL_NOPRFCNT_Pos   24U
 
#define DWT_CTRL_NOPRFCNT_Msk   (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
 
#define DWT_CTRL_CYCEVTENA_Pos   22U
 
#define DWT_CTRL_CYCEVTENA_Msk   (0x1UL << DWT_CTRL_CYCEVTENA_Pos)
 
#define DWT_CTRL_FOLDEVTENA_Pos   21U
 
#define DWT_CTRL_FOLDEVTENA_Msk   (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)
 
#define DWT_CTRL_LSUEVTENA_Pos   20U
 
#define DWT_CTRL_LSUEVTENA_Msk   (0x1UL << DWT_CTRL_LSUEVTENA_Pos)
 
#define DWT_CTRL_SLEEPEVTENA_Pos   19U
 
#define DWT_CTRL_SLEEPEVTENA_Msk   (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)
 
#define DWT_CTRL_EXCEVTENA_Pos   18U
 
#define DWT_CTRL_EXCEVTENA_Msk   (0x1UL << DWT_CTRL_EXCEVTENA_Pos)
 
#define DWT_CTRL_CPIEVTENA_Pos   17U
 
#define DWT_CTRL_CPIEVTENA_Msk   (0x1UL << DWT_CTRL_CPIEVTENA_Pos)
 
#define DWT_CTRL_EXCTRCENA_Pos   16U
 
#define DWT_CTRL_EXCTRCENA_Msk   (0x1UL << DWT_CTRL_EXCTRCENA_Pos)
 
#define DWT_CTRL_PCSAMPLENA_Pos   12U
 
#define DWT_CTRL_PCSAMPLENA_Msk   (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)
 
#define DWT_CTRL_SYNCTAP_Pos   10U
 
#define DWT_CTRL_SYNCTAP_Msk   (0x3UL << DWT_CTRL_SYNCTAP_Pos)
 
#define DWT_CTRL_CYCTAP_Pos   9U
 
#define DWT_CTRL_CYCTAP_Msk   (0x1UL << DWT_CTRL_CYCTAP_Pos)
 
#define DWT_CTRL_POSTINIT_Pos   5U
 
#define DWT_CTRL_POSTINIT_Msk   (0xFUL << DWT_CTRL_POSTINIT_Pos)
 
#define DWT_CTRL_POSTPRESET_Pos   1U
 
#define DWT_CTRL_POSTPRESET_Msk   (0xFUL << DWT_CTRL_POSTPRESET_Pos)
 
#define DWT_CTRL_CYCCNTENA_Pos   0U
 
#define DWT_CTRL_CYCCNTENA_Msk   (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)
 
#define DWT_CPICNT_CPICNT_Pos   0U
 
#define DWT_CPICNT_CPICNT_Msk   (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)
 
#define DWT_EXCCNT_EXCCNT_Pos   0U
 
#define DWT_EXCCNT_EXCCNT_Msk   (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)
 
#define DWT_SLEEPCNT_SLEEPCNT_Pos   0U
 
#define DWT_SLEEPCNT_SLEEPCNT_Msk   (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)
 
#define DWT_LSUCNT_LSUCNT_Pos   0U
 
#define DWT_LSUCNT_LSUCNT_Msk   (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)
 
#define DWT_FOLDCNT_FOLDCNT_Pos   0U
 
#define DWT_FOLDCNT_FOLDCNT_Msk   (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)
 
#define DWT_MASK_MASK_Pos   0U
 
#define DWT_MASK_MASK_Msk   (0x1FUL /*<< DWT_MASK_MASK_Pos*/)
 
#define DWT_FUNCTION_MATCHED_Pos   24U
 
#define DWT_FUNCTION_MATCHED_Msk   (0x1UL << DWT_FUNCTION_MATCHED_Pos)
 
#define DWT_FUNCTION_DATAVADDR1_Pos   16U
 
#define DWT_FUNCTION_DATAVADDR1_Msk   (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)
 
#define DWT_FUNCTION_DATAVADDR0_Pos   12U
 
#define DWT_FUNCTION_DATAVADDR0_Msk   (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)
 
#define DWT_FUNCTION_DATAVSIZE_Pos   10U
 
#define DWT_FUNCTION_DATAVSIZE_Msk   (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
 
#define DWT_FUNCTION_LNK1ENA_Pos   9U
 
#define DWT_FUNCTION_LNK1ENA_Msk   (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)
 
#define DWT_FUNCTION_DATAVMATCH_Pos   8U
 
#define DWT_FUNCTION_DATAVMATCH_Msk   (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)
 
#define DWT_FUNCTION_CYCMATCH_Pos   7U
 
#define DWT_FUNCTION_CYCMATCH_Msk   (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)
 
#define DWT_FUNCTION_EMITRANGE_Pos   5U
 
#define DWT_FUNCTION_EMITRANGE_Msk   (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)
 
#define DWT_FUNCTION_FUNCTION_Pos   0U
 
#define DWT_FUNCTION_FUNCTION_Msk   (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)
 
#define TPI_ACPR_PRESCALER_Pos   0U
 
#define TPI_ACPR_PRESCALER_Msk   (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)
 
#define TPI_SPPR_TXMODE_Pos   0U
 
#define TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
 
#define TPI_FFSR_FtNonStop_Pos   3U
 
#define TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)
 
#define TPI_FFSR_TCPresent_Pos   2U
 
#define TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)
 
#define TPI_FFSR_FtStopped_Pos   1U
 
#define TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)
 
#define TPI_FFSR_FlInProg_Pos   0U
 
#define TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
 
#define TPI_FFCR_TrigIn_Pos   8U
 
#define TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)
 
#define TPI_FFCR_EnFCont_Pos   1U
 
#define TPI_FFCR_EnFCont_Msk   (0x1UL << TPI_FFCR_EnFCont_Pos)
 
#define TPI_TRIGGER_TRIGGER_Pos   0U
 
#define TPI_TRIGGER_TRIGGER_Msk   (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)
 
#define TPI_FIFO0_ITM_ATVALID_Pos   29U
 
#define TPI_FIFO0_ITM_ATVALID_Msk   (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)
 
#define TPI_FIFO0_ITM_bytecount_Pos   27U
 
#define TPI_FIFO0_ITM_bytecount_Msk   (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)
 
#define TPI_FIFO0_ETM_ATVALID_Pos   26U
 
#define TPI_FIFO0_ETM_ATVALID_Msk   (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)
 
#define TPI_FIFO0_ETM_bytecount_Pos   24U
 
#define TPI_FIFO0_ETM_bytecount_Msk   (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)
 
#define TPI_FIFO0_ETM2_Pos   16U
 
#define TPI_FIFO0_ETM2_Msk   (0xFFUL << TPI_FIFO0_ETM2_Pos)
 
#define TPI_FIFO0_ETM1_Pos   8U
 
#define TPI_FIFO0_ETM1_Msk   (0xFFUL << TPI_FIFO0_ETM1_Pos)
 
#define TPI_FIFO0_ETM0_Pos   0U
 
#define TPI_FIFO0_ETM0_Msk   (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)
 
#define TPI_ITATBCTR2_ATREADY2_Pos   0U
 
#define TPI_ITATBCTR2_ATREADY2_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)
 
#define TPI_ITATBCTR2_ATREADY1_Pos   0U
 
#define TPI_ITATBCTR2_ATREADY1_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)
 
#define TPI_FIFO1_ITM_ATVALID_Pos   29U
 
#define TPI_FIFO1_ITM_ATVALID_Msk   (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)
 
#define TPI_FIFO1_ITM_bytecount_Pos   27U
 
#define TPI_FIFO1_ITM_bytecount_Msk   (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)
 
#define TPI_FIFO1_ETM_ATVALID_Pos   26U
 
#define TPI_FIFO1_ETM_ATVALID_Msk   (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)
 
#define TPI_FIFO1_ETM_bytecount_Pos   24U
 
#define TPI_FIFO1_ETM_bytecount_Msk   (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)
 
#define TPI_FIFO1_ITM2_Pos   16U
 
#define TPI_FIFO1_ITM2_Msk   (0xFFUL << TPI_FIFO1_ITM2_Pos)
 
#define TPI_FIFO1_ITM1_Pos   8U
 
#define TPI_FIFO1_ITM1_Msk   (0xFFUL << TPI_FIFO1_ITM1_Pos)
 
#define TPI_FIFO1_ITM0_Pos   0U
 
#define TPI_FIFO1_ITM0_Msk   (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)
 
#define TPI_ITATBCTR0_ATREADY2_Pos   0U
 
#define TPI_ITATBCTR0_ATREADY2_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)
 
#define TPI_ITATBCTR0_ATREADY1_Pos   0U
 
#define TPI_ITATBCTR0_ATREADY1_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)
 
#define TPI_ITCTRL_Mode_Pos   0U
 
#define TPI_ITCTRL_Mode_Msk   (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)
 
#define TPI_DEVID_NRZVALID_Pos   11U
 
#define TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)
 
#define TPI_DEVID_MANCVALID_Pos   10U
 
#define TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)
 
#define TPI_DEVID_PTINVALID_Pos   9U
 
#define TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)
 
#define TPI_DEVID_MinBufSz_Pos   6U
 
#define TPI_DEVID_MinBufSz_Msk   (0x7UL << TPI_DEVID_MinBufSz_Pos)
 
#define TPI_DEVID_AsynClkIn_Pos   5U
 
#define TPI_DEVID_AsynClkIn_Msk   (0x1UL << TPI_DEVID_AsynClkIn_Pos)
 
#define TPI_DEVID_NrTraceInput_Pos   0U
 
#define TPI_DEVID_NrTraceInput_Msk   (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)
 
#define TPI_DEVTYPE_SubType_Pos   4U
 
#define TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
 
#define TPI_DEVTYPE_MajorType_Pos   0U
 
#define TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)
 
#define MPU_TYPE_IREGION_Pos   16U
 
#define MPU_TYPE_IREGION_Msk   (0xFFUL << MPU_TYPE_IREGION_Pos)
 
#define MPU_TYPE_DREGION_Pos   8U
 
#define MPU_TYPE_DREGION_Msk   (0xFFUL << MPU_TYPE_DREGION_Pos)
 
#define MPU_TYPE_SEPARATE_Pos   0U
 
#define MPU_TYPE_SEPARATE_Msk   (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)
 
#define MPU_CTRL_PRIVDEFENA_Pos   2U
 
#define MPU_CTRL_PRIVDEFENA_Msk   (1UL << MPU_CTRL_PRIVDEFENA_Pos)
 
#define MPU_CTRL_HFNMIENA_Pos   1U
 
#define MPU_CTRL_HFNMIENA_Msk   (1UL << MPU_CTRL_HFNMIENA_Pos)
 
#define MPU_CTRL_ENABLE_Pos   0U
 
#define MPU_CTRL_ENABLE_Msk   (1UL /*<< MPU_CTRL_ENABLE_Pos*/)
 
#define MPU_RNR_REGION_Pos   0U
 
#define MPU_RNR_REGION_Msk   (0xFFUL /*<< MPU_RNR_REGION_Pos*/)
 
#define MPU_RBAR_ADDR_Pos   5U
 
#define MPU_RBAR_ADDR_Msk   (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)
 
#define MPU_RBAR_VALID_Pos   4U
 
#define MPU_RBAR_VALID_Msk   (1UL << MPU_RBAR_VALID_Pos)
 
#define MPU_RBAR_REGION_Pos   0U
 
#define MPU_RBAR_REGION_Msk   (0xFUL /*<< MPU_RBAR_REGION_Pos*/)
 
#define MPU_RASR_ATTRS_Pos   16U
 
#define MPU_RASR_ATTRS_Msk   (0xFFFFUL << MPU_RASR_ATTRS_Pos)
 
#define MPU_RASR_XN_Pos   28U
 
#define MPU_RASR_XN_Msk   (1UL << MPU_RASR_XN_Pos)
 
#define MPU_RASR_AP_Pos   24U
 
#define MPU_RASR_AP_Msk   (0x7UL << MPU_RASR_AP_Pos)
 
#define MPU_RASR_TEX_Pos   19U
 
#define MPU_RASR_TEX_Msk   (0x7UL << MPU_RASR_TEX_Pos)
 
#define MPU_RASR_S_Pos   18U
 
#define MPU_RASR_S_Msk   (1UL << MPU_RASR_S_Pos)
 
#define MPU_RASR_C_Pos   17U
 
#define MPU_RASR_C_Msk   (1UL << MPU_RASR_C_Pos)
 
#define MPU_RASR_B_Pos   16U
 
#define MPU_RASR_B_Msk   (1UL << MPU_RASR_B_Pos)
 
#define MPU_RASR_SRD_Pos   8U
 
#define MPU_RASR_SRD_Msk   (0xFFUL << MPU_RASR_SRD_Pos)
 
#define MPU_RASR_SIZE_Pos   1U
 
#define MPU_RASR_SIZE_Msk   (0x1FUL << MPU_RASR_SIZE_Pos)
 
#define MPU_RASR_ENABLE_Pos   0U
 
#define MPU_RASR_ENABLE_Msk   (1UL /*<< MPU_RASR_ENABLE_Pos*/)
 
#define CoreDebug_DHCSR_DBGKEY_Pos   16U
 
#define CoreDebug_DHCSR_DBGKEY_Msk   (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
 
#define CoreDebug_DHCSR_S_RESET_ST_Pos   25U
 
#define CoreDebug_DHCSR_S_RESET_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
 
#define CoreDebug_DHCSR_S_RETIRE_ST_Pos   24U
 
#define CoreDebug_DHCSR_S_RETIRE_ST_Msk   (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
 
#define CoreDebug_DHCSR_S_LOCKUP_Pos   19U
 
#define CoreDebug_DHCSR_S_LOCKUP_Msk   (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
 
#define CoreDebug_DHCSR_S_SLEEP_Pos   18U
 
#define CoreDebug_DHCSR_S_SLEEP_Msk   (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
 
#define CoreDebug_DHCSR_S_HALT_Pos   17U
 
#define CoreDebug_DHCSR_S_HALT_Msk   (1UL << CoreDebug_DHCSR_S_HALT_Pos)
 
#define CoreDebug_DHCSR_S_REGRDY_Pos   16U
 
#define CoreDebug_DHCSR_S_REGRDY_Msk   (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
 
#define CoreDebug_DHCSR_C_SNAPSTALL_Pos   5U
 
#define CoreDebug_DHCSR_C_SNAPSTALL_Msk   (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)
 
#define CoreDebug_DHCSR_C_MASKINTS_Pos   3U
 
#define CoreDebug_DHCSR_C_MASKINTS_Msk   (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
 
#define CoreDebug_DHCSR_C_STEP_Pos   2U
 
#define CoreDebug_DHCSR_C_STEP_Msk   (1UL << CoreDebug_DHCSR_C_STEP_Pos)
 
#define CoreDebug_DHCSR_C_HALT_Pos   1U
 
#define CoreDebug_DHCSR_C_HALT_Msk   (1UL << CoreDebug_DHCSR_C_HALT_Pos)
 
#define CoreDebug_DHCSR_C_DEBUGEN_Pos   0U
 
#define CoreDebug_DHCSR_C_DEBUGEN_Msk   (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)
 
#define CoreDebug_DCRSR_REGWnR_Pos   16U
 
#define CoreDebug_DCRSR_REGWnR_Msk   (1UL << CoreDebug_DCRSR_REGWnR_Pos)
 
#define CoreDebug_DCRSR_REGSEL_Pos   0U
 
#define CoreDebug_DCRSR_REGSEL_Msk   (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)
 
#define CoreDebug_DEMCR_TRCENA_Pos   24U
 
#define CoreDebug_DEMCR_TRCENA_Msk   (1UL << CoreDebug_DEMCR_TRCENA_Pos)
 
#define CoreDebug_DEMCR_MON_REQ_Pos   19U
 
#define CoreDebug_DEMCR_MON_REQ_Msk   (1UL << CoreDebug_DEMCR_MON_REQ_Pos)
 
#define CoreDebug_DEMCR_MON_STEP_Pos   18U
 
#define CoreDebug_DEMCR_MON_STEP_Msk   (1UL << CoreDebug_DEMCR_MON_STEP_Pos)
 
#define CoreDebug_DEMCR_MON_PEND_Pos   17U
 
#define CoreDebug_DEMCR_MON_PEND_Msk   (1UL << CoreDebug_DEMCR_MON_PEND_Pos)
 
#define CoreDebug_DEMCR_MON_EN_Pos   16U
 
#define CoreDebug_DEMCR_MON_EN_Msk   (1UL << CoreDebug_DEMCR_MON_EN_Pos)
 
#define CoreDebug_DEMCR_VC_HARDERR_Pos   10U
 
#define CoreDebug_DEMCR_VC_HARDERR_Msk   (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
 
#define CoreDebug_DEMCR_VC_INTERR_Pos   9U
 
#define CoreDebug_DEMCR_VC_INTERR_Msk   (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)
 
#define CoreDebug_DEMCR_VC_BUSERR_Pos   8U
 
#define CoreDebug_DEMCR_VC_BUSERR_Msk   (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)
 
#define CoreDebug_DEMCR_VC_STATERR_Pos   7U
 
#define CoreDebug_DEMCR_VC_STATERR_Msk   (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)
 
#define CoreDebug_DEMCR_VC_CHKERR_Pos   6U
 
#define CoreDebug_DEMCR_VC_CHKERR_Msk   (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)
 
#define CoreDebug_DEMCR_VC_NOCPERR_Pos   5U
 
#define CoreDebug_DEMCR_VC_NOCPERR_Msk   (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)
 
#define CoreDebug_DEMCR_VC_MMERR_Pos   4U
 
#define CoreDebug_DEMCR_VC_MMERR_Msk   (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)
 
#define CoreDebug_DEMCR_VC_CORERESET_Pos   0U
 
#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)
 
#define _VAL2FLD(field, value)
 Mask and shift a bit field value for use in a register bit range.
 
#define _FLD2VAL(field, value)
 Mask and shift a register value to extract a bit filed value.
 
#define FPU_BASE   (SCS_BASE + 0x0F30UL)
 
#define FPU   ((FPU_Type *) FPU_BASE )
 
#define SCS_BASE   (0xE000E000UL)
 
#define ITM_BASE   (0xE0000000UL)
 
#define DWT_BASE   (0xE0001000UL)
 
#define TPI_BASE   (0xE0040000UL)
 
#define CoreDebug_BASE   (0xE000EDF0UL)
 
#define SysTick_BASE   (SCS_BASE + 0x0010UL)
 
#define NVIC_BASE   (SCS_BASE + 0x0100UL)
 
#define SCB_BASE   (SCS_BASE + 0x0D00UL)
 
#define SCnSCB   ((SCnSCB_Type *) SCS_BASE )
 
#define SCB   ((SCB_Type *) SCB_BASE )
 
#define SysTick   ((SysTick_Type *) SysTick_BASE )
 
#define NVIC   ((NVIC_Type *) NVIC_BASE )
 
#define ITM   ((ITM_Type *) ITM_BASE )
 
#define DWT   ((DWT_Type *) DWT_BASE )
 
#define TPI   ((TPI_Type *) TPI_BASE )
 
#define CoreDebug   ((CoreDebug_Type *) CoreDebug_BASE)
 
#define MPU_BASE   (SCS_BASE + 0x0D90UL)
 
#define MPU   ((MPU_Type *) MPU_BASE )
 
#define EXC_RETURN_HANDLER_FPU   (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */
 
#define EXC_RETURN_THREAD_MSP_FPU   (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */
 
#define EXC_RETURN_THREAD_PSP_FPU   (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */
 
#define NVIC_SetPriorityGrouping   __NVIC_SetPriorityGrouping
 
#define NVIC_GetPriorityGrouping   __NVIC_GetPriorityGrouping
 
#define NVIC_EnableIRQ   __NVIC_EnableIRQ
 
#define NVIC_GetEnableIRQ   __NVIC_GetEnableIRQ
 
#define NVIC_DisableIRQ   __NVIC_DisableIRQ
 
#define NVIC_GetPendingIRQ   __NVIC_GetPendingIRQ
 
#define NVIC_SetPendingIRQ   __NVIC_SetPendingIRQ
 
#define NVIC_ClearPendingIRQ   __NVIC_ClearPendingIRQ
 
#define NVIC_GetActive   __NVIC_GetActive
 
#define NVIC_SetPriority   __NVIC_SetPriority
 
#define NVIC_GetPriority   __NVIC_GetPriority
 
#define NVIC_SystemReset   __NVIC_SystemReset
 
#define NVIC_SetVector   __NVIC_SetVector
 
#define NVIC_GetVector   __NVIC_GetVector
 
#define NVIC_USER_IRQ_OFFSET   16
 
#define EXC_RETURN_HANDLER   (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
 
#define EXC_RETURN_THREAD_MSP   (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
 
#define EXC_RETURN_THREAD_PSP   (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
 
#define SCnSCB_ICTR_INTLINESNUM_Pos   0U
 
#define SCnSCB_ICTR_INTLINESNUM_Msk   (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)
 
#define ITM_STIM_DISABLED_Pos   1U
 
#define ITM_STIM_DISABLED_Msk   (0x1UL << ITM_STIM_DISABLED_Pos)
 
#define ITM_STIM_FIFOREADY_Pos   0U
 
#define ITM_STIM_FIFOREADY_Msk   (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)
 
#define ITM_TCR_TRACEBUSID_Pos   16U
 
#define ITM_TCR_TRACEBUSID_Msk   (0x7FUL << ITM_TCR_TRACEBUSID_Pos)
 
#define ITM_TCR_TSPRESCALE_Pos   8U
 
#define ITM_TCR_TSPRESCALE_Msk   (3UL << ITM_TCR_TSPRESCALE_Pos)
 
#define ITM_TCR_STALLENA_Pos   5U
 
#define ITM_TCR_STALLENA_Msk   (1UL << ITM_TCR_STALLENA_Pos)
 
#define ITM_TPR_PRIVMASK_Pos   0U
 
#define ITM_TPR_PRIVMASK_Msk   (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
 
#define ITM_TCR_BUSY_Pos   23U
 
#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)
 
#define ITM_TCR_TraceBusID_Pos   16U
 
#define ITM_TCR_TraceBusID_Msk   (0x7FUL << ITM_TCR_TraceBusID_Pos)
 
#define ITM_TCR_GTSFREQ_Pos   10U
 
#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)
 
#define ITM_TCR_TSPrescale_Pos   8U
 
#define ITM_TCR_TSPrescale_Msk   (3UL << ITM_TCR_TSPrescale_Pos)
 
#define ITM_TCR_SWOENA_Pos   4U
 
#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)
 
#define ITM_TCR_DWTENA_Pos   3U
 
#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)
 
#define ITM_TCR_SYNCENA_Pos   2U
 
#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)
 
#define ITM_TCR_TSENA_Pos   1U
 
#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)
 
#define ITM_TCR_ITMENA_Pos   0U
 
#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)
 
#define ITM_IWR_ATVALIDM_Pos   0U
 
#define ITM_IWR_ATVALIDM_Msk   (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)
 
#define ITM_IRR_ATREADYM_Pos   0U
 
#define ITM_IRR_ATREADYM_Msk   (1UL /*<< ITM_IRR_ATREADYM_Pos*/)
 
#define ITM_IMCR_INTEGRATION_Pos   0U
 
#define ITM_IMCR_INTEGRATION_Msk   (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)
 
#define ITM_LSR_ByteAcc_Pos   2U
 
#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)
 
#define ITM_LSR_Access_Pos   1U
 
#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)
 
#define ITM_LSR_Present_Pos   0U
 
#define ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)
 
#define FPU_FPCCR_LSPENS_Pos   29U
 
#define FPU_FPCCR_LSPENS_Msk   (1UL << FPU_FPCCR_LSPENS_Pos)
 
#define FPU_FPCCR_CLRONRET_Pos   28U
 
#define FPU_FPCCR_CLRONRET_Msk   (1UL << FPU_FPCCR_CLRONRET_Pos)
 
#define FPU_FPCCR_CLRONRETS_Pos   27U
 
#define FPU_FPCCR_CLRONRETS_Msk   (1UL << FPU_FPCCR_CLRONRETS_Pos)
 
#define FPU_FPCCR_TS_Pos   26U
 
#define FPU_FPCCR_TS_Msk   (1UL << FPU_FPCCR_TS_Pos)
 
#define FPU_FPCCR_UFRDY_Pos   10U
 
#define FPU_FPCCR_UFRDY_Msk   (1UL << FPU_FPCCR_UFRDY_Pos)
 
#define FPU_FPCCR_SPLIMVIOL_Pos   9U
 
#define FPU_FPCCR_SPLIMVIOL_Msk   (1UL << FPU_FPCCR_SPLIMVIOL_Pos)
 
#define FPU_FPCCR_SFRDY_Pos   7U
 
#define FPU_FPCCR_SFRDY_Msk   (1UL << FPU_FPCCR_SFRDY_Pos)
 
#define FPU_FPCCR_S_Pos   2U
 
#define FPU_FPCCR_S_Msk   (1UL << FPU_FPCCR_S_Pos)
 
#define FPU_FPCCR_ASPEN_Pos   31U
 
#define FPU_FPCCR_ASPEN_Msk   (1UL << FPU_FPCCR_ASPEN_Pos)
 
#define FPU_FPCCR_LSPEN_Pos   30U
 
#define FPU_FPCCR_LSPEN_Msk   (1UL << FPU_FPCCR_LSPEN_Pos)
 
#define FPU_FPCCR_MONRDY_Pos   8U
 
#define FPU_FPCCR_MONRDY_Msk   (1UL << FPU_FPCCR_MONRDY_Pos)
 
#define FPU_FPCCR_BFRDY_Pos   6U
 
#define FPU_FPCCR_BFRDY_Msk   (1UL << FPU_FPCCR_BFRDY_Pos)
 
#define FPU_FPCCR_MMRDY_Pos   5U
 
#define FPU_FPCCR_MMRDY_Msk   (1UL << FPU_FPCCR_MMRDY_Pos)
 
#define FPU_FPCCR_HFRDY_Pos   4U
 
#define FPU_FPCCR_HFRDY_Msk   (1UL << FPU_FPCCR_HFRDY_Pos)
 
#define FPU_FPCCR_THREAD_Pos   3U
 
#define FPU_FPCCR_THREAD_Msk   (1UL << FPU_FPCCR_THREAD_Pos)
 
#define FPU_FPCCR_USER_Pos   1U
 
#define FPU_FPCCR_USER_Msk   (1UL << FPU_FPCCR_USER_Pos)
 
#define FPU_FPCCR_LSPACT_Pos   0U
 
#define FPU_FPCCR_LSPACT_Msk   (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)
 
#define FPU_FPCAR_ADDRESS_Pos   3U
 
#define FPU_FPCAR_ADDRESS_Msk   (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
 
#define FPU_FPDSCR_AHP_Pos   26U
 
#define FPU_FPDSCR_AHP_Msk   (1UL << FPU_FPDSCR_AHP_Pos)
 
#define FPU_FPDSCR_DN_Pos   25U
 
#define FPU_FPDSCR_DN_Msk   (1UL << FPU_FPDSCR_DN_Pos)
 
#define FPU_FPDSCR_FZ_Pos   24U
 
#define FPU_FPDSCR_FZ_Msk   (1UL << FPU_FPDSCR_FZ_Pos)
 
#define FPU_FPDSCR_RMode_Pos   22U
 
#define FPU_FPDSCR_RMode_Msk   (3UL << FPU_FPDSCR_RMode_Pos)
 
#define FPU_MVFR0_FP_rounding_modes_Pos   28U
 
#define FPU_MVFR0_FP_rounding_modes_Msk   (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)
 
#define FPU_MVFR0_Short_vectors_Pos   24U
 
#define FPU_MVFR0_Short_vectors_Msk   (0xFUL << FPU_MVFR0_Short_vectors_Pos)
 
#define FPU_MVFR0_Square_root_Pos   20U
 
#define FPU_MVFR0_Square_root_Msk   (0xFUL << FPU_MVFR0_Square_root_Pos)
 
#define FPU_MVFR0_Divide_Pos   16U
 
#define FPU_MVFR0_Divide_Msk   (0xFUL << FPU_MVFR0_Divide_Pos)
 
#define FPU_MVFR0_FP_excep_trapping_Pos   12U
 
#define FPU_MVFR0_FP_excep_trapping_Msk   (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)
 
#define FPU_MVFR0_Double_precision_Pos   8U
 
#define FPU_MVFR0_Double_precision_Msk   (0xFUL << FPU_MVFR0_Double_precision_Pos)
 
#define FPU_MVFR0_Single_precision_Pos   4U
 
#define FPU_MVFR0_Single_precision_Msk   (0xFUL << FPU_MVFR0_Single_precision_Pos)
 
#define FPU_MVFR0_A_SIMD_registers_Pos   0U
 
#define FPU_MVFR0_A_SIMD_registers_Msk   (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)
 
#define FPU_MVFR1_FP_fused_MAC_Pos   28U
 
#define FPU_MVFR1_FP_fused_MAC_Msk   (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)
 
#define FPU_MVFR1_FP_HPFP_Pos   24U
 
#define FPU_MVFR1_FP_HPFP_Msk   (0xFUL << FPU_MVFR1_FP_HPFP_Pos)
 
#define FPU_MVFR1_D_NaN_mode_Pos   4U
 
#define FPU_MVFR1_D_NaN_mode_Msk   (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)
 
#define FPU_MVFR1_FtZ_mode_Pos   0U
 
#define FPU_MVFR1_FtZ_mode_Msk   (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)
 
#define APSR_N_Pos   31U
 
#define APSR_N_Msk   (1UL << APSR_N_Pos)
 
#define APSR_Z_Pos   30U
 
#define APSR_Z_Msk   (1UL << APSR_Z_Pos)
 
#define APSR_C_Pos   29U
 
#define APSR_C_Msk   (1UL << APSR_C_Pos)
 
#define APSR_V_Pos   28U
 
#define APSR_V_Msk   (1UL << APSR_V_Pos)
 
#define IPSR_ISR_Pos   0U
 
#define IPSR_ISR_Msk   (0x1FFUL /*<< IPSR_ISR_Pos*/)
 
#define xPSR_N_Pos   31U
 
#define xPSR_N_Msk   (1UL << xPSR_N_Pos)
 
#define xPSR_Z_Pos   30U
 
#define xPSR_Z_Msk   (1UL << xPSR_Z_Pos)
 
#define xPSR_C_Pos   29U
 
#define xPSR_C_Msk   (1UL << xPSR_C_Pos)
 
#define xPSR_V_Pos   28U
 
#define xPSR_V_Msk   (1UL << xPSR_V_Pos)
 
#define xPSR_T_Pos   24U
 
#define xPSR_T_Msk   (1UL << xPSR_T_Pos)
 
#define xPSR_ISR_Pos   0U
 
#define xPSR_ISR_Msk   (0x1FFUL /*<< xPSR_ISR_Pos*/)
 
#define CONTROL_SPSEL_Pos   1U
 
#define CONTROL_SPSEL_Msk   (1UL << CONTROL_SPSEL_Pos)
 
#define CONTROL_nPRIV_Pos   0U
 
#define CONTROL_nPRIV_Msk   (1UL /*<< CONTROL_nPRIV_Pos*/)
 
#define APSR_N_Pos   31U
 
#define APSR_N_Msk   (1UL << APSR_N_Pos)
 
#define APSR_Z_Pos   30U
 
#define APSR_Z_Msk   (1UL << APSR_Z_Pos)
 
#define APSR_C_Pos   29U
 
#define APSR_C_Msk   (1UL << APSR_C_Pos)
 
#define APSR_V_Pos   28U
 
#define APSR_V_Msk   (1UL << APSR_V_Pos)
 
#define APSR_Q_Pos   27U
 
#define APSR_Q_Msk   (1UL << APSR_Q_Pos)
 
#define IPSR_ISR_Pos   0U
 
#define IPSR_ISR_Msk   (0x1FFUL /*<< IPSR_ISR_Pos*/)
 
#define xPSR_N_Pos   31U
 
#define xPSR_N_Msk   (1UL << xPSR_N_Pos)
 
#define xPSR_Z_Pos   30U
 
#define xPSR_Z_Msk   (1UL << xPSR_Z_Pos)
 
#define xPSR_C_Pos   29U
 
#define xPSR_C_Msk   (1UL << xPSR_C_Pos)
 
#define xPSR_V_Pos   28U
 
#define xPSR_V_Msk   (1UL << xPSR_V_Pos)
 
#define xPSR_Q_Pos   27U
 
#define xPSR_Q_Msk   (1UL << xPSR_Q_Pos)
 
#define xPSR_T_Pos   24U
 
#define xPSR_T_Msk   (1UL << xPSR_T_Pos)
 
#define xPSR_ISR_Pos   0U
 
#define xPSR_ISR_Msk   (0x1FFUL /*<< xPSR_ISR_Pos*/)
 
#define CONTROL_SPSEL_Pos   1U
 
#define CONTROL_SPSEL_Msk   (1UL << CONTROL_SPSEL_Pos)
 
#define CONTROL_nPRIV_Pos   0U
 
#define CONTROL_nPRIV_Msk   (1UL /*<< CONTROL_nPRIV_Pos*/)
 
#define APSR_N_Pos   31U
 
#define APSR_N_Msk   (1UL << APSR_N_Pos)
 
#define APSR_Z_Pos   30U
 
#define APSR_Z_Msk   (1UL << APSR_Z_Pos)
 
#define APSR_C_Pos   29U
 
#define APSR_C_Msk   (1UL << APSR_C_Pos)
 
#define APSR_V_Pos   28U
 
#define APSR_V_Msk   (1UL << APSR_V_Pos)
 
#define IPSR_ISR_Pos   0U
 
#define IPSR_ISR_Msk   (0x1FFUL /*<< IPSR_ISR_Pos*/)
 
#define xPSR_N_Pos   31U
 
#define xPSR_N_Msk   (1UL << xPSR_N_Pos)
 
#define xPSR_Z_Pos   30U
 
#define xPSR_Z_Msk   (1UL << xPSR_Z_Pos)
 
#define xPSR_C_Pos   29U
 
#define xPSR_C_Msk   (1UL << xPSR_C_Pos)
 
#define xPSR_V_Pos   28U
 
#define xPSR_V_Msk   (1UL << xPSR_V_Pos)
 
#define xPSR_T_Pos   24U
 
#define xPSR_T_Msk   (1UL << xPSR_T_Pos)
 
#define xPSR_ISR_Pos   0U
 
#define xPSR_ISR_Msk   (0x1FFUL /*<< xPSR_ISR_Pos*/)
 
#define CONTROL_SPSEL_Pos   1U
 
#define CONTROL_SPSEL_Msk   (1UL << CONTROL_SPSEL_Pos)
 
#define APSR_N_Pos   31U
 
#define APSR_N_Msk   (1UL << APSR_N_Pos)
 
#define APSR_Z_Pos   30U
 
#define APSR_Z_Msk   (1UL << APSR_Z_Pos)
 
#define APSR_C_Pos   29U
 
#define APSR_C_Msk   (1UL << APSR_C_Pos)
 
#define APSR_V_Pos   28U
 
#define APSR_V_Msk   (1UL << APSR_V_Pos)
 
#define IPSR_ISR_Pos   0U
 
#define IPSR_ISR_Msk   (0x1FFUL /*<< IPSR_ISR_Pos*/)
 
#define xPSR_N_Pos   31U
 
#define xPSR_N_Msk   (1UL << xPSR_N_Pos)
 
#define xPSR_Z_Pos   30U
 
#define xPSR_Z_Msk   (1UL << xPSR_Z_Pos)
 
#define xPSR_C_Pos   29U
 
#define xPSR_C_Msk   (1UL << xPSR_C_Pos)
 
#define xPSR_V_Pos   28U
 
#define xPSR_V_Msk   (1UL << xPSR_V_Pos)
 
#define xPSR_T_Pos   24U
 
#define xPSR_T_Msk   (1UL << xPSR_T_Pos)
 
#define xPSR_ISR_Pos   0U
 
#define xPSR_ISR_Msk   (0x1FFUL /*<< xPSR_ISR_Pos*/)
 
#define CONTROL_SPSEL_Pos   1U
 
#define CONTROL_SPSEL_Msk   (1UL << CONTROL_SPSEL_Pos)
 
#define CONTROL_nPRIV_Pos   0U
 
#define CONTROL_nPRIV_Msk   (1UL /*<< CONTROL_nPRIV_Pos*/)
 
#define APSR_N_Pos   31U
 
#define APSR_N_Msk   (1UL << APSR_N_Pos)
 
#define APSR_Z_Pos   30U
 
#define APSR_Z_Msk   (1UL << APSR_Z_Pos)
 
#define APSR_C_Pos   29U
 
#define APSR_C_Msk   (1UL << APSR_C_Pos)
 
#define APSR_V_Pos   28U
 
#define APSR_V_Msk   (1UL << APSR_V_Pos)
 
#define IPSR_ISR_Pos   0U
 
#define IPSR_ISR_Msk   (0x1FFUL /*<< IPSR_ISR_Pos*/)
 
#define xPSR_N_Pos   31U
 
#define xPSR_N_Msk   (1UL << xPSR_N_Pos)
 
#define xPSR_Z_Pos   30U
 
#define xPSR_Z_Msk   (1UL << xPSR_Z_Pos)
 
#define xPSR_C_Pos   29U
 
#define xPSR_C_Msk   (1UL << xPSR_C_Pos)
 
#define xPSR_V_Pos   28U
 
#define xPSR_V_Msk   (1UL << xPSR_V_Pos)
 
#define xPSR_T_Pos   24U
 
#define xPSR_T_Msk   (1UL << xPSR_T_Pos)
 
#define xPSR_ISR_Pos   0U
 
#define xPSR_ISR_Msk   (0x1FFUL /*<< xPSR_ISR_Pos*/)
 
#define CONTROL_SPSEL_Pos   1U
 
#define CONTROL_SPSEL_Msk   (1UL << CONTROL_SPSEL_Pos)
 
#define APSR_N_Pos   31U
 
#define APSR_N_Msk   (1UL << APSR_N_Pos)
 
#define APSR_Z_Pos   30U
 
#define APSR_Z_Msk   (1UL << APSR_Z_Pos)
 
#define APSR_C_Pos   29U
 
#define APSR_C_Msk   (1UL << APSR_C_Pos)
 
#define APSR_V_Pos   28U
 
#define APSR_V_Msk   (1UL << APSR_V_Pos)
 
#define IPSR_ISR_Pos   0U
 
#define IPSR_ISR_Msk   (0x1FFUL /*<< IPSR_ISR_Pos*/)
 
#define xPSR_N_Pos   31U
 
#define xPSR_N_Msk   (1UL << xPSR_N_Pos)
 
#define xPSR_Z_Pos   30U
 
#define xPSR_Z_Msk   (1UL << xPSR_Z_Pos)
 
#define xPSR_C_Pos   29U
 
#define xPSR_C_Msk   (1UL << xPSR_C_Pos)
 
#define xPSR_V_Pos   28U
 
#define xPSR_V_Msk   (1UL << xPSR_V_Pos)
 
#define xPSR_T_Pos   24U
 
#define xPSR_T_Msk   (1UL << xPSR_T_Pos)
 
#define xPSR_ISR_Pos   0U
 
#define xPSR_ISR_Msk   (0x1FFUL /*<< xPSR_ISR_Pos*/)
 
#define CONTROL_SPSEL_Pos   1U
 
#define CONTROL_SPSEL_Msk   (1UL << CONTROL_SPSEL_Pos)
 
#define CONTROL_nPRIV_Pos   0U
 
#define CONTROL_nPRIV_Msk   (1UL /*<< CONTROL_nPRIV_Pos*/)
 
#define APSR_N_Pos   31U
 
#define APSR_N_Msk   (1UL << APSR_N_Pos)
 
#define APSR_Z_Pos   30U
 
#define APSR_Z_Msk   (1UL << APSR_Z_Pos)
 
#define APSR_C_Pos   29U
 
#define APSR_C_Msk   (1UL << APSR_C_Pos)
 
#define APSR_V_Pos   28U
 
#define APSR_V_Msk   (1UL << APSR_V_Pos)
 
#define APSR_Q_Pos   27U
 
#define APSR_Q_Msk   (1UL << APSR_Q_Pos)
 
#define IPSR_ISR_Pos   0U
 
#define IPSR_ISR_Msk   (0x1FFUL /*<< IPSR_ISR_Pos*/)
 
#define xPSR_N_Pos   31U
 
#define xPSR_N_Msk   (1UL << xPSR_N_Pos)
 
#define xPSR_Z_Pos   30U
 
#define xPSR_Z_Msk   (1UL << xPSR_Z_Pos)
 
#define xPSR_C_Pos   29U
 
#define xPSR_C_Msk   (1UL << xPSR_C_Pos)
 
#define xPSR_V_Pos   28U
 
#define xPSR_V_Msk   (1UL << xPSR_V_Pos)
 
#define xPSR_Q_Pos   27U
 
#define xPSR_Q_Msk   (1UL << xPSR_Q_Pos)
 
#define xPSR_ICI_IT_2_Pos   25U
 
#define xPSR_ICI_IT_2_Msk   (3UL << xPSR_ICI_IT_2_Pos)
 
#define xPSR_T_Pos   24U
 
#define xPSR_T_Msk   (1UL << xPSR_T_Pos)
 
#define xPSR_ICI_IT_1_Pos   10U
 
#define xPSR_ICI_IT_1_Msk   (0x3FUL << xPSR_ICI_IT_1_Pos)
 
#define xPSR_ISR_Pos   0U
 
#define xPSR_ISR_Msk   (0x1FFUL /*<< xPSR_ISR_Pos*/)
 
#define CONTROL_SPSEL_Pos   1U
 
#define CONTROL_SPSEL_Msk   (1UL << CONTROL_SPSEL_Pos)
 
#define CONTROL_nPRIV_Pos   0U
 
#define CONTROL_nPRIV_Msk   (1UL /*<< CONTROL_nPRIV_Pos*/)
 
#define APSR_N_Pos   31U
 
#define APSR_N_Msk   (1UL << APSR_N_Pos)
 
#define APSR_Z_Pos   30U
 
#define APSR_Z_Msk   (1UL << APSR_Z_Pos)
 
#define APSR_C_Pos   29U
 
#define APSR_C_Msk   (1UL << APSR_C_Pos)
 
#define APSR_V_Pos   28U
 
#define APSR_V_Msk   (1UL << APSR_V_Pos)
 
#define APSR_Q_Pos   27U
 
#define APSR_Q_Msk   (1UL << APSR_Q_Pos)
 
#define IPSR_ISR_Pos   0U
 
#define IPSR_ISR_Msk   (0x1FFUL /*<< IPSR_ISR_Pos*/)
 
#define xPSR_N_Pos   31U
 
#define xPSR_N_Msk   (1UL << xPSR_N_Pos)
 
#define xPSR_Z_Pos   30U
 
#define xPSR_Z_Msk   (1UL << xPSR_Z_Pos)
 
#define xPSR_C_Pos   29U
 
#define xPSR_C_Msk   (1UL << xPSR_C_Pos)
 
#define xPSR_V_Pos   28U
 
#define xPSR_V_Msk   (1UL << xPSR_V_Pos)
 
#define xPSR_Q_Pos   27U
 
#define xPSR_Q_Msk   (1UL << xPSR_Q_Pos)
 
#define xPSR_T_Pos   24U
 
#define xPSR_T_Msk   (1UL << xPSR_T_Pos)
 
#define xPSR_ISR_Pos   0U
 
#define xPSR_ISR_Msk   (0x1FFUL /*<< xPSR_ISR_Pos*/)
 
#define CONTROL_SPSEL_Pos   1U
 
#define CONTROL_SPSEL_Msk   (1UL << CONTROL_SPSEL_Pos)
 
#define CONTROL_nPRIV_Pos   0U
 
#define CONTROL_nPRIV_Msk   (1UL /*<< CONTROL_nPRIV_Pos*/)
 
#define APSR_N_Pos   31U
 
#define APSR_N_Msk   (1UL << APSR_N_Pos)
 
#define APSR_Z_Pos   30U
 
#define APSR_Z_Msk   (1UL << APSR_Z_Pos)
 
#define APSR_C_Pos   29U
 
#define APSR_C_Msk   (1UL << APSR_C_Pos)
 
#define APSR_V_Pos   28U
 
#define APSR_V_Msk   (1UL << APSR_V_Pos)
 
#define APSR_Q_Pos   27U
 
#define APSR_Q_Msk   (1UL << APSR_Q_Pos)
 
#define IPSR_ISR_Pos   0U
 
#define IPSR_ISR_Msk   (0x1FFUL /*<< IPSR_ISR_Pos*/)
 
#define xPSR_N_Pos   31U
 
#define xPSR_N_Msk   (1UL << xPSR_N_Pos)
 
#define xPSR_Z_Pos   30U
 
#define xPSR_Z_Msk   (1UL << xPSR_Z_Pos)
 
#define xPSR_C_Pos   29U
 
#define xPSR_C_Msk   (1UL << xPSR_C_Pos)
 
#define xPSR_V_Pos   28U
 
#define xPSR_V_Msk   (1UL << xPSR_V_Pos)
 
#define xPSR_Q_Pos   27U
 
#define xPSR_Q_Msk   (1UL << xPSR_Q_Pos)
 
#define xPSR_ICI_IT_2_Pos   25U
 
#define xPSR_ICI_IT_2_Msk   (3UL << xPSR_ICI_IT_2_Pos)
 
#define xPSR_T_Pos   24U
 
#define xPSR_T_Msk   (1UL << xPSR_T_Pos)
 
#define xPSR_ICI_IT_1_Pos   10U
 
#define xPSR_ICI_IT_1_Msk   (0x3FUL << xPSR_ICI_IT_1_Pos)
 
#define xPSR_ISR_Pos   0U
 
#define xPSR_ISR_Msk   (0x1FFUL /*<< xPSR_ISR_Pos*/)
 
#define CONTROL_SPSEL_Pos   1U
 
#define CONTROL_SPSEL_Msk   (1UL << CONTROL_SPSEL_Pos)
 
#define CONTROL_nPRIV_Pos   0U
 
#define CONTROL_nPRIV_Msk   (1UL /*<< CONTROL_nPRIV_Pos*/)
 
#define APSR_N_Pos   31U
 
#define APSR_N_Msk   (1UL << APSR_N_Pos)
 
#define APSR_Z_Pos   30U
 
#define APSR_Z_Msk   (1UL << APSR_Z_Pos)
 
#define APSR_C_Pos   29U
 
#define APSR_C_Msk   (1UL << APSR_C_Pos)
 
#define APSR_V_Pos   28U
 
#define APSR_V_Msk   (1UL << APSR_V_Pos)
 
#define APSR_Q_Pos   27U
 
#define APSR_Q_Msk   (1UL << APSR_Q_Pos)
 
#define IPSR_ISR_Pos   0U
 
#define IPSR_ISR_Msk   (0x1FFUL /*<< IPSR_ISR_Pos*/)
 
#define xPSR_N_Pos   31U
 
#define xPSR_N_Msk   (1UL << xPSR_N_Pos)
 
#define xPSR_Z_Pos   30U
 
#define xPSR_Z_Msk   (1UL << xPSR_Z_Pos)
 
#define xPSR_C_Pos   29U
 
#define xPSR_C_Msk   (1UL << xPSR_C_Pos)
 
#define xPSR_V_Pos   28U
 
#define xPSR_V_Msk   (1UL << xPSR_V_Pos)
 
#define xPSR_Q_Pos   27U
 
#define xPSR_Q_Msk   (1UL << xPSR_Q_Pos)
 
#define xPSR_ICI_IT_2_Pos   25U
 
#define xPSR_ICI_IT_2_Msk   (3UL << xPSR_ICI_IT_2_Pos)
 
#define xPSR_T_Pos   24U
 
#define xPSR_T_Msk   (1UL << xPSR_T_Pos)
 
#define xPSR_ICI_IT_1_Pos   10U
 
#define xPSR_ICI_IT_1_Msk   (0x3FUL << xPSR_ICI_IT_1_Pos)
 
#define xPSR_ISR_Pos   0U
 
#define xPSR_ISR_Msk   (0x1FFUL /*<< xPSR_ISR_Pos*/)
 
#define CONTROL_SPSEL_Pos   1U
 
#define CONTROL_SPSEL_Msk   (1UL << CONTROL_SPSEL_Pos)
 
#define CONTROL_nPRIV_Pos   0U
 
#define CONTROL_nPRIV_Msk   (1UL /*<< CONTROL_nPRIV_Pos*/)
 
#define APSR_N_Pos   31U
 
#define APSR_N_Msk   (1UL << APSR_N_Pos)
 
#define APSR_Z_Pos   30U
 
#define APSR_Z_Msk   (1UL << APSR_Z_Pos)
 
#define APSR_C_Pos   29U
 
#define APSR_C_Msk   (1UL << APSR_C_Pos)
 
#define APSR_V_Pos   28U
 
#define APSR_V_Msk   (1UL << APSR_V_Pos)
 
#define IPSR_ISR_Pos   0U
 
#define IPSR_ISR_Msk   (0x1FFUL /*<< IPSR_ISR_Pos*/)
 
#define xPSR_N_Pos   31U
 
#define xPSR_N_Msk   (1UL << xPSR_N_Pos)
 
#define xPSR_Z_Pos   30U
 
#define xPSR_Z_Msk   (1UL << xPSR_Z_Pos)
 
#define xPSR_C_Pos   29U
 
#define xPSR_C_Msk   (1UL << xPSR_C_Pos)
 
#define xPSR_V_Pos   28U
 
#define xPSR_V_Msk   (1UL << xPSR_V_Pos)
 
#define xPSR_T_Pos   24U
 
#define xPSR_T_Msk   (1UL << xPSR_T_Pos)
 
#define xPSR_ISR_Pos   0U
 
#define xPSR_ISR_Msk   (0x1FFUL /*<< xPSR_ISR_Pos*/)
 
#define CONTROL_SPSEL_Pos   1U
 
#define CONTROL_SPSEL_Msk   (1UL << CONTROL_SPSEL_Pos)
 
#define APSR_N_Pos   31U
 
#define APSR_N_Msk   (1UL << APSR_N_Pos)
 
#define APSR_Z_Pos   30U
 
#define APSR_Z_Msk   (1UL << APSR_Z_Pos)
 
#define APSR_C_Pos   29U
 
#define APSR_C_Msk   (1UL << APSR_C_Pos)
 
#define APSR_V_Pos   28U
 
#define APSR_V_Msk   (1UL << APSR_V_Pos)
 
#define APSR_Q_Pos   27U
 
#define APSR_Q_Msk   (1UL << APSR_Q_Pos)
 
#define IPSR_ISR_Pos   0U
 
#define IPSR_ISR_Msk   (0x1FFUL /*<< IPSR_ISR_Pos*/)
 
#define xPSR_N_Pos   31U
 
#define xPSR_N_Msk   (1UL << xPSR_N_Pos)
 
#define xPSR_Z_Pos   30U
 
#define xPSR_Z_Msk   (1UL << xPSR_Z_Pos)
 
#define xPSR_C_Pos   29U
 
#define xPSR_C_Msk   (1UL << xPSR_C_Pos)
 
#define xPSR_V_Pos   28U
 
#define xPSR_V_Msk   (1UL << xPSR_V_Pos)
 
#define xPSR_Q_Pos   27U
 
#define xPSR_Q_Msk   (1UL << xPSR_Q_Pos)
 
#define xPSR_ICI_IT_2_Pos   25U
 
#define xPSR_ICI_IT_2_Msk   (3UL << xPSR_ICI_IT_2_Pos)
 
#define xPSR_T_Pos   24U
 
#define xPSR_T_Msk   (1UL << xPSR_T_Pos)
 
#define xPSR_ICI_IT_1_Pos   10U
 
#define xPSR_ICI_IT_1_Msk   (0x3FUL << xPSR_ICI_IT_1_Pos)
 
#define xPSR_ISR_Pos   0U
 
#define xPSR_ISR_Msk   (0x1FFUL /*<< xPSR_ISR_Pos*/)
 
#define CONTROL_SPSEL_Pos   1U
 
#define CONTROL_SPSEL_Msk   (1UL << CONTROL_SPSEL_Pos)
 
#define CONTROL_nPRIV_Pos   0U
 
#define CONTROL_nPRIV_Msk   (1UL /*<< CONTROL_nPRIV_Pos*/)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos
 
#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SysTick_CTRL_COUNTFLAG_Pos   16U
 
#define SysTick_CTRL_COUNTFLAG_Msk   (1UL << SysTick_CTRL_COUNTFLAG_Pos)
 
#define SysTick_CTRL_CLKSOURCE_Pos   2U
 
#define SysTick_CTRL_CLKSOURCE_Msk   (1UL << SysTick_CTRL_CLKSOURCE_Pos)
 
#define SysTick_CTRL_TICKINT_Pos   1U
 
#define SysTick_CTRL_TICKINT_Msk   (1UL << SysTick_CTRL_TICKINT_Pos)
 
#define SysTick_CTRL_ENABLE_Pos   0U
 
#define SysTick_CTRL_ENABLE_Msk   (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)
 
#define SysTick_LOAD_RELOAD_Pos   0U
 
#define SysTick_LOAD_RELOAD_Msk   (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)
 
#define SysTick_VAL_CURRENT_Pos   0U
 
#define SysTick_VAL_CURRENT_Msk   (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)
 
#define SysTick_CALIB_NOREF_Pos   31U
 
#define SysTick_CALIB_NOREF_Msk   (1UL << SysTick_CALIB_NOREF_Pos)
 
#define SysTick_CALIB_SKEW_Pos   30U
 
#define SysTick_CALIB_SKEW_Msk   (1UL << SysTick_CALIB_SKEW_Pos)
 
#define SysTick_CALIB_TENMS_Pos   0U
 
#define SysTick_CALIB_TENMS_Msk   (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)
 
#define DWT_CTRL_NUMCOMP_Pos   28U
 
#define DWT_CTRL_NUMCOMP_Msk   (0xFUL << DWT_CTRL_NUMCOMP_Pos)
 
#define DWT_CTRL_NOTRCPKT_Pos   27U
 
#define DWT_CTRL_NOTRCPKT_Msk   (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
 
#define DWT_CTRL_NOEXTTRIG_Pos   26U
 
#define DWT_CTRL_NOEXTTRIG_Msk   (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
 
#define DWT_CTRL_NOCYCCNT_Pos   25U
 
#define DWT_CTRL_NOCYCCNT_Msk   (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
 
#define DWT_CTRL_NOPRFCNT_Pos   24U
 
#define DWT_CTRL_NOPRFCNT_Msk   (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
 
#define DWT_FUNCTION_MATCHED_Pos   24U
 
#define DWT_FUNCTION_MATCHED_Msk   (0x1UL << DWT_FUNCTION_MATCHED_Pos)
 
#define DWT_FUNCTION_DATAVSIZE_Pos   10U
 
#define DWT_FUNCTION_DATAVSIZE_Msk   (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
 
#define TPI_SPPR_TXMODE_Pos   0U
 
#define TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
 
#define TPI_FFSR_FtNonStop_Pos   3U
 
#define TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)
 
#define TPI_FFSR_TCPresent_Pos   2U
 
#define TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)
 
#define TPI_FFSR_FtStopped_Pos   1U
 
#define TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)
 
#define TPI_FFSR_FlInProg_Pos   0U
 
#define TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
 
#define TPI_FFCR_TrigIn_Pos   8U
 
#define TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)
 
#define TPI_FFCR_EnFCont_Pos   1U
 
#define TPI_FFCR_EnFCont_Msk   (0x1UL << TPI_FFCR_EnFCont_Pos)
 
#define TPI_DEVID_NRZVALID_Pos   11U
 
#define TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)
 
#define TPI_DEVID_MANCVALID_Pos   10U
 
#define TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)
 
#define TPI_DEVID_PTINVALID_Pos   9U
 
#define TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)
 
#define TPI_DEVTYPE_SubType_Pos   4U
 
#define TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
 
#define TPI_DEVTYPE_MajorType_Pos   0U
 
#define TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)
 
#define MPU_TYPE_IREGION_Pos   16U
 
#define MPU_TYPE_IREGION_Msk   (0xFFUL << MPU_TYPE_IREGION_Pos)
 
#define MPU_TYPE_DREGION_Pos   8U
 
#define MPU_TYPE_DREGION_Msk   (0xFFUL << MPU_TYPE_DREGION_Pos)
 
#define MPU_TYPE_SEPARATE_Pos   0U
 
#define MPU_TYPE_SEPARATE_Msk   (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)
 
#define MPU_CTRL_PRIVDEFENA_Pos   2U
 
#define MPU_CTRL_PRIVDEFENA_Msk   (1UL << MPU_CTRL_PRIVDEFENA_Pos)
 
#define MPU_CTRL_HFNMIENA_Pos   1U
 
#define MPU_CTRL_HFNMIENA_Msk   (1UL << MPU_CTRL_HFNMIENA_Pos)
 
#define MPU_CTRL_ENABLE_Pos   0U
 
#define MPU_CTRL_ENABLE_Msk   (1UL /*<< MPU_CTRL_ENABLE_Pos*/)
 
#define MPU_RNR_REGION_Pos   0U
 
#define MPU_RNR_REGION_Msk   (0xFFUL /*<< MPU_RNR_REGION_Pos*/)
 
#define CoreDebug_DHCSR_DBGKEY_Pos   16U
 
#define CoreDebug_DHCSR_DBGKEY_Msk   (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
 
#define CoreDebug_DHCSR_S_RESET_ST_Pos   25U
 
#define CoreDebug_DHCSR_S_RESET_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
 
#define CoreDebug_DHCSR_S_RETIRE_ST_Pos   24U
 
#define CoreDebug_DHCSR_S_RETIRE_ST_Msk   (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
 
#define CoreDebug_DHCSR_S_LOCKUP_Pos   19U
 
#define CoreDebug_DHCSR_S_LOCKUP_Msk   (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
 
#define CoreDebug_DHCSR_S_SLEEP_Pos   18U
 
#define CoreDebug_DHCSR_S_SLEEP_Msk   (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
 
#define CoreDebug_DHCSR_S_HALT_Pos   17U
 
#define CoreDebug_DHCSR_S_HALT_Msk   (1UL << CoreDebug_DHCSR_S_HALT_Pos)
 
#define CoreDebug_DHCSR_S_REGRDY_Pos   16U
 
#define CoreDebug_DHCSR_S_REGRDY_Msk   (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
 
#define CoreDebug_DHCSR_C_MASKINTS_Pos   3U
 
#define CoreDebug_DHCSR_C_MASKINTS_Msk   (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
 
#define CoreDebug_DHCSR_C_STEP_Pos   2U
 
#define CoreDebug_DHCSR_C_STEP_Msk   (1UL << CoreDebug_DHCSR_C_STEP_Pos)
 
#define CoreDebug_DHCSR_C_HALT_Pos   1U
 
#define CoreDebug_DHCSR_C_HALT_Msk   (1UL << CoreDebug_DHCSR_C_HALT_Pos)
 
#define CoreDebug_DHCSR_C_DEBUGEN_Pos   0U
 
#define CoreDebug_DHCSR_C_DEBUGEN_Msk   (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)
 
#define CoreDebug_DCRSR_REGWnR_Pos   16U
 
#define CoreDebug_DCRSR_REGWnR_Msk   (1UL << CoreDebug_DCRSR_REGWnR_Pos)
 
#define CoreDebug_DCRSR_REGSEL_Pos   0U
 
#define CoreDebug_DCRSR_REGSEL_Msk   (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)
 
#define CoreDebug_DEMCR_VC_HARDERR_Pos   10U
 
#define CoreDebug_DEMCR_VC_HARDERR_Msk   (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
 
#define CoreDebug_DEMCR_VC_CORERESET_Pos   0U
 
#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)
 
#define _VAL2FLD(field, value)
 Mask and shift a bit field value for use in a register bit range.
 
#define _FLD2VAL(field, value)
 Mask and shift a register value to extract a bit filed value.
 
#define SCS_BASE   (0xE000E000UL)
 
#define DWT_BASE   (0xE0001000UL)
 
#define TPI_BASE   (0xE0040000UL)
 
#define CoreDebug_BASE   (0xE000EDF0UL)
 
#define SysTick_BASE   (SCS_BASE + 0x0010UL)
 
#define NVIC_BASE   (SCS_BASE + 0x0100UL)
 
#define SCB_BASE   (SCS_BASE + 0x0D00UL)
 
#define SCB   ((SCB_Type *) SCB_BASE )
 
#define SysTick   ((SysTick_Type *) SysTick_BASE )
 
#define NVIC   ((NVIC_Type *) NVIC_BASE )
 
#define DWT   ((DWT_Type *) DWT_BASE )
 
#define TPI   ((TPI_Type *) TPI_BASE )
 
#define CoreDebug   ((CoreDebug_Type *) CoreDebug_BASE )
 
#define MPU_BASE   (SCS_BASE + 0x0D90UL)
 
#define MPU   ((MPU_Type *) MPU_BASE )
 
#define NVIC_SetPriorityGrouping   __NVIC_SetPriorityGrouping
 
#define NVIC_GetPriorityGrouping   __NVIC_GetPriorityGrouping
 
#define NVIC_EnableIRQ   __NVIC_EnableIRQ
 
#define NVIC_GetEnableIRQ   __NVIC_GetEnableIRQ
 
#define NVIC_DisableIRQ   __NVIC_DisableIRQ
 
#define NVIC_GetPendingIRQ   __NVIC_GetPendingIRQ
 
#define NVIC_SetPendingIRQ   __NVIC_SetPendingIRQ
 
#define NVIC_ClearPendingIRQ   __NVIC_ClearPendingIRQ
 
#define NVIC_GetActive   __NVIC_GetActive
 
#define NVIC_SetPriority   __NVIC_SetPriority
 
#define NVIC_GetPriority   __NVIC_GetPriority
 
#define NVIC_SystemReset   __NVIC_SystemReset
 
#define NVIC_SetVector   __NVIC_SetVector
 
#define NVIC_GetVector   __NVIC_GetVector
 
#define NVIC_USER_IRQ_OFFSET   16
 
#define NVIC_STIR_INTID_Pos   0U
 
#define NVIC_STIR_INTID_Msk   (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos
 
#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCnSCB_ICTR_INTLINESNUM_Pos   0U
 
#define SCnSCB_ICTR_INTLINESNUM_Msk   (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)
 
#define SysTick_CTRL_COUNTFLAG_Pos   16U
 
#define SysTick_CTRL_COUNTFLAG_Msk   (1UL << SysTick_CTRL_COUNTFLAG_Pos)
 
#define SysTick_CTRL_CLKSOURCE_Pos   2U
 
#define SysTick_CTRL_CLKSOURCE_Msk   (1UL << SysTick_CTRL_CLKSOURCE_Pos)
 
#define SysTick_CTRL_TICKINT_Pos   1U
 
#define SysTick_CTRL_TICKINT_Msk   (1UL << SysTick_CTRL_TICKINT_Pos)
 
#define SysTick_CTRL_ENABLE_Pos   0U
 
#define SysTick_CTRL_ENABLE_Msk   (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)
 
#define SysTick_LOAD_RELOAD_Pos   0U
 
#define SysTick_LOAD_RELOAD_Msk   (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)
 
#define SysTick_VAL_CURRENT_Pos   0U
 
#define SysTick_VAL_CURRENT_Msk   (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)
 
#define SysTick_CALIB_NOREF_Pos   31U
 
#define SysTick_CALIB_NOREF_Msk   (1UL << SysTick_CALIB_NOREF_Pos)
 
#define SysTick_CALIB_SKEW_Pos   30U
 
#define SysTick_CALIB_SKEW_Msk   (1UL << SysTick_CALIB_SKEW_Pos)
 
#define SysTick_CALIB_TENMS_Pos   0U
 
#define SysTick_CALIB_TENMS_Msk   (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)
 
#define ITM_TPR_PRIVMASK_Pos   0U
 
#define ITM_TPR_PRIVMASK_Msk   (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
 
#define ITM_TCR_BUSY_Pos   23U
 
#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)
 
#define ITM_TCR_GTSFREQ_Pos   10U
 
#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)
 
#define ITM_TCR_SWOENA_Pos   4U
 
#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)
 
#define ITM_TCR_DWTENA_Pos   3U
 
#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)
 
#define ITM_TCR_SYNCENA_Pos   2U
 
#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)
 
#define ITM_TCR_TSENA_Pos   1U
 
#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)
 
#define ITM_TCR_ITMENA_Pos   0U
 
#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)
 
#define ITM_IWR_ATVALIDM_Pos   0U
 
#define ITM_IWR_ATVALIDM_Msk   (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)
 
#define ITM_IRR_ATREADYM_Pos   0U
 
#define ITM_IRR_ATREADYM_Msk   (1UL /*<< ITM_IRR_ATREADYM_Pos*/)
 
#define ITM_IMCR_INTEGRATION_Pos   0U
 
#define ITM_IMCR_INTEGRATION_Msk   (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)
 
#define ITM_LSR_ByteAcc_Pos   2U
 
#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)
 
#define ITM_LSR_Access_Pos   1U
 
#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)
 
#define ITM_LSR_Present_Pos   0U
 
#define ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)
 
#define DWT_CTRL_NUMCOMP_Pos   28U
 
#define DWT_CTRL_NUMCOMP_Msk   (0xFUL << DWT_CTRL_NUMCOMP_Pos)
 
#define DWT_CTRL_NOTRCPKT_Pos   27U
 
#define DWT_CTRL_NOTRCPKT_Msk   (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
 
#define DWT_CTRL_NOEXTTRIG_Pos   26U
 
#define DWT_CTRL_NOEXTTRIG_Msk   (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
 
#define DWT_CTRL_NOCYCCNT_Pos   25U
 
#define DWT_CTRL_NOCYCCNT_Msk   (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
 
#define DWT_CTRL_NOPRFCNT_Pos   24U
 
#define DWT_CTRL_NOPRFCNT_Msk   (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
 
#define DWT_CTRL_CYCEVTENA_Pos   22U
 
#define DWT_CTRL_CYCEVTENA_Msk   (0x1UL << DWT_CTRL_CYCEVTENA_Pos)
 
#define DWT_CTRL_FOLDEVTENA_Pos   21U
 
#define DWT_CTRL_FOLDEVTENA_Msk   (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)
 
#define DWT_CTRL_LSUEVTENA_Pos   20U
 
#define DWT_CTRL_LSUEVTENA_Msk   (0x1UL << DWT_CTRL_LSUEVTENA_Pos)
 
#define DWT_CTRL_SLEEPEVTENA_Pos   19U
 
#define DWT_CTRL_SLEEPEVTENA_Msk   (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)
 
#define DWT_CTRL_EXCEVTENA_Pos   18U
 
#define DWT_CTRL_EXCEVTENA_Msk   (0x1UL << DWT_CTRL_EXCEVTENA_Pos)
 
#define DWT_CTRL_CPIEVTENA_Pos   17U
 
#define DWT_CTRL_CPIEVTENA_Msk   (0x1UL << DWT_CTRL_CPIEVTENA_Pos)
 
#define DWT_CTRL_EXCTRCENA_Pos   16U
 
#define DWT_CTRL_EXCTRCENA_Msk   (0x1UL << DWT_CTRL_EXCTRCENA_Pos)
 
#define DWT_CTRL_PCSAMPLENA_Pos   12U
 
#define DWT_CTRL_PCSAMPLENA_Msk   (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)
 
#define DWT_CTRL_SYNCTAP_Pos   10U
 
#define DWT_CTRL_SYNCTAP_Msk   (0x3UL << DWT_CTRL_SYNCTAP_Pos)
 
#define DWT_CTRL_CYCTAP_Pos   9U
 
#define DWT_CTRL_CYCTAP_Msk   (0x1UL << DWT_CTRL_CYCTAP_Pos)
 
#define DWT_CTRL_POSTINIT_Pos   5U
 
#define DWT_CTRL_POSTINIT_Msk   (0xFUL << DWT_CTRL_POSTINIT_Pos)
 
#define DWT_CTRL_POSTPRESET_Pos   1U
 
#define DWT_CTRL_POSTPRESET_Msk   (0xFUL << DWT_CTRL_POSTPRESET_Pos)
 
#define DWT_CTRL_CYCCNTENA_Pos   0U
 
#define DWT_CTRL_CYCCNTENA_Msk   (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)
 
#define DWT_CPICNT_CPICNT_Pos   0U
 
#define DWT_CPICNT_CPICNT_Msk   (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)
 
#define DWT_EXCCNT_EXCCNT_Pos   0U
 
#define DWT_EXCCNT_EXCCNT_Msk   (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)
 
#define DWT_SLEEPCNT_SLEEPCNT_Pos   0U
 
#define DWT_SLEEPCNT_SLEEPCNT_Msk   (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)
 
#define DWT_LSUCNT_LSUCNT_Pos   0U
 
#define DWT_LSUCNT_LSUCNT_Msk   (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)
 
#define DWT_FOLDCNT_FOLDCNT_Pos   0U
 
#define DWT_FOLDCNT_FOLDCNT_Msk   (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)
 
#define DWT_FUNCTION_MATCHED_Pos   24U
 
#define DWT_FUNCTION_MATCHED_Msk   (0x1UL << DWT_FUNCTION_MATCHED_Pos)
 
#define DWT_FUNCTION_DATAVSIZE_Pos   10U
 
#define DWT_FUNCTION_DATAVSIZE_Msk   (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
 
#define TPI_SPPR_TXMODE_Pos   0U
 
#define TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
 
#define TPI_FFSR_FtNonStop_Pos   3U
 
#define TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)
 
#define TPI_FFSR_TCPresent_Pos   2U
 
#define TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)
 
#define TPI_FFSR_FtStopped_Pos   1U
 
#define TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)
 
#define TPI_FFSR_FlInProg_Pos   0U
 
#define TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
 
#define TPI_FFCR_TrigIn_Pos   8U
 
#define TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)
 
#define TPI_FFCR_EnFCont_Pos   1U
 
#define TPI_FFCR_EnFCont_Msk   (0x1UL << TPI_FFCR_EnFCont_Pos)
 
#define TPI_DEVID_NRZVALID_Pos   11U
 
#define TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)
 
#define TPI_DEVID_MANCVALID_Pos   10U
 
#define TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)
 
#define TPI_DEVID_PTINVALID_Pos   9U
 
#define TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)
 
#define TPI_DEVTYPE_SubType_Pos   4U
 
#define TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
 
#define TPI_DEVTYPE_MajorType_Pos   0U
 
#define TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)
 
#define MPU_TYPE_IREGION_Pos   16U
 
#define MPU_TYPE_IREGION_Msk   (0xFFUL << MPU_TYPE_IREGION_Pos)
 
#define MPU_TYPE_DREGION_Pos   8U
 
#define MPU_TYPE_DREGION_Msk   (0xFFUL << MPU_TYPE_DREGION_Pos)
 
#define MPU_TYPE_SEPARATE_Pos   0U
 
#define MPU_TYPE_SEPARATE_Msk   (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)
 
#define MPU_CTRL_PRIVDEFENA_Pos   2U
 
#define MPU_CTRL_PRIVDEFENA_Msk   (1UL << MPU_CTRL_PRIVDEFENA_Pos)
 
#define MPU_CTRL_HFNMIENA_Pos   1U
 
#define MPU_CTRL_HFNMIENA_Msk   (1UL << MPU_CTRL_HFNMIENA_Pos)
 
#define MPU_CTRL_ENABLE_Pos   0U
 
#define MPU_CTRL_ENABLE_Msk   (1UL /*<< MPU_CTRL_ENABLE_Pos*/)
 
#define MPU_RNR_REGION_Pos   0U
 
#define MPU_RNR_REGION_Msk   (0xFFUL /*<< MPU_RNR_REGION_Pos*/)
 
#define CoreDebug_DHCSR_DBGKEY_Pos   16U
 
#define CoreDebug_DHCSR_DBGKEY_Msk   (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
 
#define CoreDebug_DHCSR_S_RESET_ST_Pos   25U
 
#define CoreDebug_DHCSR_S_RESET_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
 
#define CoreDebug_DHCSR_S_RETIRE_ST_Pos   24U
 
#define CoreDebug_DHCSR_S_RETIRE_ST_Msk   (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
 
#define CoreDebug_DHCSR_S_LOCKUP_Pos   19U
 
#define CoreDebug_DHCSR_S_LOCKUP_Msk   (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
 
#define CoreDebug_DHCSR_S_SLEEP_Pos   18U
 
#define CoreDebug_DHCSR_S_SLEEP_Msk   (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
 
#define CoreDebug_DHCSR_S_HALT_Pos   17U
 
#define CoreDebug_DHCSR_S_HALT_Msk   (1UL << CoreDebug_DHCSR_S_HALT_Pos)
 
#define CoreDebug_DHCSR_S_REGRDY_Pos   16U
 
#define CoreDebug_DHCSR_S_REGRDY_Msk   (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
 
#define CoreDebug_DHCSR_C_SNAPSTALL_Pos   5U
 
#define CoreDebug_DHCSR_C_SNAPSTALL_Msk   (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)
 
#define CoreDebug_DHCSR_C_MASKINTS_Pos   3U
 
#define CoreDebug_DHCSR_C_MASKINTS_Msk   (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
 
#define CoreDebug_DHCSR_C_STEP_Pos   2U
 
#define CoreDebug_DHCSR_C_STEP_Msk   (1UL << CoreDebug_DHCSR_C_STEP_Pos)
 
#define CoreDebug_DHCSR_C_HALT_Pos   1U
 
#define CoreDebug_DHCSR_C_HALT_Msk   (1UL << CoreDebug_DHCSR_C_HALT_Pos)
 
#define CoreDebug_DHCSR_C_DEBUGEN_Pos   0U
 
#define CoreDebug_DHCSR_C_DEBUGEN_Msk   (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)
 
#define CoreDebug_DCRSR_REGWnR_Pos   16U
 
#define CoreDebug_DCRSR_REGWnR_Msk   (1UL << CoreDebug_DCRSR_REGWnR_Pos)
 
#define CoreDebug_DCRSR_REGSEL_Pos   0U
 
#define CoreDebug_DCRSR_REGSEL_Msk   (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)
 
#define CoreDebug_DEMCR_TRCENA_Pos   24U
 
#define CoreDebug_DEMCR_TRCENA_Msk   (1UL << CoreDebug_DEMCR_TRCENA_Pos)
 
#define CoreDebug_DEMCR_MON_REQ_Pos   19U
 
#define CoreDebug_DEMCR_MON_REQ_Msk   (1UL << CoreDebug_DEMCR_MON_REQ_Pos)
 
#define CoreDebug_DEMCR_MON_STEP_Pos   18U
 
#define CoreDebug_DEMCR_MON_STEP_Msk   (1UL << CoreDebug_DEMCR_MON_STEP_Pos)
 
#define CoreDebug_DEMCR_MON_PEND_Pos   17U
 
#define CoreDebug_DEMCR_MON_PEND_Msk   (1UL << CoreDebug_DEMCR_MON_PEND_Pos)
 
#define CoreDebug_DEMCR_MON_EN_Pos   16U
 
#define CoreDebug_DEMCR_MON_EN_Msk   (1UL << CoreDebug_DEMCR_MON_EN_Pos)
 
#define CoreDebug_DEMCR_VC_HARDERR_Pos   10U
 
#define CoreDebug_DEMCR_VC_HARDERR_Msk   (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
 
#define CoreDebug_DEMCR_VC_INTERR_Pos   9U
 
#define CoreDebug_DEMCR_VC_INTERR_Msk   (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)
 
#define CoreDebug_DEMCR_VC_BUSERR_Pos   8U
 
#define CoreDebug_DEMCR_VC_BUSERR_Msk   (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)
 
#define CoreDebug_DEMCR_VC_STATERR_Pos   7U
 
#define CoreDebug_DEMCR_VC_STATERR_Msk   (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)
 
#define CoreDebug_DEMCR_VC_CHKERR_Pos   6U
 
#define CoreDebug_DEMCR_VC_CHKERR_Msk   (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)
 
#define CoreDebug_DEMCR_VC_NOCPERR_Pos   5U
 
#define CoreDebug_DEMCR_VC_NOCPERR_Msk   (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)
 
#define CoreDebug_DEMCR_VC_MMERR_Pos   4U
 
#define CoreDebug_DEMCR_VC_MMERR_Msk   (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)
 
#define CoreDebug_DEMCR_VC_CORERESET_Pos   0U
 
#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)
 
#define _VAL2FLD(field, value)
 Mask and shift a bit field value for use in a register bit range.
 
#define _FLD2VAL(field, value)
 Mask and shift a register value to extract a bit filed value.
 
#define SCS_BASE   (0xE000E000UL)
 
#define ITM_BASE   (0xE0000000UL)
 
#define DWT_BASE   (0xE0001000UL)
 
#define TPI_BASE   (0xE0040000UL)
 
#define CoreDebug_BASE   (0xE000EDF0UL)
 
#define SysTick_BASE   (SCS_BASE + 0x0010UL)
 
#define NVIC_BASE   (SCS_BASE + 0x0100UL)
 
#define SCB_BASE   (SCS_BASE + 0x0D00UL)
 
#define SCnSCB   ((SCnSCB_Type *) SCS_BASE )
 
#define SCB   ((SCB_Type *) SCB_BASE )
 
#define SysTick   ((SysTick_Type *) SysTick_BASE )
 
#define NVIC   ((NVIC_Type *) NVIC_BASE )
 
#define ITM   ((ITM_Type *) ITM_BASE )
 
#define DWT   ((DWT_Type *) DWT_BASE )
 
#define TPI   ((TPI_Type *) TPI_BASE )
 
#define CoreDebug   ((CoreDebug_Type *) CoreDebug_BASE )
 
#define MPU_BASE   (SCS_BASE + 0x0D90UL)
 
#define MPU   ((MPU_Type *) MPU_BASE )
 
#define NVIC_SetPriorityGrouping   __NVIC_SetPriorityGrouping
 
#define NVIC_GetPriorityGrouping   __NVIC_GetPriorityGrouping
 
#define NVIC_EnableIRQ   __NVIC_EnableIRQ
 
#define NVIC_GetEnableIRQ   __NVIC_GetEnableIRQ
 
#define NVIC_DisableIRQ   __NVIC_DisableIRQ
 
#define NVIC_GetPendingIRQ   __NVIC_GetPendingIRQ
 
#define NVIC_SetPendingIRQ   __NVIC_SetPendingIRQ
 
#define NVIC_ClearPendingIRQ   __NVIC_ClearPendingIRQ
 
#define NVIC_GetActive   __NVIC_GetActive
 
#define NVIC_SetPriority   __NVIC_SetPriority
 
#define NVIC_GetPriority   __NVIC_GetPriority
 
#define NVIC_SystemReset   __NVIC_SystemReset
 
#define NVIC_SetVector   __NVIC_SetVector
 
#define NVIC_GetVector   __NVIC_GetVector
 
#define NVIC_USER_IRQ_OFFSET   16
 
#define ITM_RXBUFFER_EMPTY   ((int32_t)0x5AA55AA5U)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SysTick_CTRL_COUNTFLAG_Pos   16U
 
#define SysTick_CTRL_COUNTFLAG_Msk   (1UL << SysTick_CTRL_COUNTFLAG_Pos)
 
#define SysTick_CTRL_CLKSOURCE_Pos   2U
 
#define SysTick_CTRL_CLKSOURCE_Msk   (1UL << SysTick_CTRL_CLKSOURCE_Pos)
 
#define SysTick_CTRL_TICKINT_Pos   1U
 
#define SysTick_CTRL_TICKINT_Msk   (1UL << SysTick_CTRL_TICKINT_Pos)
 
#define SysTick_CTRL_ENABLE_Pos   0U
 
#define SysTick_CTRL_ENABLE_Msk   (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)
 
#define SysTick_LOAD_RELOAD_Pos   0U
 
#define SysTick_LOAD_RELOAD_Msk   (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)
 
#define SysTick_VAL_CURRENT_Pos   0U
 
#define SysTick_VAL_CURRENT_Msk   (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)
 
#define SysTick_CALIB_NOREF_Pos   31U
 
#define SysTick_CALIB_NOREF_Msk   (1UL << SysTick_CALIB_NOREF_Pos)
 
#define SysTick_CALIB_SKEW_Pos   30U
 
#define SysTick_CALIB_SKEW_Msk   (1UL << SysTick_CALIB_SKEW_Pos)
 
#define SysTick_CALIB_TENMS_Pos   0U
 
#define SysTick_CALIB_TENMS_Msk   (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)
 
#define _VAL2FLD(field, value)
 Mask and shift a bit field value for use in a register bit range.
 
#define _FLD2VAL(field, value)
 Mask and shift a register value to extract a bit filed value.
 
#define SCS_BASE   (0xE000E000UL)
 
#define SysTick_BASE   (SCS_BASE + 0x0010UL)
 
#define NVIC_BASE   (SCS_BASE + 0x0100UL)
 
#define SCB_BASE   (SCS_BASE + 0x0D00UL)
 
#define SCB   ((SCB_Type *) SCB_BASE )
 
#define SysTick   ((SysTick_Type *) SysTick_BASE )
 
#define NVIC   ((NVIC_Type *) NVIC_BASE )
 
#define NVIC_SetPriorityGrouping   __NVIC_SetPriorityGrouping
 
#define NVIC_GetPriorityGrouping   __NVIC_GetPriorityGrouping
 
#define NVIC_EnableIRQ   __NVIC_EnableIRQ
 
#define NVIC_GetEnableIRQ   __NVIC_GetEnableIRQ
 
#define NVIC_DisableIRQ   __NVIC_DisableIRQ
 
#define NVIC_GetPendingIRQ   __NVIC_GetPendingIRQ
 
#define NVIC_SetPendingIRQ   __NVIC_SetPendingIRQ
 
#define NVIC_ClearPendingIRQ   __NVIC_ClearPendingIRQ
 
#define NVIC_SetPriority   __NVIC_SetPriority
 
#define NVIC_GetPriority   __NVIC_GetPriority
 
#define NVIC_SystemReset   __NVIC_SystemReset
 
#define NVIC_SetVector   __NVIC_SetVector
 
#define NVIC_GetVector   __NVIC_GetVector
 
#define NVIC_USER_IRQ_OFFSET   16
 
#define EXC_RETURN_HANDLER   (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
 
#define EXC_RETURN_THREAD_MSP   (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
 
#define EXC_RETURN_THREAD_PSP   (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SysTick_CTRL_COUNTFLAG_Pos   16U
 
#define SysTick_CTRL_COUNTFLAG_Msk   (1UL << SysTick_CTRL_COUNTFLAG_Pos)
 
#define SysTick_CTRL_CLKSOURCE_Pos   2U
 
#define SysTick_CTRL_CLKSOURCE_Msk   (1UL << SysTick_CTRL_CLKSOURCE_Pos)
 
#define SysTick_CTRL_TICKINT_Pos   1U
 
#define SysTick_CTRL_TICKINT_Msk   (1UL << SysTick_CTRL_TICKINT_Pos)
 
#define SysTick_CTRL_ENABLE_Pos   0U
 
#define SysTick_CTRL_ENABLE_Msk   (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)
 
#define SysTick_LOAD_RELOAD_Pos   0U
 
#define SysTick_LOAD_RELOAD_Msk   (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)
 
#define SysTick_VAL_CURRENT_Pos   0U
 
#define SysTick_VAL_CURRENT_Msk   (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)
 
#define SysTick_CALIB_NOREF_Pos   31U
 
#define SysTick_CALIB_NOREF_Msk   (1UL << SysTick_CALIB_NOREF_Pos)
 
#define SysTick_CALIB_SKEW_Pos   30U
 
#define SysTick_CALIB_SKEW_Msk   (1UL << SysTick_CALIB_SKEW_Pos)
 
#define SysTick_CALIB_TENMS_Pos   0U
 
#define SysTick_CALIB_TENMS_Msk   (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)
 
#define MPU_TYPE_IREGION_Pos   16U
 
#define MPU_TYPE_IREGION_Msk   (0xFFUL << MPU_TYPE_IREGION_Pos)
 
#define MPU_TYPE_DREGION_Pos   8U
 
#define MPU_TYPE_DREGION_Msk   (0xFFUL << MPU_TYPE_DREGION_Pos)
 
#define MPU_TYPE_SEPARATE_Pos   0U
 
#define MPU_TYPE_SEPARATE_Msk   (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)
 
#define MPU_CTRL_PRIVDEFENA_Pos   2U
 
#define MPU_CTRL_PRIVDEFENA_Msk   (1UL << MPU_CTRL_PRIVDEFENA_Pos)
 
#define MPU_CTRL_HFNMIENA_Pos   1U
 
#define MPU_CTRL_HFNMIENA_Msk   (1UL << MPU_CTRL_HFNMIENA_Pos)
 
#define MPU_CTRL_ENABLE_Pos   0U
 
#define MPU_CTRL_ENABLE_Msk   (1UL /*<< MPU_CTRL_ENABLE_Pos*/)
 
#define MPU_RNR_REGION_Pos   0U
 
#define MPU_RNR_REGION_Msk   (0xFFUL /*<< MPU_RNR_REGION_Pos*/)
 
#define MPU_RBAR_ADDR_Pos   8U
 
#define MPU_RBAR_ADDR_Msk   (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)
 
#define MPU_RBAR_VALID_Pos   4U
 
#define MPU_RBAR_VALID_Msk   (1UL << MPU_RBAR_VALID_Pos)
 
#define MPU_RBAR_REGION_Pos   0U
 
#define MPU_RBAR_REGION_Msk   (0xFUL /*<< MPU_RBAR_REGION_Pos*/)
 
#define MPU_RASR_ATTRS_Pos   16U
 
#define MPU_RASR_ATTRS_Msk   (0xFFFFUL << MPU_RASR_ATTRS_Pos)
 
#define MPU_RASR_XN_Pos   28U
 
#define MPU_RASR_XN_Msk   (1UL << MPU_RASR_XN_Pos)
 
#define MPU_RASR_AP_Pos   24U
 
#define MPU_RASR_AP_Msk   (0x7UL << MPU_RASR_AP_Pos)
 
#define MPU_RASR_TEX_Pos   19U
 
#define MPU_RASR_TEX_Msk   (0x7UL << MPU_RASR_TEX_Pos)
 
#define MPU_RASR_S_Pos   18U
 
#define MPU_RASR_S_Msk   (1UL << MPU_RASR_S_Pos)
 
#define MPU_RASR_C_Pos   17U
 
#define MPU_RASR_C_Msk   (1UL << MPU_RASR_C_Pos)
 
#define MPU_RASR_B_Pos   16U
 
#define MPU_RASR_B_Msk   (1UL << MPU_RASR_B_Pos)
 
#define MPU_RASR_SRD_Pos   8U
 
#define MPU_RASR_SRD_Msk   (0xFFUL << MPU_RASR_SRD_Pos)
 
#define MPU_RASR_SIZE_Pos   1U
 
#define MPU_RASR_SIZE_Msk   (0x1FUL << MPU_RASR_SIZE_Pos)
 
#define MPU_RASR_ENABLE_Pos   0U
 
#define MPU_RASR_ENABLE_Msk   (1UL /*<< MPU_RASR_ENABLE_Pos*/)
 
#define _VAL2FLD(field, value)
 Mask and shift a bit field value for use in a register bit range.
 
#define _FLD2VAL(field, value)
 Mask and shift a register value to extract a bit filed value.
 
#define SCS_BASE   (0xE000E000UL)
 
#define SysTick_BASE   (SCS_BASE + 0x0010UL)
 
#define NVIC_BASE   (SCS_BASE + 0x0100UL)
 
#define SCB_BASE   (SCS_BASE + 0x0D00UL)
 
#define SCB   ((SCB_Type *) SCB_BASE )
 
#define SysTick   ((SysTick_Type *) SysTick_BASE )
 
#define NVIC   ((NVIC_Type *) NVIC_BASE )
 
#define MPU_BASE   (SCS_BASE + 0x0D90UL)
 
#define MPU   ((MPU_Type *) MPU_BASE )
 
#define NVIC_SetPriorityGrouping   __NVIC_SetPriorityGrouping
 
#define NVIC_GetPriorityGrouping   __NVIC_GetPriorityGrouping
 
#define NVIC_EnableIRQ   __NVIC_EnableIRQ
 
#define NVIC_GetEnableIRQ   __NVIC_GetEnableIRQ
 
#define NVIC_DisableIRQ   __NVIC_DisableIRQ
 
#define NVIC_GetPendingIRQ   __NVIC_GetPendingIRQ
 
#define NVIC_SetPendingIRQ   __NVIC_SetPendingIRQ
 
#define NVIC_ClearPendingIRQ   __NVIC_ClearPendingIRQ
 
#define NVIC_SetPriority   __NVIC_SetPriority
 
#define NVIC_GetPriority   __NVIC_GetPriority
 
#define NVIC_SystemReset   __NVIC_SystemReset
 
#define NVIC_SetVector   __NVIC_SetVector
 
#define NVIC_GetVector   __NVIC_GetVector
 
#define NVIC_USER_IRQ_OFFSET   16
 
#define EXC_RETURN_HANDLER   (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
 
#define EXC_RETURN_THREAD_MSP   (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
 
#define EXC_RETURN_THREAD_PSP   (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SysTick_CTRL_COUNTFLAG_Pos   16U
 
#define SysTick_CTRL_COUNTFLAG_Msk   (1UL << SysTick_CTRL_COUNTFLAG_Pos)
 
#define SysTick_CTRL_CLKSOURCE_Pos   2U
 
#define SysTick_CTRL_CLKSOURCE_Msk   (1UL << SysTick_CTRL_CLKSOURCE_Pos)
 
#define SysTick_CTRL_TICKINT_Pos   1U
 
#define SysTick_CTRL_TICKINT_Msk   (1UL << SysTick_CTRL_TICKINT_Pos)
 
#define SysTick_CTRL_ENABLE_Pos   0U
 
#define SysTick_CTRL_ENABLE_Msk   (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)
 
#define SysTick_LOAD_RELOAD_Pos   0U
 
#define SysTick_LOAD_RELOAD_Msk   (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)
 
#define SysTick_VAL_CURRENT_Pos   0U
 
#define SysTick_VAL_CURRENT_Msk   (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)
 
#define SysTick_CALIB_NOREF_Pos   31U
 
#define SysTick_CALIB_NOREF_Msk   (1UL << SysTick_CALIB_NOREF_Pos)
 
#define SysTick_CALIB_SKEW_Pos   30U
 
#define SysTick_CALIB_SKEW_Msk   (1UL << SysTick_CALIB_SKEW_Pos)
 
#define SysTick_CALIB_TENMS_Pos   0U
 
#define SysTick_CALIB_TENMS_Msk   (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)
 
#define _VAL2FLD(field, value)
 Mask and shift a bit field value for use in a register bit range.
 
#define _FLD2VAL(field, value)
 Mask and shift a register value to extract a bit filed value.
 
#define SCS_BASE   (0xE000E000UL)
 
#define SysTick_BASE   (SCS_BASE + 0x0010UL)
 
#define NVIC_BASE   (SCS_BASE + 0x0100UL)
 
#define SCB_BASE   (SCS_BASE + 0x0D00UL)
 
#define SCnSCB   ((SCnSCB_Type *) SCS_BASE )
 
#define SCB   ((SCB_Type *) SCB_BASE )
 
#define SysTick   ((SysTick_Type *) SysTick_BASE )
 
#define NVIC   ((NVIC_Type *) NVIC_BASE )
 
#define NVIC_SetPriorityGrouping   __NVIC_SetPriorityGrouping
 
#define NVIC_GetPriorityGrouping   __NVIC_GetPriorityGrouping
 
#define NVIC_EnableIRQ   __NVIC_EnableIRQ
 
#define NVIC_GetEnableIRQ   __NVIC_GetEnableIRQ
 
#define NVIC_DisableIRQ   __NVIC_DisableIRQ
 
#define NVIC_GetPendingIRQ   __NVIC_GetPendingIRQ
 
#define NVIC_SetPendingIRQ   __NVIC_SetPendingIRQ
 
#define NVIC_ClearPendingIRQ   __NVIC_ClearPendingIRQ
 
#define NVIC_SetPriority   __NVIC_SetPriority
 
#define NVIC_GetPriority   __NVIC_GetPriority
 
#define NVIC_SystemReset   __NVIC_SystemReset
 
#define NVIC_SetVector   __NVIC_SetVector
 
#define NVIC_GetVector   __NVIC_GetVector
 
#define NVIC_USER_IRQ_OFFSET   16
 
#define EXC_RETURN_HANDLER   (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
 
#define EXC_RETURN_THREAD_MSP   (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
 
#define EXC_RETURN_THREAD_PSP   (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos
 
#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SysTick_CTRL_COUNTFLAG_Pos   16U
 
#define SysTick_CTRL_COUNTFLAG_Msk   (1UL << SysTick_CTRL_COUNTFLAG_Pos)
 
#define SysTick_CTRL_CLKSOURCE_Pos   2U
 
#define SysTick_CTRL_CLKSOURCE_Msk   (1UL << SysTick_CTRL_CLKSOURCE_Pos)
 
#define SysTick_CTRL_TICKINT_Pos   1U
 
#define SysTick_CTRL_TICKINT_Msk   (1UL << SysTick_CTRL_TICKINT_Pos)
 
#define SysTick_CTRL_ENABLE_Pos   0U
 
#define SysTick_CTRL_ENABLE_Msk   (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)
 
#define SysTick_LOAD_RELOAD_Pos   0U
 
#define SysTick_LOAD_RELOAD_Msk   (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)
 
#define SysTick_VAL_CURRENT_Pos   0U
 
#define SysTick_VAL_CURRENT_Msk   (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)
 
#define SysTick_CALIB_NOREF_Pos   31U
 
#define SysTick_CALIB_NOREF_Msk   (1UL << SysTick_CALIB_NOREF_Pos)
 
#define SysTick_CALIB_SKEW_Pos   30U
 
#define SysTick_CALIB_SKEW_Msk   (1UL << SysTick_CALIB_SKEW_Pos)
 
#define SysTick_CALIB_TENMS_Pos   0U
 
#define SysTick_CALIB_TENMS_Msk   (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)
 
#define DWT_CTRL_NUMCOMP_Pos   28U
 
#define DWT_CTRL_NUMCOMP_Msk   (0xFUL << DWT_CTRL_NUMCOMP_Pos)
 
#define DWT_CTRL_NOTRCPKT_Pos   27U
 
#define DWT_CTRL_NOTRCPKT_Msk   (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
 
#define DWT_CTRL_NOEXTTRIG_Pos   26U
 
#define DWT_CTRL_NOEXTTRIG_Msk   (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
 
#define DWT_CTRL_NOCYCCNT_Pos   25U
 
#define DWT_CTRL_NOCYCCNT_Msk   (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
 
#define DWT_CTRL_NOPRFCNT_Pos   24U
 
#define DWT_CTRL_NOPRFCNT_Msk   (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
 
#define DWT_FUNCTION_MATCHED_Pos   24U
 
#define DWT_FUNCTION_MATCHED_Msk   (0x1UL << DWT_FUNCTION_MATCHED_Pos)
 
#define DWT_FUNCTION_DATAVSIZE_Pos   10U
 
#define DWT_FUNCTION_DATAVSIZE_Msk   (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
 
#define TPI_ACPR_PRESCALER_Pos   0U
 
#define TPI_ACPR_PRESCALER_Msk   (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)
 
#define TPI_SPPR_TXMODE_Pos   0U
 
#define TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
 
#define TPI_FFSR_FtNonStop_Pos   3U
 
#define TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)
 
#define TPI_FFSR_TCPresent_Pos   2U
 
#define TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)
 
#define TPI_FFSR_FtStopped_Pos   1U
 
#define TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)
 
#define TPI_FFSR_FlInProg_Pos   0U
 
#define TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
 
#define TPI_FFCR_TrigIn_Pos   8U
 
#define TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)
 
#define TPI_FFCR_EnFCont_Pos   1U
 
#define TPI_FFCR_EnFCont_Msk   (0x1UL << TPI_FFCR_EnFCont_Pos)
 
#define TPI_TRIGGER_TRIGGER_Pos   0U
 
#define TPI_TRIGGER_TRIGGER_Msk   (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)
 
#define TPI_ITCTRL_Mode_Pos   0U
 
#define TPI_ITCTRL_Mode_Msk   (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)
 
#define TPI_DEVID_NRZVALID_Pos   11U
 
#define TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)
 
#define TPI_DEVID_MANCVALID_Pos   10U
 
#define TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)
 
#define TPI_DEVID_PTINVALID_Pos   9U
 
#define TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)
 
#define TPI_DEVID_NrTraceInput_Pos   0U
 
#define TPI_DEVID_NrTraceInput_Msk   (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)
 
#define TPI_DEVTYPE_SubType_Pos   4U
 
#define TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
 
#define TPI_DEVTYPE_MajorType_Pos   0U
 
#define TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)
 
#define MPU_TYPE_IREGION_Pos   16U
 
#define MPU_TYPE_IREGION_Msk   (0xFFUL << MPU_TYPE_IREGION_Pos)
 
#define MPU_TYPE_DREGION_Pos   8U
 
#define MPU_TYPE_DREGION_Msk   (0xFFUL << MPU_TYPE_DREGION_Pos)
 
#define MPU_TYPE_SEPARATE_Pos   0U
 
#define MPU_TYPE_SEPARATE_Msk   (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)
 
#define MPU_CTRL_PRIVDEFENA_Pos   2U
 
#define MPU_CTRL_PRIVDEFENA_Msk   (1UL << MPU_CTRL_PRIVDEFENA_Pos)
 
#define MPU_CTRL_HFNMIENA_Pos   1U
 
#define MPU_CTRL_HFNMIENA_Msk   (1UL << MPU_CTRL_HFNMIENA_Pos)
 
#define MPU_CTRL_ENABLE_Pos   0U
 
#define MPU_CTRL_ENABLE_Msk   (1UL /*<< MPU_CTRL_ENABLE_Pos*/)
 
#define MPU_RNR_REGION_Pos   0U
 
#define MPU_RNR_REGION_Msk   (0xFFUL /*<< MPU_RNR_REGION_Pos*/)
 
#define CoreDebug_DHCSR_DBGKEY_Pos   16U
 
#define CoreDebug_DHCSR_DBGKEY_Msk   (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
 
#define CoreDebug_DHCSR_S_RESET_ST_Pos   25U
 
#define CoreDebug_DHCSR_S_RESET_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
 
#define CoreDebug_DHCSR_S_RETIRE_ST_Pos   24U
 
#define CoreDebug_DHCSR_S_RETIRE_ST_Msk   (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
 
#define CoreDebug_DHCSR_S_LOCKUP_Pos   19U
 
#define CoreDebug_DHCSR_S_LOCKUP_Msk   (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
 
#define CoreDebug_DHCSR_S_SLEEP_Pos   18U
 
#define CoreDebug_DHCSR_S_SLEEP_Msk   (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
 
#define CoreDebug_DHCSR_S_HALT_Pos   17U
 
#define CoreDebug_DHCSR_S_HALT_Msk   (1UL << CoreDebug_DHCSR_S_HALT_Pos)
 
#define CoreDebug_DHCSR_S_REGRDY_Pos   16U
 
#define CoreDebug_DHCSR_S_REGRDY_Msk   (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
 
#define CoreDebug_DHCSR_C_MASKINTS_Pos   3U
 
#define CoreDebug_DHCSR_C_MASKINTS_Msk   (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
 
#define CoreDebug_DHCSR_C_STEP_Pos   2U
 
#define CoreDebug_DHCSR_C_STEP_Msk   (1UL << CoreDebug_DHCSR_C_STEP_Pos)
 
#define CoreDebug_DHCSR_C_HALT_Pos   1U
 
#define CoreDebug_DHCSR_C_HALT_Msk   (1UL << CoreDebug_DHCSR_C_HALT_Pos)
 
#define CoreDebug_DHCSR_C_DEBUGEN_Pos   0U
 
#define CoreDebug_DHCSR_C_DEBUGEN_Msk   (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)
 
#define CoreDebug_DCRSR_REGWnR_Pos   16U
 
#define CoreDebug_DCRSR_REGWnR_Msk   (1UL << CoreDebug_DCRSR_REGWnR_Pos)
 
#define CoreDebug_DCRSR_REGSEL_Pos   0U
 
#define CoreDebug_DCRSR_REGSEL_Msk   (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)
 
#define CoreDebug_DEMCR_VC_HARDERR_Pos   10U
 
#define CoreDebug_DEMCR_VC_HARDERR_Msk   (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
 
#define CoreDebug_DEMCR_VC_CORERESET_Pos   0U
 
#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)
 
#define _VAL2FLD(field, value)
 Mask and shift a bit field value for use in a register bit range.
 
#define _FLD2VAL(field, value)
 Mask and shift a register value to extract a bit filed value.
 
#define SCS_BASE   (0xE000E000UL)
 
#define DWT_BASE   (0xE0001000UL)
 
#define TPI_BASE   (0xE0040000UL)
 
#define CoreDebug_BASE   (0xE000EDF0UL)
 
#define SysTick_BASE   (SCS_BASE + 0x0010UL)
 
#define NVIC_BASE   (SCS_BASE + 0x0100UL)
 
#define SCB_BASE   (SCS_BASE + 0x0D00UL)
 
#define SCB   ((SCB_Type *) SCB_BASE )
 
#define SysTick   ((SysTick_Type *) SysTick_BASE )
 
#define NVIC   ((NVIC_Type *) NVIC_BASE )
 
#define DWT   ((DWT_Type *) DWT_BASE )
 
#define TPI   ((TPI_Type *) TPI_BASE )
 
#define CoreDebug   ((CoreDebug_Type *) CoreDebug_BASE )
 
#define MPU_BASE   (SCS_BASE + 0x0D90UL)
 
#define MPU   ((MPU_Type *) MPU_BASE )
 
#define NVIC_EnableIRQ   __NVIC_EnableIRQ
 
#define NVIC_GetEnableIRQ   __NVIC_GetEnableIRQ
 
#define NVIC_DisableIRQ   __NVIC_DisableIRQ
 
#define NVIC_GetPendingIRQ   __NVIC_GetPendingIRQ
 
#define NVIC_SetPendingIRQ   __NVIC_SetPendingIRQ
 
#define NVIC_ClearPendingIRQ   __NVIC_ClearPendingIRQ
 
#define NVIC_GetActive   __NVIC_GetActive
 
#define NVIC_SetPriority   __NVIC_SetPriority
 
#define NVIC_GetPriority   __NVIC_GetPriority
 
#define NVIC_SystemReset   __NVIC_SystemReset
 
#define NVIC_SetVector   __NVIC_SetVector
 
#define NVIC_GetVector   __NVIC_GetVector
 
#define NVIC_USER_IRQ_OFFSET   16
 
#define NVIC_STIR_INTID_Pos   0U
 
#define NVIC_STIR_INTID_Msk   (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLBASE_Pos   29U
 
#define SCB_VTOR_TBLBASE_Msk   (1UL << SCB_VTOR_TBLBASE_Pos)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_AIRCR_VECTRESET_Pos   0U
 
#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_CCR_NONBASETHRDENA_Pos   0U
 
#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCnSCB_ICTR_INTLINESNUM_Pos   0U
 
#define SCnSCB_ICTR_INTLINESNUM_Msk   (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)
 
#define SysTick_CTRL_COUNTFLAG_Pos   16U
 
#define SysTick_CTRL_COUNTFLAG_Msk   (1UL << SysTick_CTRL_COUNTFLAG_Pos)
 
#define SysTick_CTRL_CLKSOURCE_Pos   2U
 
#define SysTick_CTRL_CLKSOURCE_Msk   (1UL << SysTick_CTRL_CLKSOURCE_Pos)
 
#define SysTick_CTRL_TICKINT_Pos   1U
 
#define SysTick_CTRL_TICKINT_Msk   (1UL << SysTick_CTRL_TICKINT_Pos)
 
#define SysTick_CTRL_ENABLE_Pos   0U
 
#define SysTick_CTRL_ENABLE_Msk   (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)
 
#define SysTick_LOAD_RELOAD_Pos   0U
 
#define SysTick_LOAD_RELOAD_Msk   (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)
 
#define SysTick_VAL_CURRENT_Pos   0U
 
#define SysTick_VAL_CURRENT_Msk   (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)
 
#define SysTick_CALIB_NOREF_Pos   31U
 
#define SysTick_CALIB_NOREF_Msk   (1UL << SysTick_CALIB_NOREF_Pos)
 
#define SysTick_CALIB_SKEW_Pos   30U
 
#define SysTick_CALIB_SKEW_Msk   (1UL << SysTick_CALIB_SKEW_Pos)
 
#define SysTick_CALIB_TENMS_Pos   0U
 
#define SysTick_CALIB_TENMS_Msk   (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)
 
#define ITM_TPR_PRIVMASK_Pos   0U
 
#define ITM_TPR_PRIVMASK_Msk   (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
 
#define ITM_TCR_BUSY_Pos   23U
 
#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)
 
#define ITM_TCR_TraceBusID_Pos   16U
 
#define ITM_TCR_TraceBusID_Msk   (0x7FUL << ITM_TCR_TraceBusID_Pos)
 
#define ITM_TCR_GTSFREQ_Pos   10U
 
#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)
 
#define ITM_TCR_TSPrescale_Pos   8U
 
#define ITM_TCR_TSPrescale_Msk   (3UL << ITM_TCR_TSPrescale_Pos)
 
#define ITM_TCR_SWOENA_Pos   4U
 
#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)
 
#define ITM_TCR_DWTENA_Pos   3U
 
#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)
 
#define ITM_TCR_SYNCENA_Pos   2U
 
#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)
 
#define ITM_TCR_TSENA_Pos   1U
 
#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)
 
#define ITM_TCR_ITMENA_Pos   0U
 
#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)
 
#define ITM_IWR_ATVALIDM_Pos   0U
 
#define ITM_IWR_ATVALIDM_Msk   (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)
 
#define ITM_IRR_ATREADYM_Pos   0U
 
#define ITM_IRR_ATREADYM_Msk   (1UL /*<< ITM_IRR_ATREADYM_Pos*/)
 
#define ITM_IMCR_INTEGRATION_Pos   0U
 
#define ITM_IMCR_INTEGRATION_Msk   (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)
 
#define ITM_LSR_ByteAcc_Pos   2U
 
#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)
 
#define ITM_LSR_Access_Pos   1U
 
#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)
 
#define ITM_LSR_Present_Pos   0U
 
#define ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)
 
#define DWT_CTRL_NUMCOMP_Pos   28U
 
#define DWT_CTRL_NUMCOMP_Msk   (0xFUL << DWT_CTRL_NUMCOMP_Pos)
 
#define DWT_CTRL_NOTRCPKT_Pos   27U
 
#define DWT_CTRL_NOTRCPKT_Msk   (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
 
#define DWT_CTRL_NOEXTTRIG_Pos   26U
 
#define DWT_CTRL_NOEXTTRIG_Msk   (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
 
#define DWT_CTRL_NOCYCCNT_Pos   25U
 
#define DWT_CTRL_NOCYCCNT_Msk   (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
 
#define DWT_CTRL_NOPRFCNT_Pos   24U
 
#define DWT_CTRL_NOPRFCNT_Msk   (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
 
#define DWT_CTRL_CYCEVTENA_Pos   22U
 
#define DWT_CTRL_CYCEVTENA_Msk   (0x1UL << DWT_CTRL_CYCEVTENA_Pos)
 
#define DWT_CTRL_FOLDEVTENA_Pos   21U
 
#define DWT_CTRL_FOLDEVTENA_Msk   (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)
 
#define DWT_CTRL_LSUEVTENA_Pos   20U
 
#define DWT_CTRL_LSUEVTENA_Msk   (0x1UL << DWT_CTRL_LSUEVTENA_Pos)
 
#define DWT_CTRL_SLEEPEVTENA_Pos   19U
 
#define DWT_CTRL_SLEEPEVTENA_Msk   (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)
 
#define DWT_CTRL_EXCEVTENA_Pos   18U
 
#define DWT_CTRL_EXCEVTENA_Msk   (0x1UL << DWT_CTRL_EXCEVTENA_Pos)
 
#define DWT_CTRL_CPIEVTENA_Pos   17U
 
#define DWT_CTRL_CPIEVTENA_Msk   (0x1UL << DWT_CTRL_CPIEVTENA_Pos)
 
#define DWT_CTRL_EXCTRCENA_Pos   16U
 
#define DWT_CTRL_EXCTRCENA_Msk   (0x1UL << DWT_CTRL_EXCTRCENA_Pos)
 
#define DWT_CTRL_PCSAMPLENA_Pos   12U
 
#define DWT_CTRL_PCSAMPLENA_Msk   (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)
 
#define DWT_CTRL_SYNCTAP_Pos   10U
 
#define DWT_CTRL_SYNCTAP_Msk   (0x3UL << DWT_CTRL_SYNCTAP_Pos)
 
#define DWT_CTRL_CYCTAP_Pos   9U
 
#define DWT_CTRL_CYCTAP_Msk   (0x1UL << DWT_CTRL_CYCTAP_Pos)
 
#define DWT_CTRL_POSTINIT_Pos   5U
 
#define DWT_CTRL_POSTINIT_Msk   (0xFUL << DWT_CTRL_POSTINIT_Pos)
 
#define DWT_CTRL_POSTPRESET_Pos   1U
 
#define DWT_CTRL_POSTPRESET_Msk   (0xFUL << DWT_CTRL_POSTPRESET_Pos)
 
#define DWT_CTRL_CYCCNTENA_Pos   0U
 
#define DWT_CTRL_CYCCNTENA_Msk   (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)
 
#define DWT_CPICNT_CPICNT_Pos   0U
 
#define DWT_CPICNT_CPICNT_Msk   (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)
 
#define DWT_EXCCNT_EXCCNT_Pos   0U
 
#define DWT_EXCCNT_EXCCNT_Msk   (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)
 
#define DWT_SLEEPCNT_SLEEPCNT_Pos   0U
 
#define DWT_SLEEPCNT_SLEEPCNT_Msk   (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)
 
#define DWT_LSUCNT_LSUCNT_Pos   0U
 
#define DWT_LSUCNT_LSUCNT_Msk   (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)
 
#define DWT_FOLDCNT_FOLDCNT_Pos   0U
 
#define DWT_FOLDCNT_FOLDCNT_Msk   (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)
 
#define DWT_MASK_MASK_Pos   0U
 
#define DWT_MASK_MASK_Msk   (0x1FUL /*<< DWT_MASK_MASK_Pos*/)
 
#define DWT_FUNCTION_MATCHED_Pos   24U
 
#define DWT_FUNCTION_MATCHED_Msk   (0x1UL << DWT_FUNCTION_MATCHED_Pos)
 
#define DWT_FUNCTION_DATAVADDR1_Pos   16U
 
#define DWT_FUNCTION_DATAVADDR1_Msk   (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)
 
#define DWT_FUNCTION_DATAVADDR0_Pos   12U
 
#define DWT_FUNCTION_DATAVADDR0_Msk   (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)
 
#define DWT_FUNCTION_DATAVSIZE_Pos   10U
 
#define DWT_FUNCTION_DATAVSIZE_Msk   (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
 
#define DWT_FUNCTION_LNK1ENA_Pos   9U
 
#define DWT_FUNCTION_LNK1ENA_Msk   (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)
 
#define DWT_FUNCTION_DATAVMATCH_Pos   8U
 
#define DWT_FUNCTION_DATAVMATCH_Msk   (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)
 
#define DWT_FUNCTION_CYCMATCH_Pos   7U
 
#define DWT_FUNCTION_CYCMATCH_Msk   (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)
 
#define DWT_FUNCTION_EMITRANGE_Pos   5U
 
#define DWT_FUNCTION_EMITRANGE_Msk   (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)
 
#define DWT_FUNCTION_FUNCTION_Pos   0U
 
#define DWT_FUNCTION_FUNCTION_Msk   (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)
 
#define TPI_ACPR_PRESCALER_Pos   0U
 
#define TPI_ACPR_PRESCALER_Msk   (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)
 
#define TPI_SPPR_TXMODE_Pos   0U
 
#define TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
 
#define TPI_FFSR_FtNonStop_Pos   3U
 
#define TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)
 
#define TPI_FFSR_TCPresent_Pos   2U
 
#define TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)
 
#define TPI_FFSR_FtStopped_Pos   1U
 
#define TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)
 
#define TPI_FFSR_FlInProg_Pos   0U
 
#define TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
 
#define TPI_FFCR_TrigIn_Pos   8U
 
#define TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)
 
#define TPI_FFCR_EnFCont_Pos   1U
 
#define TPI_FFCR_EnFCont_Msk   (0x1UL << TPI_FFCR_EnFCont_Pos)
 
#define TPI_TRIGGER_TRIGGER_Pos   0U
 
#define TPI_TRIGGER_TRIGGER_Msk   (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)
 
#define TPI_FIFO0_ITM_ATVALID_Pos   29U
 
#define TPI_FIFO0_ITM_ATVALID_Msk   (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)
 
#define TPI_FIFO0_ITM_bytecount_Pos   27U
 
#define TPI_FIFO0_ITM_bytecount_Msk   (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)
 
#define TPI_FIFO0_ETM_ATVALID_Pos   26U
 
#define TPI_FIFO0_ETM_ATVALID_Msk   (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)
 
#define TPI_FIFO0_ETM_bytecount_Pos   24U
 
#define TPI_FIFO0_ETM_bytecount_Msk   (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)
 
#define TPI_FIFO0_ETM2_Pos   16U
 
#define TPI_FIFO0_ETM2_Msk   (0xFFUL << TPI_FIFO0_ETM2_Pos)
 
#define TPI_FIFO0_ETM1_Pos   8U
 
#define TPI_FIFO0_ETM1_Msk   (0xFFUL << TPI_FIFO0_ETM1_Pos)
 
#define TPI_FIFO0_ETM0_Pos   0U
 
#define TPI_FIFO0_ETM0_Msk   (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)
 
#define TPI_ITATBCTR2_ATREADY2_Pos   0U
 
#define TPI_ITATBCTR2_ATREADY2_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)
 
#define TPI_ITATBCTR2_ATREADY1_Pos   0U
 
#define TPI_ITATBCTR2_ATREADY1_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)
 
#define TPI_FIFO1_ITM_ATVALID_Pos   29U
 
#define TPI_FIFO1_ITM_ATVALID_Msk   (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)
 
#define TPI_FIFO1_ITM_bytecount_Pos   27U
 
#define TPI_FIFO1_ITM_bytecount_Msk   (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)
 
#define TPI_FIFO1_ETM_ATVALID_Pos   26U
 
#define TPI_FIFO1_ETM_ATVALID_Msk   (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)
 
#define TPI_FIFO1_ETM_bytecount_Pos   24U
 
#define TPI_FIFO1_ETM_bytecount_Msk   (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)
 
#define TPI_FIFO1_ITM2_Pos   16U
 
#define TPI_FIFO1_ITM2_Msk   (0xFFUL << TPI_FIFO1_ITM2_Pos)
 
#define TPI_FIFO1_ITM1_Pos   8U
 
#define TPI_FIFO1_ITM1_Msk   (0xFFUL << TPI_FIFO1_ITM1_Pos)
 
#define TPI_FIFO1_ITM0_Pos   0U
 
#define TPI_FIFO1_ITM0_Msk   (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)
 
#define TPI_ITATBCTR0_ATREADY2_Pos   0U
 
#define TPI_ITATBCTR0_ATREADY2_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)
 
#define TPI_ITATBCTR0_ATREADY1_Pos   0U
 
#define TPI_ITATBCTR0_ATREADY1_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)
 
#define TPI_ITCTRL_Mode_Pos   0U
 
#define TPI_ITCTRL_Mode_Msk   (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)
 
#define TPI_DEVID_NRZVALID_Pos   11U
 
#define TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)
 
#define TPI_DEVID_MANCVALID_Pos   10U
 
#define TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)
 
#define TPI_DEVID_PTINVALID_Pos   9U
 
#define TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)
 
#define TPI_DEVID_MinBufSz_Pos   6U
 
#define TPI_DEVID_MinBufSz_Msk   (0x7UL << TPI_DEVID_MinBufSz_Pos)
 
#define TPI_DEVID_AsynClkIn_Pos   5U
 
#define TPI_DEVID_AsynClkIn_Msk   (0x1UL << TPI_DEVID_AsynClkIn_Pos)
 
#define TPI_DEVID_NrTraceInput_Pos   0U
 
#define TPI_DEVID_NrTraceInput_Msk   (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)
 
#define TPI_DEVTYPE_SubType_Pos   4U
 
#define TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
 
#define TPI_DEVTYPE_MajorType_Pos   0U
 
#define TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)
 
#define MPU_TYPE_IREGION_Pos   16U
 
#define MPU_TYPE_IREGION_Msk   (0xFFUL << MPU_TYPE_IREGION_Pos)
 
#define MPU_TYPE_DREGION_Pos   8U
 
#define MPU_TYPE_DREGION_Msk   (0xFFUL << MPU_TYPE_DREGION_Pos)
 
#define MPU_TYPE_SEPARATE_Pos   0U
 
#define MPU_TYPE_SEPARATE_Msk   (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)
 
#define MPU_CTRL_PRIVDEFENA_Pos   2U
 
#define MPU_CTRL_PRIVDEFENA_Msk   (1UL << MPU_CTRL_PRIVDEFENA_Pos)
 
#define MPU_CTRL_HFNMIENA_Pos   1U
 
#define MPU_CTRL_HFNMIENA_Msk   (1UL << MPU_CTRL_HFNMIENA_Pos)
 
#define MPU_CTRL_ENABLE_Pos   0U
 
#define MPU_CTRL_ENABLE_Msk   (1UL /*<< MPU_CTRL_ENABLE_Pos*/)
 
#define MPU_RNR_REGION_Pos   0U
 
#define MPU_RNR_REGION_Msk   (0xFFUL /*<< MPU_RNR_REGION_Pos*/)
 
#define MPU_RBAR_ADDR_Pos   5U
 
#define MPU_RBAR_ADDR_Msk   (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)
 
#define MPU_RBAR_VALID_Pos   4U
 
#define MPU_RBAR_VALID_Msk   (1UL << MPU_RBAR_VALID_Pos)
 
#define MPU_RBAR_REGION_Pos   0U
 
#define MPU_RBAR_REGION_Msk   (0xFUL /*<< MPU_RBAR_REGION_Pos*/)
 
#define MPU_RASR_ATTRS_Pos   16U
 
#define MPU_RASR_ATTRS_Msk   (0xFFFFUL << MPU_RASR_ATTRS_Pos)
 
#define MPU_RASR_XN_Pos   28U
 
#define MPU_RASR_XN_Msk   (1UL << MPU_RASR_XN_Pos)
 
#define MPU_RASR_AP_Pos   24U
 
#define MPU_RASR_AP_Msk   (0x7UL << MPU_RASR_AP_Pos)
 
#define MPU_RASR_TEX_Pos   19U
 
#define MPU_RASR_TEX_Msk   (0x7UL << MPU_RASR_TEX_Pos)
 
#define MPU_RASR_S_Pos   18U
 
#define MPU_RASR_S_Msk   (1UL << MPU_RASR_S_Pos)
 
#define MPU_RASR_C_Pos   17U
 
#define MPU_RASR_C_Msk   (1UL << MPU_RASR_C_Pos)
 
#define MPU_RASR_B_Pos   16U
 
#define MPU_RASR_B_Msk   (1UL << MPU_RASR_B_Pos)
 
#define MPU_RASR_SRD_Pos   8U
 
#define MPU_RASR_SRD_Msk   (0xFFUL << MPU_RASR_SRD_Pos)
 
#define MPU_RASR_SIZE_Pos   1U
 
#define MPU_RASR_SIZE_Msk   (0x1FUL << MPU_RASR_SIZE_Pos)
 
#define MPU_RASR_ENABLE_Pos   0U
 
#define MPU_RASR_ENABLE_Msk   (1UL /*<< MPU_RASR_ENABLE_Pos*/)
 
#define CoreDebug_DHCSR_DBGKEY_Pos   16U
 
#define CoreDebug_DHCSR_DBGKEY_Msk   (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
 
#define CoreDebug_DHCSR_S_RESET_ST_Pos   25U
 
#define CoreDebug_DHCSR_S_RESET_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
 
#define CoreDebug_DHCSR_S_RETIRE_ST_Pos   24U
 
#define CoreDebug_DHCSR_S_RETIRE_ST_Msk   (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
 
#define CoreDebug_DHCSR_S_LOCKUP_Pos   19U
 
#define CoreDebug_DHCSR_S_LOCKUP_Msk   (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
 
#define CoreDebug_DHCSR_S_SLEEP_Pos   18U
 
#define CoreDebug_DHCSR_S_SLEEP_Msk   (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
 
#define CoreDebug_DHCSR_S_HALT_Pos   17U
 
#define CoreDebug_DHCSR_S_HALT_Msk   (1UL << CoreDebug_DHCSR_S_HALT_Pos)
 
#define CoreDebug_DHCSR_S_REGRDY_Pos   16U
 
#define CoreDebug_DHCSR_S_REGRDY_Msk   (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
 
#define CoreDebug_DHCSR_C_SNAPSTALL_Pos   5U
 
#define CoreDebug_DHCSR_C_SNAPSTALL_Msk   (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)
 
#define CoreDebug_DHCSR_C_MASKINTS_Pos   3U
 
#define CoreDebug_DHCSR_C_MASKINTS_Msk   (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
 
#define CoreDebug_DHCSR_C_STEP_Pos   2U
 
#define CoreDebug_DHCSR_C_STEP_Msk   (1UL << CoreDebug_DHCSR_C_STEP_Pos)
 
#define CoreDebug_DHCSR_C_HALT_Pos   1U
 
#define CoreDebug_DHCSR_C_HALT_Msk   (1UL << CoreDebug_DHCSR_C_HALT_Pos)
 
#define CoreDebug_DHCSR_C_DEBUGEN_Pos   0U
 
#define CoreDebug_DHCSR_C_DEBUGEN_Msk   (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)
 
#define CoreDebug_DCRSR_REGWnR_Pos   16U
 
#define CoreDebug_DCRSR_REGWnR_Msk   (1UL << CoreDebug_DCRSR_REGWnR_Pos)
 
#define CoreDebug_DCRSR_REGSEL_Pos   0U
 
#define CoreDebug_DCRSR_REGSEL_Msk   (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)
 
#define CoreDebug_DEMCR_TRCENA_Pos   24U
 
#define CoreDebug_DEMCR_TRCENA_Msk   (1UL << CoreDebug_DEMCR_TRCENA_Pos)
 
#define CoreDebug_DEMCR_MON_REQ_Pos   19U
 
#define CoreDebug_DEMCR_MON_REQ_Msk   (1UL << CoreDebug_DEMCR_MON_REQ_Pos)
 
#define CoreDebug_DEMCR_MON_STEP_Pos   18U
 
#define CoreDebug_DEMCR_MON_STEP_Msk   (1UL << CoreDebug_DEMCR_MON_STEP_Pos)
 
#define CoreDebug_DEMCR_MON_PEND_Pos   17U
 
#define CoreDebug_DEMCR_MON_PEND_Msk   (1UL << CoreDebug_DEMCR_MON_PEND_Pos)
 
#define CoreDebug_DEMCR_MON_EN_Pos   16U
 
#define CoreDebug_DEMCR_MON_EN_Msk   (1UL << CoreDebug_DEMCR_MON_EN_Pos)
 
#define CoreDebug_DEMCR_VC_HARDERR_Pos   10U
 
#define CoreDebug_DEMCR_VC_HARDERR_Msk   (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
 
#define CoreDebug_DEMCR_VC_INTERR_Pos   9U
 
#define CoreDebug_DEMCR_VC_INTERR_Msk   (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)
 
#define CoreDebug_DEMCR_VC_BUSERR_Pos   8U
 
#define CoreDebug_DEMCR_VC_BUSERR_Msk   (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)
 
#define CoreDebug_DEMCR_VC_STATERR_Pos   7U
 
#define CoreDebug_DEMCR_VC_STATERR_Msk   (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)
 
#define CoreDebug_DEMCR_VC_CHKERR_Pos   6U
 
#define CoreDebug_DEMCR_VC_CHKERR_Msk   (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)
 
#define CoreDebug_DEMCR_VC_NOCPERR_Pos   5U
 
#define CoreDebug_DEMCR_VC_NOCPERR_Msk   (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)
 
#define CoreDebug_DEMCR_VC_MMERR_Pos   4U
 
#define CoreDebug_DEMCR_VC_MMERR_Msk   (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)
 
#define CoreDebug_DEMCR_VC_CORERESET_Pos   0U
 
#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)
 
#define _VAL2FLD(field, value)
 Mask and shift a bit field value for use in a register bit range.
 
#define _FLD2VAL(field, value)
 Mask and shift a register value to extract a bit filed value.
 
#define SCS_BASE   (0xE000E000UL)
 
#define ITM_BASE   (0xE0000000UL)
 
#define DWT_BASE   (0xE0001000UL)
 
#define TPI_BASE   (0xE0040000UL)
 
#define CoreDebug_BASE   (0xE000EDF0UL)
 
#define SysTick_BASE   (SCS_BASE + 0x0010UL)
 
#define NVIC_BASE   (SCS_BASE + 0x0100UL)
 
#define SCB_BASE   (SCS_BASE + 0x0D00UL)
 
#define SCnSCB   ((SCnSCB_Type *) SCS_BASE )
 
#define SCB   ((SCB_Type *) SCB_BASE )
 
#define SysTick   ((SysTick_Type *) SysTick_BASE )
 
#define NVIC   ((NVIC_Type *) NVIC_BASE )
 
#define ITM   ((ITM_Type *) ITM_BASE )
 
#define DWT   ((DWT_Type *) DWT_BASE )
 
#define TPI   ((TPI_Type *) TPI_BASE )
 
#define CoreDebug   ((CoreDebug_Type *) CoreDebug_BASE)
 
#define MPU_BASE   (SCS_BASE + 0x0D90UL)
 
#define MPU   ((MPU_Type *) MPU_BASE )
 
#define NVIC_SetPriorityGrouping   __NVIC_SetPriorityGrouping
 
#define NVIC_GetPriorityGrouping   __NVIC_GetPriorityGrouping
 
#define NVIC_EnableIRQ   __NVIC_EnableIRQ
 
#define NVIC_GetEnableIRQ   __NVIC_GetEnableIRQ
 
#define NVIC_DisableIRQ   __NVIC_DisableIRQ
 
#define NVIC_GetPendingIRQ   __NVIC_GetPendingIRQ
 
#define NVIC_SetPendingIRQ   __NVIC_SetPendingIRQ
 
#define NVIC_ClearPendingIRQ   __NVIC_ClearPendingIRQ
 
#define NVIC_GetActive   __NVIC_GetActive
 
#define NVIC_SetPriority   __NVIC_SetPriority
 
#define NVIC_GetPriority   __NVIC_GetPriority
 
#define NVIC_SystemReset   __NVIC_SystemReset
 
#define NVIC_SetVector   __NVIC_SetVector
 
#define NVIC_GetVector   __NVIC_GetVector
 
#define NVIC_USER_IRQ_OFFSET   16
 
#define EXC_RETURN_HANDLER   (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
 
#define EXC_RETURN_THREAD_MSP   (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
 
#define EXC_RETURN_THREAD_PSP   (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
 
#define ITM_RXBUFFER_EMPTY   ((int32_t)0x5AA55AA5U)
 
#define NVIC_STIR_INTID_Pos   0U
 
#define NVIC_STIR_INTID_Msk   (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos
 
#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCnSCB_ICTR_INTLINESNUM_Pos   0U
 
#define SCnSCB_ICTR_INTLINESNUM_Msk   (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)
 
#define SysTick_CTRL_COUNTFLAG_Pos   16U
 
#define SysTick_CTRL_COUNTFLAG_Msk   (1UL << SysTick_CTRL_COUNTFLAG_Pos)
 
#define SysTick_CTRL_CLKSOURCE_Pos   2U
 
#define SysTick_CTRL_CLKSOURCE_Msk   (1UL << SysTick_CTRL_CLKSOURCE_Pos)
 
#define SysTick_CTRL_TICKINT_Pos   1U
 
#define SysTick_CTRL_TICKINT_Msk   (1UL << SysTick_CTRL_TICKINT_Pos)
 
#define SysTick_CTRL_ENABLE_Pos   0U
 
#define SysTick_CTRL_ENABLE_Msk   (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)
 
#define SysTick_LOAD_RELOAD_Pos   0U
 
#define SysTick_LOAD_RELOAD_Msk   (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)
 
#define SysTick_VAL_CURRENT_Pos   0U
 
#define SysTick_VAL_CURRENT_Msk   (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)
 
#define SysTick_CALIB_NOREF_Pos   31U
 
#define SysTick_CALIB_NOREF_Msk   (1UL << SysTick_CALIB_NOREF_Pos)
 
#define SysTick_CALIB_SKEW_Pos   30U
 
#define SysTick_CALIB_SKEW_Msk   (1UL << SysTick_CALIB_SKEW_Pos)
 
#define SysTick_CALIB_TENMS_Pos   0U
 
#define SysTick_CALIB_TENMS_Msk   (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)
 
#define ITM_TPR_PRIVMASK_Pos   0U
 
#define ITM_TPR_PRIVMASK_Msk   (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
 
#define ITM_TCR_BUSY_Pos   23U
 
#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)
 
#define ITM_TCR_GTSFREQ_Pos   10U
 
#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)
 
#define ITM_TCR_SWOENA_Pos   4U
 
#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)
 
#define ITM_TCR_DWTENA_Pos   3U
 
#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)
 
#define ITM_TCR_SYNCENA_Pos   2U
 
#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)
 
#define ITM_TCR_TSENA_Pos   1U
 
#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)
 
#define ITM_TCR_ITMENA_Pos   0U
 
#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)
 
#define ITM_IWR_ATVALIDM_Pos   0U
 
#define ITM_IWR_ATVALIDM_Msk   (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)
 
#define ITM_IRR_ATREADYM_Pos   0U
 
#define ITM_IRR_ATREADYM_Msk   (1UL /*<< ITM_IRR_ATREADYM_Pos*/)
 
#define ITM_IMCR_INTEGRATION_Pos   0U
 
#define ITM_IMCR_INTEGRATION_Msk   (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)
 
#define ITM_LSR_ByteAcc_Pos   2U
 
#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)
 
#define ITM_LSR_Access_Pos   1U
 
#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)
 
#define ITM_LSR_Present_Pos   0U
 
#define ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)
 
#define DWT_CTRL_NUMCOMP_Pos   28U
 
#define DWT_CTRL_NUMCOMP_Msk   (0xFUL << DWT_CTRL_NUMCOMP_Pos)
 
#define DWT_CTRL_NOTRCPKT_Pos   27U
 
#define DWT_CTRL_NOTRCPKT_Msk   (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
 
#define DWT_CTRL_NOEXTTRIG_Pos   26U
 
#define DWT_CTRL_NOEXTTRIG_Msk   (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
 
#define DWT_CTRL_NOCYCCNT_Pos   25U
 
#define DWT_CTRL_NOCYCCNT_Msk   (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
 
#define DWT_CTRL_NOPRFCNT_Pos   24U
 
#define DWT_CTRL_NOPRFCNT_Msk   (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
 
#define DWT_CTRL_CYCEVTENA_Pos   22U
 
#define DWT_CTRL_CYCEVTENA_Msk   (0x1UL << DWT_CTRL_CYCEVTENA_Pos)
 
#define DWT_CTRL_FOLDEVTENA_Pos   21U
 
#define DWT_CTRL_FOLDEVTENA_Msk   (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)
 
#define DWT_CTRL_LSUEVTENA_Pos   20U
 
#define DWT_CTRL_LSUEVTENA_Msk   (0x1UL << DWT_CTRL_LSUEVTENA_Pos)
 
#define DWT_CTRL_SLEEPEVTENA_Pos   19U
 
#define DWT_CTRL_SLEEPEVTENA_Msk   (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)
 
#define DWT_CTRL_EXCEVTENA_Pos   18U
 
#define DWT_CTRL_EXCEVTENA_Msk   (0x1UL << DWT_CTRL_EXCEVTENA_Pos)
 
#define DWT_CTRL_CPIEVTENA_Pos   17U
 
#define DWT_CTRL_CPIEVTENA_Msk   (0x1UL << DWT_CTRL_CPIEVTENA_Pos)
 
#define DWT_CTRL_EXCTRCENA_Pos   16U
 
#define DWT_CTRL_EXCTRCENA_Msk   (0x1UL << DWT_CTRL_EXCTRCENA_Pos)
 
#define DWT_CTRL_PCSAMPLENA_Pos   12U
 
#define DWT_CTRL_PCSAMPLENA_Msk   (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)
 
#define DWT_CTRL_SYNCTAP_Pos   10U
 
#define DWT_CTRL_SYNCTAP_Msk   (0x3UL << DWT_CTRL_SYNCTAP_Pos)
 
#define DWT_CTRL_CYCTAP_Pos   9U
 
#define DWT_CTRL_CYCTAP_Msk   (0x1UL << DWT_CTRL_CYCTAP_Pos)
 
#define DWT_CTRL_POSTINIT_Pos   5U
 
#define DWT_CTRL_POSTINIT_Msk   (0xFUL << DWT_CTRL_POSTINIT_Pos)
 
#define DWT_CTRL_POSTPRESET_Pos   1U
 
#define DWT_CTRL_POSTPRESET_Msk   (0xFUL << DWT_CTRL_POSTPRESET_Pos)
 
#define DWT_CTRL_CYCCNTENA_Pos   0U
 
#define DWT_CTRL_CYCCNTENA_Msk   (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)
 
#define DWT_CPICNT_CPICNT_Pos   0U
 
#define DWT_CPICNT_CPICNT_Msk   (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)
 
#define DWT_EXCCNT_EXCCNT_Pos   0U
 
#define DWT_EXCCNT_EXCCNT_Msk   (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)
 
#define DWT_SLEEPCNT_SLEEPCNT_Pos   0U
 
#define DWT_SLEEPCNT_SLEEPCNT_Msk   (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)
 
#define DWT_LSUCNT_LSUCNT_Pos   0U
 
#define DWT_LSUCNT_LSUCNT_Msk   (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)
 
#define DWT_FOLDCNT_FOLDCNT_Pos   0U
 
#define DWT_FOLDCNT_FOLDCNT_Msk   (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)
 
#define DWT_FUNCTION_MATCHED_Pos   24U
 
#define DWT_FUNCTION_MATCHED_Msk   (0x1UL << DWT_FUNCTION_MATCHED_Pos)
 
#define DWT_FUNCTION_DATAVSIZE_Pos   10U
 
#define DWT_FUNCTION_DATAVSIZE_Msk   (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
 
#define TPI_ACPR_PRESCALER_Pos   0U
 
#define TPI_ACPR_PRESCALER_Msk   (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)
 
#define TPI_SPPR_TXMODE_Pos   0U
 
#define TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
 
#define TPI_FFSR_FtNonStop_Pos   3U
 
#define TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)
 
#define TPI_FFSR_TCPresent_Pos   2U
 
#define TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)
 
#define TPI_FFSR_FtStopped_Pos   1U
 
#define TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)
 
#define TPI_FFSR_FlInProg_Pos   0U
 
#define TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
 
#define TPI_FFCR_TrigIn_Pos   8U
 
#define TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)
 
#define TPI_FFCR_EnFCont_Pos   1U
 
#define TPI_FFCR_EnFCont_Msk   (0x1UL << TPI_FFCR_EnFCont_Pos)
 
#define TPI_TRIGGER_TRIGGER_Pos   0U
 
#define TPI_TRIGGER_TRIGGER_Msk   (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)
 
#define TPI_ITCTRL_Mode_Pos   0U
 
#define TPI_ITCTRL_Mode_Msk   (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)
 
#define TPI_DEVID_NRZVALID_Pos   11U
 
#define TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)
 
#define TPI_DEVID_MANCVALID_Pos   10U
 
#define TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)
 
#define TPI_DEVID_PTINVALID_Pos   9U
 
#define TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)
 
#define TPI_DEVID_NrTraceInput_Pos   0U
 
#define TPI_DEVID_NrTraceInput_Msk   (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)
 
#define TPI_DEVTYPE_SubType_Pos   4U
 
#define TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
 
#define TPI_DEVTYPE_MajorType_Pos   0U
 
#define TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)
 
#define MPU_TYPE_IREGION_Pos   16U
 
#define MPU_TYPE_IREGION_Msk   (0xFFUL << MPU_TYPE_IREGION_Pos)
 
#define MPU_TYPE_DREGION_Pos   8U
 
#define MPU_TYPE_DREGION_Msk   (0xFFUL << MPU_TYPE_DREGION_Pos)
 
#define MPU_TYPE_SEPARATE_Pos   0U
 
#define MPU_TYPE_SEPARATE_Msk   (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)
 
#define MPU_CTRL_PRIVDEFENA_Pos   2U
 
#define MPU_CTRL_PRIVDEFENA_Msk   (1UL << MPU_CTRL_PRIVDEFENA_Pos)
 
#define MPU_CTRL_HFNMIENA_Pos   1U
 
#define MPU_CTRL_HFNMIENA_Msk   (1UL << MPU_CTRL_HFNMIENA_Pos)
 
#define MPU_CTRL_ENABLE_Pos   0U
 
#define MPU_CTRL_ENABLE_Msk   (1UL /*<< MPU_CTRL_ENABLE_Pos*/)
 
#define MPU_RNR_REGION_Pos   0U
 
#define MPU_RNR_REGION_Msk   (0xFFUL /*<< MPU_RNR_REGION_Pos*/)
 
#define CoreDebug_DHCSR_DBGKEY_Pos   16U
 
#define CoreDebug_DHCSR_DBGKEY_Msk   (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
 
#define CoreDebug_DHCSR_S_RESET_ST_Pos   25U
 
#define CoreDebug_DHCSR_S_RESET_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
 
#define CoreDebug_DHCSR_S_RETIRE_ST_Pos   24U
 
#define CoreDebug_DHCSR_S_RETIRE_ST_Msk   (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
 
#define CoreDebug_DHCSR_S_LOCKUP_Pos   19U
 
#define CoreDebug_DHCSR_S_LOCKUP_Msk   (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
 
#define CoreDebug_DHCSR_S_SLEEP_Pos   18U
 
#define CoreDebug_DHCSR_S_SLEEP_Msk   (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
 
#define CoreDebug_DHCSR_S_HALT_Pos   17U
 
#define CoreDebug_DHCSR_S_HALT_Msk   (1UL << CoreDebug_DHCSR_S_HALT_Pos)
 
#define CoreDebug_DHCSR_S_REGRDY_Pos   16U
 
#define CoreDebug_DHCSR_S_REGRDY_Msk   (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
 
#define CoreDebug_DHCSR_C_SNAPSTALL_Pos   5U
 
#define CoreDebug_DHCSR_C_SNAPSTALL_Msk   (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)
 
#define CoreDebug_DHCSR_C_MASKINTS_Pos   3U
 
#define CoreDebug_DHCSR_C_MASKINTS_Msk   (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
 
#define CoreDebug_DHCSR_C_STEP_Pos   2U
 
#define CoreDebug_DHCSR_C_STEP_Msk   (1UL << CoreDebug_DHCSR_C_STEP_Pos)
 
#define CoreDebug_DHCSR_C_HALT_Pos   1U
 
#define CoreDebug_DHCSR_C_HALT_Msk   (1UL << CoreDebug_DHCSR_C_HALT_Pos)
 
#define CoreDebug_DHCSR_C_DEBUGEN_Pos   0U
 
#define CoreDebug_DHCSR_C_DEBUGEN_Msk   (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)
 
#define CoreDebug_DCRSR_REGWnR_Pos   16U
 
#define CoreDebug_DCRSR_REGWnR_Msk   (1UL << CoreDebug_DCRSR_REGWnR_Pos)
 
#define CoreDebug_DCRSR_REGSEL_Pos   0U
 
#define CoreDebug_DCRSR_REGSEL_Msk   (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)
 
#define CoreDebug_DEMCR_TRCENA_Pos   24U
 
#define CoreDebug_DEMCR_TRCENA_Msk   (1UL << CoreDebug_DEMCR_TRCENA_Pos)
 
#define CoreDebug_DEMCR_MON_REQ_Pos   19U
 
#define CoreDebug_DEMCR_MON_REQ_Msk   (1UL << CoreDebug_DEMCR_MON_REQ_Pos)
 
#define CoreDebug_DEMCR_MON_STEP_Pos   18U
 
#define CoreDebug_DEMCR_MON_STEP_Msk   (1UL << CoreDebug_DEMCR_MON_STEP_Pos)
 
#define CoreDebug_DEMCR_MON_PEND_Pos   17U
 
#define CoreDebug_DEMCR_MON_PEND_Msk   (1UL << CoreDebug_DEMCR_MON_PEND_Pos)
 
#define CoreDebug_DEMCR_MON_EN_Pos   16U
 
#define CoreDebug_DEMCR_MON_EN_Msk   (1UL << CoreDebug_DEMCR_MON_EN_Pos)
 
#define CoreDebug_DEMCR_VC_HARDERR_Pos   10U
 
#define CoreDebug_DEMCR_VC_HARDERR_Msk   (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
 
#define CoreDebug_DEMCR_VC_INTERR_Pos   9U
 
#define CoreDebug_DEMCR_VC_INTERR_Msk   (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)
 
#define CoreDebug_DEMCR_VC_BUSERR_Pos   8U
 
#define CoreDebug_DEMCR_VC_BUSERR_Msk   (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)
 
#define CoreDebug_DEMCR_VC_STATERR_Pos   7U
 
#define CoreDebug_DEMCR_VC_STATERR_Msk   (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)
 
#define CoreDebug_DEMCR_VC_CHKERR_Pos   6U
 
#define CoreDebug_DEMCR_VC_CHKERR_Msk   (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)
 
#define CoreDebug_DEMCR_VC_NOCPERR_Pos   5U
 
#define CoreDebug_DEMCR_VC_NOCPERR_Msk   (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)
 
#define CoreDebug_DEMCR_VC_MMERR_Pos   4U
 
#define CoreDebug_DEMCR_VC_MMERR_Msk   (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)
 
#define CoreDebug_DEMCR_VC_CORERESET_Pos   0U
 
#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)
 
#define _VAL2FLD(field, value)
 Mask and shift a bit field value for use in a register bit range.
 
#define _FLD2VAL(field, value)
 Mask and shift a register value to extract a bit filed value.
 
#define SCS_BASE   (0xE000E000UL)
 
#define ITM_BASE   (0xE0000000UL)
 
#define DWT_BASE   (0xE0001000UL)
 
#define TPI_BASE   (0xE0040000UL)
 
#define CoreDebug_BASE   (0xE000EDF0UL)
 
#define SysTick_BASE   (SCS_BASE + 0x0010UL)
 
#define NVIC_BASE   (SCS_BASE + 0x0100UL)
 
#define SCB_BASE   (SCS_BASE + 0x0D00UL)
 
#define SCnSCB   ((SCnSCB_Type *) SCS_BASE )
 
#define SCB   ((SCB_Type *) SCB_BASE )
 
#define SysTick   ((SysTick_Type *) SysTick_BASE )
 
#define NVIC   ((NVIC_Type *) NVIC_BASE )
 
#define ITM   ((ITM_Type *) ITM_BASE )
 
#define DWT   ((DWT_Type *) DWT_BASE )
 
#define TPI   ((TPI_Type *) TPI_BASE )
 
#define CoreDebug   ((CoreDebug_Type *) CoreDebug_BASE )
 
#define MPU_BASE   (SCS_BASE + 0x0D90UL)
 
#define MPU   ((MPU_Type *) MPU_BASE )
 
#define NVIC_SetPriorityGrouping   __NVIC_SetPriorityGrouping
 
#define NVIC_GetPriorityGrouping   __NVIC_GetPriorityGrouping
 
#define NVIC_EnableIRQ   __NVIC_EnableIRQ
 
#define NVIC_GetEnableIRQ   __NVIC_GetEnableIRQ
 
#define NVIC_DisableIRQ   __NVIC_DisableIRQ
 
#define NVIC_GetPendingIRQ   __NVIC_GetPendingIRQ
 
#define NVIC_SetPendingIRQ   __NVIC_SetPendingIRQ
 
#define NVIC_ClearPendingIRQ   __NVIC_ClearPendingIRQ
 
#define NVIC_GetActive   __NVIC_GetActive
 
#define NVIC_SetPriority   __NVIC_SetPriority
 
#define NVIC_GetPriority   __NVIC_GetPriority
 
#define NVIC_SystemReset   __NVIC_SystemReset
 
#define NVIC_SetVector   __NVIC_SetVector
 
#define NVIC_GetVector   __NVIC_GetVector
 
#define NVIC_USER_IRQ_OFFSET   16
 
#define ITM_RXBUFFER_EMPTY   ((int32_t)0x5AA55AA5U)
 
#define NVIC_STIR_INTID_Pos   0U
 
#define NVIC_STIR_INTID_Msk   (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_AIRCR_VECTRESET_Pos   0U
 
#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_CCR_NONBASETHRDENA_Pos   0U
 
#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCnSCB_ICTR_INTLINESNUM_Pos   0U
 
#define SCnSCB_ICTR_INTLINESNUM_Msk   (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)
 
#define SysTick_CTRL_COUNTFLAG_Pos   16U
 
#define SysTick_CTRL_COUNTFLAG_Msk   (1UL << SysTick_CTRL_COUNTFLAG_Pos)
 
#define SysTick_CTRL_CLKSOURCE_Pos   2U
 
#define SysTick_CTRL_CLKSOURCE_Msk   (1UL << SysTick_CTRL_CLKSOURCE_Pos)
 
#define SysTick_CTRL_TICKINT_Pos   1U
 
#define SysTick_CTRL_TICKINT_Msk   (1UL << SysTick_CTRL_TICKINT_Pos)
 
#define SysTick_CTRL_ENABLE_Pos   0U
 
#define SysTick_CTRL_ENABLE_Msk   (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)
 
#define SysTick_LOAD_RELOAD_Pos   0U
 
#define SysTick_LOAD_RELOAD_Msk   (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)
 
#define SysTick_VAL_CURRENT_Pos   0U
 
#define SysTick_VAL_CURRENT_Msk   (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)
 
#define SysTick_CALIB_NOREF_Pos   31U
 
#define SysTick_CALIB_NOREF_Msk   (1UL << SysTick_CALIB_NOREF_Pos)
 
#define SysTick_CALIB_SKEW_Pos   30U
 
#define SysTick_CALIB_SKEW_Msk   (1UL << SysTick_CALIB_SKEW_Pos)
 
#define SysTick_CALIB_TENMS_Pos   0U
 
#define SysTick_CALIB_TENMS_Msk   (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)
 
#define ITM_TPR_PRIVMASK_Pos   0U
 
#define ITM_TPR_PRIVMASK_Msk   (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
 
#define ITM_TCR_BUSY_Pos   23U
 
#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)
 
#define ITM_TCR_TraceBusID_Pos   16U
 
#define ITM_TCR_TraceBusID_Msk   (0x7FUL << ITM_TCR_TraceBusID_Pos)
 
#define ITM_TCR_GTSFREQ_Pos   10U
 
#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)
 
#define ITM_TCR_TSPrescale_Pos   8U
 
#define ITM_TCR_TSPrescale_Msk   (3UL << ITM_TCR_TSPrescale_Pos)
 
#define ITM_TCR_SWOENA_Pos   4U
 
#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)
 
#define ITM_TCR_DWTENA_Pos   3U
 
#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)
 
#define ITM_TCR_SYNCENA_Pos   2U
 
#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)
 
#define ITM_TCR_TSENA_Pos   1U
 
#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)
 
#define ITM_TCR_ITMENA_Pos   0U
 
#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)
 
#define ITM_IWR_ATVALIDM_Pos   0U
 
#define ITM_IWR_ATVALIDM_Msk   (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)
 
#define ITM_IRR_ATREADYM_Pos   0U
 
#define ITM_IRR_ATREADYM_Msk   (1UL /*<< ITM_IRR_ATREADYM_Pos*/)
 
#define ITM_IMCR_INTEGRATION_Pos   0U
 
#define ITM_IMCR_INTEGRATION_Msk   (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)
 
#define ITM_LSR_ByteAcc_Pos   2U
 
#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)
 
#define ITM_LSR_Access_Pos   1U
 
#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)
 
#define ITM_LSR_Present_Pos   0U
 
#define ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)
 
#define DWT_CTRL_NUMCOMP_Pos   28U
 
#define DWT_CTRL_NUMCOMP_Msk   (0xFUL << DWT_CTRL_NUMCOMP_Pos)
 
#define DWT_CTRL_NOTRCPKT_Pos   27U
 
#define DWT_CTRL_NOTRCPKT_Msk   (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
 
#define DWT_CTRL_NOEXTTRIG_Pos   26U
 
#define DWT_CTRL_NOEXTTRIG_Msk   (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
 
#define DWT_CTRL_NOCYCCNT_Pos   25U
 
#define DWT_CTRL_NOCYCCNT_Msk   (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
 
#define DWT_CTRL_NOPRFCNT_Pos   24U
 
#define DWT_CTRL_NOPRFCNT_Msk   (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
 
#define DWT_CTRL_CYCEVTENA_Pos   22U
 
#define DWT_CTRL_CYCEVTENA_Msk   (0x1UL << DWT_CTRL_CYCEVTENA_Pos)
 
#define DWT_CTRL_FOLDEVTENA_Pos   21U
 
#define DWT_CTRL_FOLDEVTENA_Msk   (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)
 
#define DWT_CTRL_LSUEVTENA_Pos   20U
 
#define DWT_CTRL_LSUEVTENA_Msk   (0x1UL << DWT_CTRL_LSUEVTENA_Pos)
 
#define DWT_CTRL_SLEEPEVTENA_Pos   19U
 
#define DWT_CTRL_SLEEPEVTENA_Msk   (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)
 
#define DWT_CTRL_EXCEVTENA_Pos   18U
 
#define DWT_CTRL_EXCEVTENA_Msk   (0x1UL << DWT_CTRL_EXCEVTENA_Pos)
 
#define DWT_CTRL_CPIEVTENA_Pos   17U
 
#define DWT_CTRL_CPIEVTENA_Msk   (0x1UL << DWT_CTRL_CPIEVTENA_Pos)
 
#define DWT_CTRL_EXCTRCENA_Pos   16U
 
#define DWT_CTRL_EXCTRCENA_Msk   (0x1UL << DWT_CTRL_EXCTRCENA_Pos)
 
#define DWT_CTRL_PCSAMPLENA_Pos   12U
 
#define DWT_CTRL_PCSAMPLENA_Msk   (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)
 
#define DWT_CTRL_SYNCTAP_Pos   10U
 
#define DWT_CTRL_SYNCTAP_Msk   (0x3UL << DWT_CTRL_SYNCTAP_Pos)
 
#define DWT_CTRL_CYCTAP_Pos   9U
 
#define DWT_CTRL_CYCTAP_Msk   (0x1UL << DWT_CTRL_CYCTAP_Pos)
 
#define DWT_CTRL_POSTINIT_Pos   5U
 
#define DWT_CTRL_POSTINIT_Msk   (0xFUL << DWT_CTRL_POSTINIT_Pos)
 
#define DWT_CTRL_POSTPRESET_Pos   1U
 
#define DWT_CTRL_POSTPRESET_Msk   (0xFUL << DWT_CTRL_POSTPRESET_Pos)
 
#define DWT_CTRL_CYCCNTENA_Pos   0U
 
#define DWT_CTRL_CYCCNTENA_Msk   (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)
 
#define DWT_CPICNT_CPICNT_Pos   0U
 
#define DWT_CPICNT_CPICNT_Msk   (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)
 
#define DWT_EXCCNT_EXCCNT_Pos   0U
 
#define DWT_EXCCNT_EXCCNT_Msk   (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)
 
#define DWT_SLEEPCNT_SLEEPCNT_Pos   0U
 
#define DWT_SLEEPCNT_SLEEPCNT_Msk   (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)
 
#define DWT_LSUCNT_LSUCNT_Pos   0U
 
#define DWT_LSUCNT_LSUCNT_Msk   (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)
 
#define DWT_FOLDCNT_FOLDCNT_Pos   0U
 
#define DWT_FOLDCNT_FOLDCNT_Msk   (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)
 
#define DWT_MASK_MASK_Pos   0U
 
#define DWT_MASK_MASK_Msk   (0x1FUL /*<< DWT_MASK_MASK_Pos*/)
 
#define DWT_FUNCTION_MATCHED_Pos   24U
 
#define DWT_FUNCTION_MATCHED_Msk   (0x1UL << DWT_FUNCTION_MATCHED_Pos)
 
#define DWT_FUNCTION_DATAVADDR1_Pos   16U
 
#define DWT_FUNCTION_DATAVADDR1_Msk   (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)
 
#define DWT_FUNCTION_DATAVADDR0_Pos   12U
 
#define DWT_FUNCTION_DATAVADDR0_Msk   (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)
 
#define DWT_FUNCTION_DATAVSIZE_Pos   10U
 
#define DWT_FUNCTION_DATAVSIZE_Msk   (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
 
#define DWT_FUNCTION_LNK1ENA_Pos   9U
 
#define DWT_FUNCTION_LNK1ENA_Msk   (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)
 
#define DWT_FUNCTION_DATAVMATCH_Pos   8U
 
#define DWT_FUNCTION_DATAVMATCH_Msk   (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)
 
#define DWT_FUNCTION_CYCMATCH_Pos   7U
 
#define DWT_FUNCTION_CYCMATCH_Msk   (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)
 
#define DWT_FUNCTION_EMITRANGE_Pos   5U
 
#define DWT_FUNCTION_EMITRANGE_Msk   (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)
 
#define DWT_FUNCTION_FUNCTION_Pos   0U
 
#define DWT_FUNCTION_FUNCTION_Msk   (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)
 
#define TPI_ACPR_PRESCALER_Pos   0U
 
#define TPI_ACPR_PRESCALER_Msk   (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)
 
#define TPI_SPPR_TXMODE_Pos   0U
 
#define TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
 
#define TPI_FFSR_FtNonStop_Pos   3U
 
#define TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)
 
#define TPI_FFSR_TCPresent_Pos   2U
 
#define TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)
 
#define TPI_FFSR_FtStopped_Pos   1U
 
#define TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)
 
#define TPI_FFSR_FlInProg_Pos   0U
 
#define TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
 
#define TPI_FFCR_TrigIn_Pos   8U
 
#define TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)
 
#define TPI_FFCR_EnFCont_Pos   1U
 
#define TPI_FFCR_EnFCont_Msk   (0x1UL << TPI_FFCR_EnFCont_Pos)
 
#define TPI_TRIGGER_TRIGGER_Pos   0U
 
#define TPI_TRIGGER_TRIGGER_Msk   (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)
 
#define TPI_FIFO0_ITM_ATVALID_Pos   29U
 
#define TPI_FIFO0_ITM_ATVALID_Msk   (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)
 
#define TPI_FIFO0_ITM_bytecount_Pos   27U
 
#define TPI_FIFO0_ITM_bytecount_Msk   (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)
 
#define TPI_FIFO0_ETM_ATVALID_Pos   26U
 
#define TPI_FIFO0_ETM_ATVALID_Msk   (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)
 
#define TPI_FIFO0_ETM_bytecount_Pos   24U
 
#define TPI_FIFO0_ETM_bytecount_Msk   (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)
 
#define TPI_FIFO0_ETM2_Pos   16U
 
#define TPI_FIFO0_ETM2_Msk   (0xFFUL << TPI_FIFO0_ETM2_Pos)
 
#define TPI_FIFO0_ETM1_Pos   8U
 
#define TPI_FIFO0_ETM1_Msk   (0xFFUL << TPI_FIFO0_ETM1_Pos)
 
#define TPI_FIFO0_ETM0_Pos   0U
 
#define TPI_FIFO0_ETM0_Msk   (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)
 
#define TPI_ITATBCTR2_ATREADY2_Pos   0U
 
#define TPI_ITATBCTR2_ATREADY2_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)
 
#define TPI_ITATBCTR2_ATREADY1_Pos   0U
 
#define TPI_ITATBCTR2_ATREADY1_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)
 
#define TPI_FIFO1_ITM_ATVALID_Pos   29U
 
#define TPI_FIFO1_ITM_ATVALID_Msk   (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)
 
#define TPI_FIFO1_ITM_bytecount_Pos   27U
 
#define TPI_FIFO1_ITM_bytecount_Msk   (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)
 
#define TPI_FIFO1_ETM_ATVALID_Pos   26U
 
#define TPI_FIFO1_ETM_ATVALID_Msk   (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)
 
#define TPI_FIFO1_ETM_bytecount_Pos   24U
 
#define TPI_FIFO1_ETM_bytecount_Msk   (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)
 
#define TPI_FIFO1_ITM2_Pos   16U
 
#define TPI_FIFO1_ITM2_Msk   (0xFFUL << TPI_FIFO1_ITM2_Pos)
 
#define TPI_FIFO1_ITM1_Pos   8U
 
#define TPI_FIFO1_ITM1_Msk   (0xFFUL << TPI_FIFO1_ITM1_Pos)
 
#define TPI_FIFO1_ITM0_Pos   0U
 
#define TPI_FIFO1_ITM0_Msk   (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)
 
#define TPI_ITATBCTR0_ATREADY2_Pos   0U
 
#define TPI_ITATBCTR0_ATREADY2_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)
 
#define TPI_ITATBCTR0_ATREADY1_Pos   0U
 
#define TPI_ITATBCTR0_ATREADY1_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)
 
#define TPI_ITCTRL_Mode_Pos   0U
 
#define TPI_ITCTRL_Mode_Msk   (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)
 
#define TPI_DEVID_NRZVALID_Pos   11U
 
#define TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)
 
#define TPI_DEVID_MANCVALID_Pos   10U
 
#define TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)
 
#define TPI_DEVID_PTINVALID_Pos   9U
 
#define TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)
 
#define TPI_DEVID_MinBufSz_Pos   6U
 
#define TPI_DEVID_MinBufSz_Msk   (0x7UL << TPI_DEVID_MinBufSz_Pos)
 
#define TPI_DEVID_AsynClkIn_Pos   5U
 
#define TPI_DEVID_AsynClkIn_Msk   (0x1UL << TPI_DEVID_AsynClkIn_Pos)
 
#define TPI_DEVID_NrTraceInput_Pos   0U
 
#define TPI_DEVID_NrTraceInput_Msk   (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)
 
#define TPI_DEVTYPE_SubType_Pos   4U
 
#define TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
 
#define TPI_DEVTYPE_MajorType_Pos   0U
 
#define TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)
 
#define MPU_TYPE_IREGION_Pos   16U
 
#define MPU_TYPE_IREGION_Msk   (0xFFUL << MPU_TYPE_IREGION_Pos)
 
#define MPU_TYPE_DREGION_Pos   8U
 
#define MPU_TYPE_DREGION_Msk   (0xFFUL << MPU_TYPE_DREGION_Pos)
 
#define MPU_TYPE_SEPARATE_Pos   0U
 
#define MPU_TYPE_SEPARATE_Msk   (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)
 
#define MPU_CTRL_PRIVDEFENA_Pos   2U
 
#define MPU_CTRL_PRIVDEFENA_Msk   (1UL << MPU_CTRL_PRIVDEFENA_Pos)
 
#define MPU_CTRL_HFNMIENA_Pos   1U
 
#define MPU_CTRL_HFNMIENA_Msk   (1UL << MPU_CTRL_HFNMIENA_Pos)
 
#define MPU_CTRL_ENABLE_Pos   0U
 
#define MPU_CTRL_ENABLE_Msk   (1UL /*<< MPU_CTRL_ENABLE_Pos*/)
 
#define MPU_RNR_REGION_Pos   0U
 
#define MPU_RNR_REGION_Msk   (0xFFUL /*<< MPU_RNR_REGION_Pos*/)
 
#define MPU_RBAR_ADDR_Pos   5U
 
#define MPU_RBAR_ADDR_Msk   (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)
 
#define MPU_RBAR_VALID_Pos   4U
 
#define MPU_RBAR_VALID_Msk   (1UL << MPU_RBAR_VALID_Pos)
 
#define MPU_RBAR_REGION_Pos   0U
 
#define MPU_RBAR_REGION_Msk   (0xFUL /*<< MPU_RBAR_REGION_Pos*/)
 
#define MPU_RASR_ATTRS_Pos   16U
 
#define MPU_RASR_ATTRS_Msk   (0xFFFFUL << MPU_RASR_ATTRS_Pos)
 
#define MPU_RASR_XN_Pos   28U
 
#define MPU_RASR_XN_Msk   (1UL << MPU_RASR_XN_Pos)
 
#define MPU_RASR_AP_Pos   24U
 
#define MPU_RASR_AP_Msk   (0x7UL << MPU_RASR_AP_Pos)
 
#define MPU_RASR_TEX_Pos   19U
 
#define MPU_RASR_TEX_Msk   (0x7UL << MPU_RASR_TEX_Pos)
 
#define MPU_RASR_S_Pos   18U
 
#define MPU_RASR_S_Msk   (1UL << MPU_RASR_S_Pos)
 
#define MPU_RASR_C_Pos   17U
 
#define MPU_RASR_C_Msk   (1UL << MPU_RASR_C_Pos)
 
#define MPU_RASR_B_Pos   16U
 
#define MPU_RASR_B_Msk   (1UL << MPU_RASR_B_Pos)
 
#define MPU_RASR_SRD_Pos   8U
 
#define MPU_RASR_SRD_Msk   (0xFFUL << MPU_RASR_SRD_Pos)
 
#define MPU_RASR_SIZE_Pos   1U
 
#define MPU_RASR_SIZE_Msk   (0x1FUL << MPU_RASR_SIZE_Pos)
 
#define MPU_RASR_ENABLE_Pos   0U
 
#define MPU_RASR_ENABLE_Msk   (1UL /*<< MPU_RASR_ENABLE_Pos*/)
 
#define CoreDebug_DHCSR_DBGKEY_Pos   16U
 
#define CoreDebug_DHCSR_DBGKEY_Msk   (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
 
#define CoreDebug_DHCSR_S_RESET_ST_Pos   25U
 
#define CoreDebug_DHCSR_S_RESET_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
 
#define CoreDebug_DHCSR_S_RETIRE_ST_Pos   24U
 
#define CoreDebug_DHCSR_S_RETIRE_ST_Msk   (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
 
#define CoreDebug_DHCSR_S_LOCKUP_Pos   19U
 
#define CoreDebug_DHCSR_S_LOCKUP_Msk   (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
 
#define CoreDebug_DHCSR_S_SLEEP_Pos   18U
 
#define CoreDebug_DHCSR_S_SLEEP_Msk   (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
 
#define CoreDebug_DHCSR_S_HALT_Pos   17U
 
#define CoreDebug_DHCSR_S_HALT_Msk   (1UL << CoreDebug_DHCSR_S_HALT_Pos)
 
#define CoreDebug_DHCSR_S_REGRDY_Pos   16U
 
#define CoreDebug_DHCSR_S_REGRDY_Msk   (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
 
#define CoreDebug_DHCSR_C_SNAPSTALL_Pos   5U
 
#define CoreDebug_DHCSR_C_SNAPSTALL_Msk   (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)
 
#define CoreDebug_DHCSR_C_MASKINTS_Pos   3U
 
#define CoreDebug_DHCSR_C_MASKINTS_Msk   (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
 
#define CoreDebug_DHCSR_C_STEP_Pos   2U
 
#define CoreDebug_DHCSR_C_STEP_Msk   (1UL << CoreDebug_DHCSR_C_STEP_Pos)
 
#define CoreDebug_DHCSR_C_HALT_Pos   1U
 
#define CoreDebug_DHCSR_C_HALT_Msk   (1UL << CoreDebug_DHCSR_C_HALT_Pos)
 
#define CoreDebug_DHCSR_C_DEBUGEN_Pos   0U
 
#define CoreDebug_DHCSR_C_DEBUGEN_Msk   (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)
 
#define CoreDebug_DCRSR_REGWnR_Pos   16U
 
#define CoreDebug_DCRSR_REGWnR_Msk   (1UL << CoreDebug_DCRSR_REGWnR_Pos)
 
#define CoreDebug_DCRSR_REGSEL_Pos   0U
 
#define CoreDebug_DCRSR_REGSEL_Msk   (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)
 
#define CoreDebug_DEMCR_TRCENA_Pos   24U
 
#define CoreDebug_DEMCR_TRCENA_Msk   (1UL << CoreDebug_DEMCR_TRCENA_Pos)
 
#define CoreDebug_DEMCR_MON_REQ_Pos   19U
 
#define CoreDebug_DEMCR_MON_REQ_Msk   (1UL << CoreDebug_DEMCR_MON_REQ_Pos)
 
#define CoreDebug_DEMCR_MON_STEP_Pos   18U
 
#define CoreDebug_DEMCR_MON_STEP_Msk   (1UL << CoreDebug_DEMCR_MON_STEP_Pos)
 
#define CoreDebug_DEMCR_MON_PEND_Pos   17U
 
#define CoreDebug_DEMCR_MON_PEND_Msk   (1UL << CoreDebug_DEMCR_MON_PEND_Pos)
 
#define CoreDebug_DEMCR_MON_EN_Pos   16U
 
#define CoreDebug_DEMCR_MON_EN_Msk   (1UL << CoreDebug_DEMCR_MON_EN_Pos)
 
#define CoreDebug_DEMCR_VC_HARDERR_Pos   10U
 
#define CoreDebug_DEMCR_VC_HARDERR_Msk   (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
 
#define CoreDebug_DEMCR_VC_INTERR_Pos   9U
 
#define CoreDebug_DEMCR_VC_INTERR_Msk   (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)
 
#define CoreDebug_DEMCR_VC_BUSERR_Pos   8U
 
#define CoreDebug_DEMCR_VC_BUSERR_Msk   (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)
 
#define CoreDebug_DEMCR_VC_STATERR_Pos   7U
 
#define CoreDebug_DEMCR_VC_STATERR_Msk   (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)
 
#define CoreDebug_DEMCR_VC_CHKERR_Pos   6U
 
#define CoreDebug_DEMCR_VC_CHKERR_Msk   (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)
 
#define CoreDebug_DEMCR_VC_NOCPERR_Pos   5U
 
#define CoreDebug_DEMCR_VC_NOCPERR_Msk   (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)
 
#define CoreDebug_DEMCR_VC_MMERR_Pos   4U
 
#define CoreDebug_DEMCR_VC_MMERR_Msk   (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)
 
#define CoreDebug_DEMCR_VC_CORERESET_Pos   0U
 
#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)
 
#define _VAL2FLD(field, value)
 Mask and shift a bit field value for use in a register bit range.
 
#define _FLD2VAL(field, value)
 Mask and shift a register value to extract a bit filed value.
 
#define SCS_BASE   (0xE000E000UL)
 
#define ITM_BASE   (0xE0000000UL)
 
#define DWT_BASE   (0xE0001000UL)
 
#define TPI_BASE   (0xE0040000UL)
 
#define CoreDebug_BASE   (0xE000EDF0UL)
 
#define SysTick_BASE   (SCS_BASE + 0x0010UL)
 
#define NVIC_BASE   (SCS_BASE + 0x0100UL)
 
#define SCB_BASE   (SCS_BASE + 0x0D00UL)
 
#define SCnSCB   ((SCnSCB_Type *) SCS_BASE )
 
#define SCB   ((SCB_Type *) SCB_BASE )
 
#define SysTick   ((SysTick_Type *) SysTick_BASE )
 
#define NVIC   ((NVIC_Type *) NVIC_BASE )
 
#define ITM   ((ITM_Type *) ITM_BASE )
 
#define DWT   ((DWT_Type *) DWT_BASE )
 
#define TPI   ((TPI_Type *) TPI_BASE )
 
#define CoreDebug   ((CoreDebug_Type *) CoreDebug_BASE)
 
#define MPU_BASE   (SCS_BASE + 0x0D90UL)
 
#define MPU   ((MPU_Type *) MPU_BASE )
 
#define NVIC_SetPriorityGrouping   __NVIC_SetPriorityGrouping
 
#define NVIC_GetPriorityGrouping   __NVIC_GetPriorityGrouping
 
#define NVIC_EnableIRQ   __NVIC_EnableIRQ
 
#define NVIC_GetEnableIRQ   __NVIC_GetEnableIRQ
 
#define NVIC_DisableIRQ   __NVIC_DisableIRQ
 
#define NVIC_GetPendingIRQ   __NVIC_GetPendingIRQ
 
#define NVIC_SetPendingIRQ   __NVIC_SetPendingIRQ
 
#define NVIC_ClearPendingIRQ   __NVIC_ClearPendingIRQ
 
#define NVIC_GetActive   __NVIC_GetActive
 
#define NVIC_SetPriority   __NVIC_SetPriority
 
#define NVIC_GetPriority   __NVIC_GetPriority
 
#define NVIC_SystemReset   __NVIC_SystemReset
 
#define NVIC_SetVector   __NVIC_SetVector
 
#define NVIC_GetVector   __NVIC_GetVector
 
#define NVIC_USER_IRQ_OFFSET   16
 
#define EXC_RETURN_HANDLER   (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
 
#define EXC_RETURN_THREAD_MSP   (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
 
#define EXC_RETURN_THREAD_PSP   (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
 
#define ITM_RXBUFFER_EMPTY   ((int32_t)0x5AA55AA5U)
 
#define NVIC_STIR_INTID_Pos   0U
 
#define NVIC_STIR_INTID_Msk   (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_AIRCR_VECTRESET_Pos   0U
 
#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_CCR_NONBASETHRDENA_Pos   0U
 
#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCnSCB_ICTR_INTLINESNUM_Pos   0U
 
#define SCnSCB_ICTR_INTLINESNUM_Msk   (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)
 
#define SysTick_CTRL_COUNTFLAG_Pos   16U
 
#define SysTick_CTRL_COUNTFLAG_Msk   (1UL << SysTick_CTRL_COUNTFLAG_Pos)
 
#define SysTick_CTRL_CLKSOURCE_Pos   2U
 
#define SysTick_CTRL_CLKSOURCE_Msk   (1UL << SysTick_CTRL_CLKSOURCE_Pos)
 
#define SysTick_CTRL_TICKINT_Pos   1U
 
#define SysTick_CTRL_TICKINT_Msk   (1UL << SysTick_CTRL_TICKINT_Pos)
 
#define SysTick_CTRL_ENABLE_Pos   0U
 
#define SysTick_CTRL_ENABLE_Msk   (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)
 
#define SysTick_LOAD_RELOAD_Pos   0U
 
#define SysTick_LOAD_RELOAD_Msk   (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)
 
#define SysTick_VAL_CURRENT_Pos   0U
 
#define SysTick_VAL_CURRENT_Msk   (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)
 
#define SysTick_CALIB_NOREF_Pos   31U
 
#define SysTick_CALIB_NOREF_Msk   (1UL << SysTick_CALIB_NOREF_Pos)
 
#define SysTick_CALIB_SKEW_Pos   30U
 
#define SysTick_CALIB_SKEW_Msk   (1UL << SysTick_CALIB_SKEW_Pos)
 
#define SysTick_CALIB_TENMS_Pos   0U
 
#define SysTick_CALIB_TENMS_Msk   (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)
 
#define ITM_TPR_PRIVMASK_Pos   0U
 
#define ITM_TPR_PRIVMASK_Msk   (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
 
#define ITM_TCR_BUSY_Pos   23U
 
#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)
 
#define ITM_TCR_TraceBusID_Pos   16U
 
#define ITM_TCR_TraceBusID_Msk   (0x7FUL << ITM_TCR_TraceBusID_Pos)
 
#define ITM_TCR_GTSFREQ_Pos   10U
 
#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)
 
#define ITM_TCR_TSPrescale_Pos   8U
 
#define ITM_TCR_TSPrescale_Msk   (3UL << ITM_TCR_TSPrescale_Pos)
 
#define ITM_TCR_SWOENA_Pos   4U
 
#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)
 
#define ITM_TCR_DWTENA_Pos   3U
 
#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)
 
#define ITM_TCR_SYNCENA_Pos   2U
 
#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)
 
#define ITM_TCR_TSENA_Pos   1U
 
#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)
 
#define ITM_TCR_ITMENA_Pos   0U
 
#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)
 
#define ITM_IWR_ATVALIDM_Pos   0U
 
#define ITM_IWR_ATVALIDM_Msk   (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)
 
#define ITM_IRR_ATREADYM_Pos   0U
 
#define ITM_IRR_ATREADYM_Msk   (1UL /*<< ITM_IRR_ATREADYM_Pos*/)
 
#define ITM_IMCR_INTEGRATION_Pos   0U
 
#define ITM_IMCR_INTEGRATION_Msk   (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)
 
#define ITM_LSR_ByteAcc_Pos   2U
 
#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)
 
#define ITM_LSR_Access_Pos   1U
 
#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)
 
#define ITM_LSR_Present_Pos   0U
 
#define ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)
 
#define DWT_CTRL_NUMCOMP_Pos   28U
 
#define DWT_CTRL_NUMCOMP_Msk   (0xFUL << DWT_CTRL_NUMCOMP_Pos)
 
#define DWT_CTRL_NOTRCPKT_Pos   27U
 
#define DWT_CTRL_NOTRCPKT_Msk   (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
 
#define DWT_CTRL_NOEXTTRIG_Pos   26U
 
#define DWT_CTRL_NOEXTTRIG_Msk   (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
 
#define DWT_CTRL_NOCYCCNT_Pos   25U
 
#define DWT_CTRL_NOCYCCNT_Msk   (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
 
#define DWT_CTRL_NOPRFCNT_Pos   24U
 
#define DWT_CTRL_NOPRFCNT_Msk   (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
 
#define DWT_CTRL_CYCEVTENA_Pos   22U
 
#define DWT_CTRL_CYCEVTENA_Msk   (0x1UL << DWT_CTRL_CYCEVTENA_Pos)
 
#define DWT_CTRL_FOLDEVTENA_Pos   21U
 
#define DWT_CTRL_FOLDEVTENA_Msk   (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)
 
#define DWT_CTRL_LSUEVTENA_Pos   20U
 
#define DWT_CTRL_LSUEVTENA_Msk   (0x1UL << DWT_CTRL_LSUEVTENA_Pos)
 
#define DWT_CTRL_SLEEPEVTENA_Pos   19U
 
#define DWT_CTRL_SLEEPEVTENA_Msk   (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)
 
#define DWT_CTRL_EXCEVTENA_Pos   18U
 
#define DWT_CTRL_EXCEVTENA_Msk   (0x1UL << DWT_CTRL_EXCEVTENA_Pos)
 
#define DWT_CTRL_CPIEVTENA_Pos   17U
 
#define DWT_CTRL_CPIEVTENA_Msk   (0x1UL << DWT_CTRL_CPIEVTENA_Pos)
 
#define DWT_CTRL_EXCTRCENA_Pos   16U
 
#define DWT_CTRL_EXCTRCENA_Msk   (0x1UL << DWT_CTRL_EXCTRCENA_Pos)
 
#define DWT_CTRL_PCSAMPLENA_Pos   12U
 
#define DWT_CTRL_PCSAMPLENA_Msk   (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)
 
#define DWT_CTRL_SYNCTAP_Pos   10U
 
#define DWT_CTRL_SYNCTAP_Msk   (0x3UL << DWT_CTRL_SYNCTAP_Pos)
 
#define DWT_CTRL_CYCTAP_Pos   9U
 
#define DWT_CTRL_CYCTAP_Msk   (0x1UL << DWT_CTRL_CYCTAP_Pos)
 
#define DWT_CTRL_POSTINIT_Pos   5U
 
#define DWT_CTRL_POSTINIT_Msk   (0xFUL << DWT_CTRL_POSTINIT_Pos)
 
#define DWT_CTRL_POSTPRESET_Pos   1U
 
#define DWT_CTRL_POSTPRESET_Msk   (0xFUL << DWT_CTRL_POSTPRESET_Pos)
 
#define DWT_CTRL_CYCCNTENA_Pos   0U
 
#define DWT_CTRL_CYCCNTENA_Msk   (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)
 
#define DWT_CPICNT_CPICNT_Pos   0U
 
#define DWT_CPICNT_CPICNT_Msk   (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)
 
#define DWT_EXCCNT_EXCCNT_Pos   0U
 
#define DWT_EXCCNT_EXCCNT_Msk   (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)
 
#define DWT_SLEEPCNT_SLEEPCNT_Pos   0U
 
#define DWT_SLEEPCNT_SLEEPCNT_Msk   (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)
 
#define DWT_LSUCNT_LSUCNT_Pos   0U
 
#define DWT_LSUCNT_LSUCNT_Msk   (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)
 
#define DWT_FOLDCNT_FOLDCNT_Pos   0U
 
#define DWT_FOLDCNT_FOLDCNT_Msk   (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)
 
#define DWT_MASK_MASK_Pos   0U
 
#define DWT_MASK_MASK_Msk   (0x1FUL /*<< DWT_MASK_MASK_Pos*/)
 
#define DWT_FUNCTION_MATCHED_Pos   24U
 
#define DWT_FUNCTION_MATCHED_Msk   (0x1UL << DWT_FUNCTION_MATCHED_Pos)
 
#define DWT_FUNCTION_DATAVADDR1_Pos   16U
 
#define DWT_FUNCTION_DATAVADDR1_Msk   (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)
 
#define DWT_FUNCTION_DATAVADDR0_Pos   12U
 
#define DWT_FUNCTION_DATAVADDR0_Msk   (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)
 
#define DWT_FUNCTION_DATAVSIZE_Pos   10U
 
#define DWT_FUNCTION_DATAVSIZE_Msk   (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
 
#define DWT_FUNCTION_LNK1ENA_Pos   9U
 
#define DWT_FUNCTION_LNK1ENA_Msk   (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)
 
#define DWT_FUNCTION_DATAVMATCH_Pos   8U
 
#define DWT_FUNCTION_DATAVMATCH_Msk   (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)
 
#define DWT_FUNCTION_CYCMATCH_Pos   7U
 
#define DWT_FUNCTION_CYCMATCH_Msk   (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)
 
#define DWT_FUNCTION_EMITRANGE_Pos   5U
 
#define DWT_FUNCTION_EMITRANGE_Msk   (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)
 
#define DWT_FUNCTION_FUNCTION_Pos   0U
 
#define DWT_FUNCTION_FUNCTION_Msk   (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)
 
#define TPI_ACPR_PRESCALER_Pos   0U
 
#define TPI_ACPR_PRESCALER_Msk   (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)
 
#define TPI_SPPR_TXMODE_Pos   0U
 
#define TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
 
#define TPI_FFSR_FtNonStop_Pos   3U
 
#define TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)
 
#define TPI_FFSR_TCPresent_Pos   2U
 
#define TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)
 
#define TPI_FFSR_FtStopped_Pos   1U
 
#define TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)
 
#define TPI_FFSR_FlInProg_Pos   0U
 
#define TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
 
#define TPI_FFCR_TrigIn_Pos   8U
 
#define TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)
 
#define TPI_FFCR_EnFCont_Pos   1U
 
#define TPI_FFCR_EnFCont_Msk   (0x1UL << TPI_FFCR_EnFCont_Pos)
 
#define TPI_TRIGGER_TRIGGER_Pos   0U
 
#define TPI_TRIGGER_TRIGGER_Msk   (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)
 
#define TPI_FIFO0_ITM_ATVALID_Pos   29U
 
#define TPI_FIFO0_ITM_ATVALID_Msk   (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)
 
#define TPI_FIFO0_ITM_bytecount_Pos   27U
 
#define TPI_FIFO0_ITM_bytecount_Msk   (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)
 
#define TPI_FIFO0_ETM_ATVALID_Pos   26U
 
#define TPI_FIFO0_ETM_ATVALID_Msk   (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)
 
#define TPI_FIFO0_ETM_bytecount_Pos   24U
 
#define TPI_FIFO0_ETM_bytecount_Msk   (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)
 
#define TPI_FIFO0_ETM2_Pos   16U
 
#define TPI_FIFO0_ETM2_Msk   (0xFFUL << TPI_FIFO0_ETM2_Pos)
 
#define TPI_FIFO0_ETM1_Pos   8U
 
#define TPI_FIFO0_ETM1_Msk   (0xFFUL << TPI_FIFO0_ETM1_Pos)
 
#define TPI_FIFO0_ETM0_Pos   0U
 
#define TPI_FIFO0_ETM0_Msk   (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)
 
#define TPI_ITATBCTR2_ATREADY2_Pos   0U
 
#define TPI_ITATBCTR2_ATREADY2_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)
 
#define TPI_ITATBCTR2_ATREADY1_Pos   0U
 
#define TPI_ITATBCTR2_ATREADY1_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)
 
#define TPI_FIFO1_ITM_ATVALID_Pos   29U
 
#define TPI_FIFO1_ITM_ATVALID_Msk   (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)
 
#define TPI_FIFO1_ITM_bytecount_Pos   27U
 
#define TPI_FIFO1_ITM_bytecount_Msk   (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)
 
#define TPI_FIFO1_ETM_ATVALID_Pos   26U
 
#define TPI_FIFO1_ETM_ATVALID_Msk   (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)
 
#define TPI_FIFO1_ETM_bytecount_Pos   24U
 
#define TPI_FIFO1_ETM_bytecount_Msk   (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)
 
#define TPI_FIFO1_ITM2_Pos   16U
 
#define TPI_FIFO1_ITM2_Msk   (0xFFUL << TPI_FIFO1_ITM2_Pos)
 
#define TPI_FIFO1_ITM1_Pos   8U
 
#define TPI_FIFO1_ITM1_Msk   (0xFFUL << TPI_FIFO1_ITM1_Pos)
 
#define TPI_FIFO1_ITM0_Pos   0U
 
#define TPI_FIFO1_ITM0_Msk   (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)
 
#define TPI_ITATBCTR0_ATREADY2_Pos   0U
 
#define TPI_ITATBCTR0_ATREADY2_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)
 
#define TPI_ITATBCTR0_ATREADY1_Pos   0U
 
#define TPI_ITATBCTR0_ATREADY1_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)
 
#define TPI_ITCTRL_Mode_Pos   0U
 
#define TPI_ITCTRL_Mode_Msk   (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)
 
#define TPI_DEVID_NRZVALID_Pos   11U
 
#define TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)
 
#define TPI_DEVID_MANCVALID_Pos   10U
 
#define TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)
 
#define TPI_DEVID_PTINVALID_Pos   9U
 
#define TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)
 
#define TPI_DEVID_MinBufSz_Pos   6U
 
#define TPI_DEVID_MinBufSz_Msk   (0x7UL << TPI_DEVID_MinBufSz_Pos)
 
#define TPI_DEVID_AsynClkIn_Pos   5U
 
#define TPI_DEVID_AsynClkIn_Msk   (0x1UL << TPI_DEVID_AsynClkIn_Pos)
 
#define TPI_DEVID_NrTraceInput_Pos   0U
 
#define TPI_DEVID_NrTraceInput_Msk   (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)
 
#define TPI_DEVTYPE_SubType_Pos   4U
 
#define TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
 
#define TPI_DEVTYPE_MajorType_Pos   0U
 
#define TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)
 
#define MPU_TYPE_IREGION_Pos   16U
 
#define MPU_TYPE_IREGION_Msk   (0xFFUL << MPU_TYPE_IREGION_Pos)
 
#define MPU_TYPE_DREGION_Pos   8U
 
#define MPU_TYPE_DREGION_Msk   (0xFFUL << MPU_TYPE_DREGION_Pos)
 
#define MPU_TYPE_SEPARATE_Pos   0U
 
#define MPU_TYPE_SEPARATE_Msk   (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)
 
#define MPU_CTRL_PRIVDEFENA_Pos   2U
 
#define MPU_CTRL_PRIVDEFENA_Msk   (1UL << MPU_CTRL_PRIVDEFENA_Pos)
 
#define MPU_CTRL_HFNMIENA_Pos   1U
 
#define MPU_CTRL_HFNMIENA_Msk   (1UL << MPU_CTRL_HFNMIENA_Pos)
 
#define MPU_CTRL_ENABLE_Pos   0U
 
#define MPU_CTRL_ENABLE_Msk   (1UL /*<< MPU_CTRL_ENABLE_Pos*/)
 
#define MPU_RNR_REGION_Pos   0U
 
#define MPU_RNR_REGION_Msk   (0xFFUL /*<< MPU_RNR_REGION_Pos*/)
 
#define MPU_RBAR_ADDR_Pos   5U
 
#define MPU_RBAR_ADDR_Msk   (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)
 
#define MPU_RBAR_VALID_Pos   4U
 
#define MPU_RBAR_VALID_Msk   (1UL << MPU_RBAR_VALID_Pos)
 
#define MPU_RBAR_REGION_Pos   0U
 
#define MPU_RBAR_REGION_Msk   (0xFUL /*<< MPU_RBAR_REGION_Pos*/)
 
#define MPU_RASR_ATTRS_Pos   16U
 
#define MPU_RASR_ATTRS_Msk   (0xFFFFUL << MPU_RASR_ATTRS_Pos)
 
#define MPU_RASR_XN_Pos   28U
 
#define MPU_RASR_XN_Msk   (1UL << MPU_RASR_XN_Pos)
 
#define MPU_RASR_AP_Pos   24U
 
#define MPU_RASR_AP_Msk   (0x7UL << MPU_RASR_AP_Pos)
 
#define MPU_RASR_TEX_Pos   19U
 
#define MPU_RASR_TEX_Msk   (0x7UL << MPU_RASR_TEX_Pos)
 
#define MPU_RASR_S_Pos   18U
 
#define MPU_RASR_S_Msk   (1UL << MPU_RASR_S_Pos)
 
#define MPU_RASR_C_Pos   17U
 
#define MPU_RASR_C_Msk   (1UL << MPU_RASR_C_Pos)
 
#define MPU_RASR_B_Pos   16U
 
#define MPU_RASR_B_Msk   (1UL << MPU_RASR_B_Pos)
 
#define MPU_RASR_SRD_Pos   8U
 
#define MPU_RASR_SRD_Msk   (0xFFUL << MPU_RASR_SRD_Pos)
 
#define MPU_RASR_SIZE_Pos   1U
 
#define MPU_RASR_SIZE_Msk   (0x1FUL << MPU_RASR_SIZE_Pos)
 
#define MPU_RASR_ENABLE_Pos   0U
 
#define MPU_RASR_ENABLE_Msk   (1UL /*<< MPU_RASR_ENABLE_Pos*/)
 
#define CoreDebug_DHCSR_DBGKEY_Pos   16U
 
#define CoreDebug_DHCSR_DBGKEY_Msk   (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
 
#define CoreDebug_DHCSR_S_RESET_ST_Pos   25U
 
#define CoreDebug_DHCSR_S_RESET_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
 
#define CoreDebug_DHCSR_S_RETIRE_ST_Pos   24U
 
#define CoreDebug_DHCSR_S_RETIRE_ST_Msk   (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
 
#define CoreDebug_DHCSR_S_LOCKUP_Pos   19U
 
#define CoreDebug_DHCSR_S_LOCKUP_Msk   (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
 
#define CoreDebug_DHCSR_S_SLEEP_Pos   18U
 
#define CoreDebug_DHCSR_S_SLEEP_Msk   (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
 
#define CoreDebug_DHCSR_S_HALT_Pos   17U
 
#define CoreDebug_DHCSR_S_HALT_Msk   (1UL << CoreDebug_DHCSR_S_HALT_Pos)
 
#define CoreDebug_DHCSR_S_REGRDY_Pos   16U
 
#define CoreDebug_DHCSR_S_REGRDY_Msk   (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
 
#define CoreDebug_DHCSR_C_SNAPSTALL_Pos   5U
 
#define CoreDebug_DHCSR_C_SNAPSTALL_Msk   (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)
 
#define CoreDebug_DHCSR_C_MASKINTS_Pos   3U
 
#define CoreDebug_DHCSR_C_MASKINTS_Msk   (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
 
#define CoreDebug_DHCSR_C_STEP_Pos   2U
 
#define CoreDebug_DHCSR_C_STEP_Msk   (1UL << CoreDebug_DHCSR_C_STEP_Pos)
 
#define CoreDebug_DHCSR_C_HALT_Pos   1U
 
#define CoreDebug_DHCSR_C_HALT_Msk   (1UL << CoreDebug_DHCSR_C_HALT_Pos)
 
#define CoreDebug_DHCSR_C_DEBUGEN_Pos   0U
 
#define CoreDebug_DHCSR_C_DEBUGEN_Msk   (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)
 
#define CoreDebug_DCRSR_REGWnR_Pos   16U
 
#define CoreDebug_DCRSR_REGWnR_Msk   (1UL << CoreDebug_DCRSR_REGWnR_Pos)
 
#define CoreDebug_DCRSR_REGSEL_Pos   0U
 
#define CoreDebug_DCRSR_REGSEL_Msk   (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)
 
#define CoreDebug_DEMCR_TRCENA_Pos   24U
 
#define CoreDebug_DEMCR_TRCENA_Msk   (1UL << CoreDebug_DEMCR_TRCENA_Pos)
 
#define CoreDebug_DEMCR_MON_REQ_Pos   19U
 
#define CoreDebug_DEMCR_MON_REQ_Msk   (1UL << CoreDebug_DEMCR_MON_REQ_Pos)
 
#define CoreDebug_DEMCR_MON_STEP_Pos   18U
 
#define CoreDebug_DEMCR_MON_STEP_Msk   (1UL << CoreDebug_DEMCR_MON_STEP_Pos)
 
#define CoreDebug_DEMCR_MON_PEND_Pos   17U
 
#define CoreDebug_DEMCR_MON_PEND_Msk   (1UL << CoreDebug_DEMCR_MON_PEND_Pos)
 
#define CoreDebug_DEMCR_MON_EN_Pos   16U
 
#define CoreDebug_DEMCR_MON_EN_Msk   (1UL << CoreDebug_DEMCR_MON_EN_Pos)
 
#define CoreDebug_DEMCR_VC_HARDERR_Pos   10U
 
#define CoreDebug_DEMCR_VC_HARDERR_Msk   (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
 
#define CoreDebug_DEMCR_VC_INTERR_Pos   9U
 
#define CoreDebug_DEMCR_VC_INTERR_Msk   (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)
 
#define CoreDebug_DEMCR_VC_BUSERR_Pos   8U
 
#define CoreDebug_DEMCR_VC_BUSERR_Msk   (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)
 
#define CoreDebug_DEMCR_VC_STATERR_Pos   7U
 
#define CoreDebug_DEMCR_VC_STATERR_Msk   (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)
 
#define CoreDebug_DEMCR_VC_CHKERR_Pos   6U
 
#define CoreDebug_DEMCR_VC_CHKERR_Msk   (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)
 
#define CoreDebug_DEMCR_VC_NOCPERR_Pos   5U
 
#define CoreDebug_DEMCR_VC_NOCPERR_Msk   (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)
 
#define CoreDebug_DEMCR_VC_MMERR_Pos   4U
 
#define CoreDebug_DEMCR_VC_MMERR_Msk   (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)
 
#define CoreDebug_DEMCR_VC_CORERESET_Pos   0U
 
#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)
 
#define _VAL2FLD(field, value)
 Mask and shift a bit field value for use in a register bit range.
 
#define _FLD2VAL(field, value)
 Mask and shift a register value to extract a bit filed value.
 
#define SCS_BASE   (0xE000E000UL)
 
#define ITM_BASE   (0xE0000000UL)
 
#define DWT_BASE   (0xE0001000UL)
 
#define TPI_BASE   (0xE0040000UL)
 
#define CoreDebug_BASE   (0xE000EDF0UL)
 
#define SysTick_BASE   (SCS_BASE + 0x0010UL)
 
#define NVIC_BASE   (SCS_BASE + 0x0100UL)
 
#define SCB_BASE   (SCS_BASE + 0x0D00UL)
 
#define SCnSCB   ((SCnSCB_Type *) SCS_BASE )
 
#define SCB   ((SCB_Type *) SCB_BASE )
 
#define SysTick   ((SysTick_Type *) SysTick_BASE )
 
#define NVIC   ((NVIC_Type *) NVIC_BASE )
 
#define ITM   ((ITM_Type *) ITM_BASE )
 
#define DWT   ((DWT_Type *) DWT_BASE )
 
#define TPI   ((TPI_Type *) TPI_BASE )
 
#define CoreDebug   ((CoreDebug_Type *) CoreDebug_BASE)
 
#define MPU_BASE   (SCS_BASE + 0x0D90UL)
 
#define MPU   ((MPU_Type *) MPU_BASE )
 
#define NVIC_SetPriorityGrouping   __NVIC_SetPriorityGrouping
 
#define NVIC_GetPriorityGrouping   __NVIC_GetPriorityGrouping
 
#define NVIC_EnableIRQ   __NVIC_EnableIRQ
 
#define NVIC_GetEnableIRQ   __NVIC_GetEnableIRQ
 
#define NVIC_DisableIRQ   __NVIC_DisableIRQ
 
#define NVIC_GetPendingIRQ   __NVIC_GetPendingIRQ
 
#define NVIC_SetPendingIRQ   __NVIC_SetPendingIRQ
 
#define NVIC_ClearPendingIRQ   __NVIC_ClearPendingIRQ
 
#define NVIC_GetActive   __NVIC_GetActive
 
#define NVIC_SetPriority   __NVIC_SetPriority
 
#define NVIC_GetPriority   __NVIC_GetPriority
 
#define NVIC_SystemReset   __NVIC_SystemReset
 
#define NVIC_SetVector   __NVIC_SetVector
 
#define NVIC_GetVector   __NVIC_GetVector
 
#define NVIC_USER_IRQ_OFFSET   16
 
#define EXC_RETURN_HANDLER   (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
 
#define EXC_RETURN_THREAD_MSP   (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
 
#define EXC_RETURN_THREAD_PSP   (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
 
#define ITM_RXBUFFER_EMPTY   ((int32_t)0x5AA55AA5U)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SysTick_CTRL_COUNTFLAG_Pos   16U
 
#define SysTick_CTRL_COUNTFLAG_Msk   (1UL << SysTick_CTRL_COUNTFLAG_Pos)
 
#define SysTick_CTRL_CLKSOURCE_Pos   2U
 
#define SysTick_CTRL_CLKSOURCE_Msk   (1UL << SysTick_CTRL_CLKSOURCE_Pos)
 
#define SysTick_CTRL_TICKINT_Pos   1U
 
#define SysTick_CTRL_TICKINT_Msk   (1UL << SysTick_CTRL_TICKINT_Pos)
 
#define SysTick_CTRL_ENABLE_Pos   0U
 
#define SysTick_CTRL_ENABLE_Msk   (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)
 
#define SysTick_LOAD_RELOAD_Pos   0U
 
#define SysTick_LOAD_RELOAD_Msk   (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)
 
#define SysTick_VAL_CURRENT_Pos   0U
 
#define SysTick_VAL_CURRENT_Msk   (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)
 
#define SysTick_CALIB_NOREF_Pos   31U
 
#define SysTick_CALIB_NOREF_Msk   (1UL << SysTick_CALIB_NOREF_Pos)
 
#define SysTick_CALIB_SKEW_Pos   30U
 
#define SysTick_CALIB_SKEW_Msk   (1UL << SysTick_CALIB_SKEW_Pos)
 
#define SysTick_CALIB_TENMS_Pos   0U
 
#define SysTick_CALIB_TENMS_Msk   (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)
 
#define MPU_TYPE_IREGION_Pos   16U
 
#define MPU_TYPE_IREGION_Msk   (0xFFUL << MPU_TYPE_IREGION_Pos)
 
#define MPU_TYPE_DREGION_Pos   8U
 
#define MPU_TYPE_DREGION_Msk   (0xFFUL << MPU_TYPE_DREGION_Pos)
 
#define MPU_TYPE_SEPARATE_Pos   0U
 
#define MPU_TYPE_SEPARATE_Msk   (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)
 
#define MPU_CTRL_PRIVDEFENA_Pos   2U
 
#define MPU_CTRL_PRIVDEFENA_Msk   (1UL << MPU_CTRL_PRIVDEFENA_Pos)
 
#define MPU_CTRL_HFNMIENA_Pos   1U
 
#define MPU_CTRL_HFNMIENA_Msk   (1UL << MPU_CTRL_HFNMIENA_Pos)
 
#define MPU_CTRL_ENABLE_Pos   0U
 
#define MPU_CTRL_ENABLE_Msk   (1UL /*<< MPU_CTRL_ENABLE_Pos*/)
 
#define MPU_RNR_REGION_Pos   0U
 
#define MPU_RNR_REGION_Msk   (0xFFUL /*<< MPU_RNR_REGION_Pos*/)
 
#define MPU_RBAR_ADDR_Pos   8U
 
#define MPU_RBAR_ADDR_Msk   (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)
 
#define MPU_RBAR_VALID_Pos   4U
 
#define MPU_RBAR_VALID_Msk   (1UL << MPU_RBAR_VALID_Pos)
 
#define MPU_RBAR_REGION_Pos   0U
 
#define MPU_RBAR_REGION_Msk   (0xFUL /*<< MPU_RBAR_REGION_Pos*/)
 
#define MPU_RASR_ATTRS_Pos   16U
 
#define MPU_RASR_ATTRS_Msk   (0xFFFFUL << MPU_RASR_ATTRS_Pos)
 
#define MPU_RASR_XN_Pos   28U
 
#define MPU_RASR_XN_Msk   (1UL << MPU_RASR_XN_Pos)
 
#define MPU_RASR_AP_Pos   24U
 
#define MPU_RASR_AP_Msk   (0x7UL << MPU_RASR_AP_Pos)
 
#define MPU_RASR_TEX_Pos   19U
 
#define MPU_RASR_TEX_Msk   (0x7UL << MPU_RASR_TEX_Pos)
 
#define MPU_RASR_S_Pos   18U
 
#define MPU_RASR_S_Msk   (1UL << MPU_RASR_S_Pos)
 
#define MPU_RASR_C_Pos   17U
 
#define MPU_RASR_C_Msk   (1UL << MPU_RASR_C_Pos)
 
#define MPU_RASR_B_Pos   16U
 
#define MPU_RASR_B_Msk   (1UL << MPU_RASR_B_Pos)
 
#define MPU_RASR_SRD_Pos   8U
 
#define MPU_RASR_SRD_Msk   (0xFFUL << MPU_RASR_SRD_Pos)
 
#define MPU_RASR_SIZE_Pos   1U
 
#define MPU_RASR_SIZE_Msk   (0x1FUL << MPU_RASR_SIZE_Pos)
 
#define MPU_RASR_ENABLE_Pos   0U
 
#define MPU_RASR_ENABLE_Msk   (1UL /*<< MPU_RASR_ENABLE_Pos*/)
 
#define _VAL2FLD(field, value)
 Mask and shift a bit field value for use in a register bit range.
 
#define _FLD2VAL(field, value)
 Mask and shift a register value to extract a bit filed value.
 
#define SCS_BASE   (0xE000E000UL)
 
#define SysTick_BASE   (SCS_BASE + 0x0010UL)
 
#define NVIC_BASE   (SCS_BASE + 0x0100UL)
 
#define SCB_BASE   (SCS_BASE + 0x0D00UL)
 
#define SCnSCB   ((SCnSCB_Type *) SCS_BASE )
 
#define SCB   ((SCB_Type *) SCB_BASE )
 
#define SysTick   ((SysTick_Type *) SysTick_BASE )
 
#define NVIC   ((NVIC_Type *) NVIC_BASE )
 
#define MPU_BASE   (SCS_BASE + 0x0D90UL)
 
#define MPU   ((MPU_Type *) MPU_BASE )
 
#define NVIC_EnableIRQ   __NVIC_EnableIRQ
 
#define NVIC_GetEnableIRQ   __NVIC_GetEnableIRQ
 
#define NVIC_DisableIRQ   __NVIC_DisableIRQ
 
#define NVIC_GetPendingIRQ   __NVIC_GetPendingIRQ
 
#define NVIC_SetPendingIRQ   __NVIC_SetPendingIRQ
 
#define NVIC_ClearPendingIRQ   __NVIC_ClearPendingIRQ
 
#define NVIC_SetPriority   __NVIC_SetPriority
 
#define NVIC_GetPriority   __NVIC_GetPriority
 
#define NVIC_SystemReset   __NVIC_SystemReset
 
#define NVIC_SetVector   __NVIC_SetVector
 
#define NVIC_GetVector   __NVIC_GetVector
 
#define NVIC_USER_IRQ_OFFSET   16
 
#define EXC_RETURN_HANDLER   (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
 
#define EXC_RETURN_THREAD_MSP   (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
 
#define EXC_RETURN_THREAD_PSP   (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
 
#define APSR_GE_Pos   16U
 
#define APSR_GE_Msk   (0xFUL << APSR_GE_Pos)
 
#define xPSR_GE_Pos   16U
 
#define xPSR_GE_Msk   (0xFUL << xPSR_GE_Pos)
 
#define CONTROL_FPCA_Pos   2U
 
#define CONTROL_FPCA_Msk   (1UL << CONTROL_FPCA_Pos)
 
#define APSR_GE_Pos   16U
 
#define APSR_GE_Msk   (0xFUL << APSR_GE_Pos)
 
#define xPSR_GE_Pos   16U
 
#define xPSR_GE_Msk   (0xFUL << xPSR_GE_Pos)
 
#define CONTROL_FPCA_Pos   2U
 
#define CONTROL_FPCA_Msk   (1UL << CONTROL_FPCA_Pos)
 
#define APSR_GE_Pos   16U
 
#define APSR_GE_Msk   (0xFUL << APSR_GE_Pos)
 
#define xPSR_GE_Pos   16U
 
#define xPSR_GE_Msk   (0xFUL << xPSR_GE_Pos)
 
#define CONTROL_FPCA_Pos   2U
 
#define CONTROL_FPCA_Msk   (1UL << CONTROL_FPCA_Pos)
 
#define APSR_GE_Pos   16U
 
#define APSR_GE_Msk   (0xFUL << APSR_GE_Pos)
 
#define xPSR_GE_Pos   16U
 
#define xPSR_GE_Msk   (0xFUL << xPSR_GE_Pos)
 
#define CONTROL_FPCA_Pos   2U
 
#define CONTROL_FPCA_Msk   (1UL << CONTROL_FPCA_Pos)
 
#define SCB_CCR_BP_Pos   18U
 
#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)
 
#define SCB_CCR_IC_Pos   17U
 
#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)
 
#define SCB_CCR_DC_Pos   16U
 
#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)
 
#define SCB_CFSR_MLSPERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 5U)
 
#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)
 
#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)
 
#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)
 
#define SCB_CLIDR_LOUU_Pos   27U
 
#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)
 
#define SCB_CLIDR_LOC_Pos   24U
 
#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)
 
#define SCB_CTR_FORMAT_Pos   29U
 
#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)
 
#define SCB_CTR_CWG_Pos   24U
 
#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)
 
#define SCB_CTR_ERG_Pos   20U
 
#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)
 
#define SCB_CTR_DMINLINE_Pos   16U
 
#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)
 
#define SCB_CTR_IMINLINE_Pos   0U
 
#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)
 
#define SCB_CCSIDR_WT_Pos   31U
 
#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)
 
#define SCB_CCSIDR_WB_Pos   30U
 
#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)
 
#define SCB_CCSIDR_RA_Pos   29U
 
#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)
 
#define SCB_CCSIDR_WA_Pos   28U
 
#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)
 
#define SCB_CCSIDR_NUMSETS_Pos   13U
 
#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
 
#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U
 
#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
 
#define SCB_CCSIDR_LINESIZE_Pos   0U
 
#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)
 
#define SCB_CSSELR_LEVEL_Pos   1U
 
#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)
 
#define SCB_CSSELR_IND_Pos   0U
 
#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)
 
#define SCB_STIR_INTID_Pos   0U
 
#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)
 
#define SCB_DCISW_WAY_Pos   30U
 
#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)
 
#define SCB_DCISW_SET_Pos   5U
 
#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)
 
#define SCB_DCCSW_WAY_Pos   30U
 
#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)
 
#define SCB_DCCSW_SET_Pos   5U
 
#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)
 
#define SCB_DCCISW_WAY_Pos   30U
 
#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)
 
#define SCB_DCCISW_SET_Pos   5U
 
#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)
 
#define SCB_ITCMCR_SZ_Pos   3U
 
#define SCB_ITCMCR_SZ_Msk   (0xFUL << SCB_ITCMCR_SZ_Pos)
 
#define SCB_ITCMCR_RETEN_Pos   2U
 
#define SCB_ITCMCR_RETEN_Msk   (1UL << SCB_ITCMCR_RETEN_Pos)
 
#define SCB_ITCMCR_RMW_Pos   1U
 
#define SCB_ITCMCR_RMW_Msk   (1UL << SCB_ITCMCR_RMW_Pos)
 
#define SCB_ITCMCR_EN_Pos   0U
 
#define SCB_ITCMCR_EN_Msk   (1UL /*<< SCB_ITCMCR_EN_Pos*/)
 
#define SCB_DTCMCR_SZ_Pos   3U
 
#define SCB_DTCMCR_SZ_Msk   (0xFUL << SCB_DTCMCR_SZ_Pos)
 
#define SCB_DTCMCR_RETEN_Pos   2U
 
#define SCB_DTCMCR_RETEN_Msk   (1UL << SCB_DTCMCR_RETEN_Pos)
 
#define SCB_DTCMCR_RMW_Pos   1U
 
#define SCB_DTCMCR_RMW_Msk   (1UL << SCB_DTCMCR_RMW_Pos)
 
#define SCB_DTCMCR_EN_Pos   0U
 
#define SCB_DTCMCR_EN_Msk   (1UL /*<< SCB_DTCMCR_EN_Pos*/)
 
#define SCB_AHBPCR_SZ_Pos   1U
 
#define SCB_AHBPCR_SZ_Msk   (7UL << SCB_AHBPCR_SZ_Pos)
 
#define SCB_AHBPCR_EN_Pos   0U
 
#define SCB_AHBPCR_EN_Msk   (1UL /*<< SCB_AHBPCR_EN_Pos*/)
 
#define SCB_CACR_FORCEWT_Pos   2U
 
#define SCB_CACR_FORCEWT_Msk   (1UL << SCB_CACR_FORCEWT_Pos)
 
#define SCB_CACR_ECCEN_Pos   1U
 
#define SCB_CACR_ECCEN_Msk   (1UL << SCB_CACR_ECCEN_Pos)
 
#define SCB_CACR_SIWT_Pos   0U
 
#define SCB_CACR_SIWT_Msk   (1UL /*<< SCB_CACR_SIWT_Pos*/)
 
#define SCB_AHBSCR_INITCOUNT_Pos   11U
 
#define SCB_AHBSCR_INITCOUNT_Msk   (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)
 
#define SCB_AHBSCR_TPRI_Pos   2U
 
#define SCB_AHBSCR_TPRI_Msk   (0x1FFUL << SCB_AHBPCR_TPRI_Pos)
 
#define SCB_AHBSCR_CTL_Pos   0U
 
#define SCB_AHBSCR_CTL_Msk   (3UL /*<< SCB_AHBPCR_CTL_Pos*/)
 
#define SCB_ABFSR_AXIMTYPE_Pos   8U
 
#define SCB_ABFSR_AXIMTYPE_Msk   (3UL << SCB_ABFSR_AXIMTYPE_Pos)
 
#define SCB_ABFSR_EPPB_Pos   4U
 
#define SCB_ABFSR_EPPB_Msk   (1UL << SCB_ABFSR_EPPB_Pos)
 
#define SCB_ABFSR_AXIM_Pos   3U
 
#define SCB_ABFSR_AXIM_Msk   (1UL << SCB_ABFSR_AXIM_Pos)
 
#define SCB_ABFSR_AHBP_Pos   2U
 
#define SCB_ABFSR_AHBP_Msk   (1UL << SCB_ABFSR_AHBP_Pos)
 
#define SCB_ABFSR_DTCM_Pos   1U
 
#define SCB_ABFSR_DTCM_Msk   (1UL << SCB_ABFSR_DTCM_Pos)
 
#define SCB_ABFSR_ITCM_Pos   0U
 
#define SCB_ABFSR_ITCM_Msk   (1UL /*<< SCB_ABFSR_ITCM_Pos*/)
 
#define MPU_TYPE_RALIASES   4U
 
#define FPU_FPCCR_ASPEN_Pos   31U
 
#define FPU_FPCCR_ASPEN_Msk   (1UL << FPU_FPCCR_ASPEN_Pos)
 
#define FPU_FPCCR_LSPEN_Pos   30U
 
#define FPU_FPCCR_LSPEN_Msk   (1UL << FPU_FPCCR_LSPEN_Pos)
 
#define FPU_FPCCR_MONRDY_Pos   8U
 
#define FPU_FPCCR_MONRDY_Msk   (1UL << FPU_FPCCR_MONRDY_Pos)
 
#define FPU_FPCCR_BFRDY_Pos   6U
 
#define FPU_FPCCR_BFRDY_Msk   (1UL << FPU_FPCCR_BFRDY_Pos)
 
#define FPU_FPCCR_MMRDY_Pos   5U
 
#define FPU_FPCCR_MMRDY_Msk   (1UL << FPU_FPCCR_MMRDY_Pos)
 
#define FPU_FPCCR_HFRDY_Pos   4U
 
#define FPU_FPCCR_HFRDY_Msk   (1UL << FPU_FPCCR_HFRDY_Pos)
 
#define FPU_FPCCR_THREAD_Pos   3U
 
#define FPU_FPCCR_THREAD_Msk   (1UL << FPU_FPCCR_THREAD_Pos)
 
#define FPU_FPCCR_USER_Pos   1U
 
#define FPU_FPCCR_USER_Msk   (1UL << FPU_FPCCR_USER_Pos)
 
#define FPU_FPCCR_LSPACT_Pos   0U
 
#define FPU_FPCCR_LSPACT_Msk   (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)
 
#define FPU_FPCAR_ADDRESS_Pos   3U
 
#define FPU_FPCAR_ADDRESS_Msk   (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
 
#define FPU_FPDSCR_AHP_Pos   26U
 
#define FPU_FPDSCR_AHP_Msk   (1UL << FPU_FPDSCR_AHP_Pos)
 
#define FPU_FPDSCR_DN_Pos   25U
 
#define FPU_FPDSCR_DN_Msk   (1UL << FPU_FPDSCR_DN_Pos)
 
#define FPU_FPDSCR_FZ_Pos   24U
 
#define FPU_FPDSCR_FZ_Msk   (1UL << FPU_FPDSCR_FZ_Pos)
 
#define FPU_FPDSCR_RMode_Pos   22U
 
#define FPU_FPDSCR_RMode_Msk   (3UL << FPU_FPDSCR_RMode_Pos)
 
#define FPU_MVFR0_FP_rounding_modes_Pos   28U
 
#define FPU_MVFR0_FP_rounding_modes_Msk   (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)
 
#define FPU_MVFR0_Short_vectors_Pos   24U
 
#define FPU_MVFR0_Short_vectors_Msk   (0xFUL << FPU_MVFR0_Short_vectors_Pos)
 
#define FPU_MVFR0_Square_root_Pos   20U
 
#define FPU_MVFR0_Square_root_Msk   (0xFUL << FPU_MVFR0_Square_root_Pos)
 
#define FPU_MVFR0_Divide_Pos   16U
 
#define FPU_MVFR0_Divide_Msk   (0xFUL << FPU_MVFR0_Divide_Pos)
 
#define FPU_MVFR0_FP_excep_trapping_Pos   12U
 
#define FPU_MVFR0_FP_excep_trapping_Msk   (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)
 
#define FPU_MVFR0_Double_precision_Pos   8U
 
#define FPU_MVFR0_Double_precision_Msk   (0xFUL << FPU_MVFR0_Double_precision_Pos)
 
#define FPU_MVFR0_Single_precision_Pos   4U
 
#define FPU_MVFR0_Single_precision_Msk   (0xFUL << FPU_MVFR0_Single_precision_Pos)
 
#define FPU_MVFR0_A_SIMD_registers_Pos   0U
 
#define FPU_MVFR0_A_SIMD_registers_Msk   (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)
 
#define FPU_MVFR1_FP_fused_MAC_Pos   28U
 
#define FPU_MVFR1_FP_fused_MAC_Msk   (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)
 
#define FPU_MVFR1_FP_HPFP_Pos   24U
 
#define FPU_MVFR1_FP_HPFP_Msk   (0xFUL << FPU_MVFR1_FP_HPFP_Pos)
 
#define FPU_MVFR1_D_NaN_mode_Pos   4U
 
#define FPU_MVFR1_D_NaN_mode_Msk   (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)
 
#define FPU_MVFR1_FtZ_mode_Pos   0U
 
#define FPU_MVFR1_FtZ_mode_Msk   (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)
 
#define FPU_BASE   (SCS_BASE + 0x0F30UL)
 
#define FPU   ((FPU_Type *) FPU_BASE )
 
#define SCB_CCR_BP_Pos   18U
 
#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)
 
#define SCB_CCR_IC_Pos   17U
 
#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)
 
#define SCB_CCR_DC_Pos   16U
 
#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)
 
#define SCB_CFSR_MLSPERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 5U)
 
#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)
 
#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)
 
#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)
 
#define SCB_CLIDR_LOUU_Pos   27U
 
#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)
 
#define SCB_CLIDR_LOC_Pos   24U
 
#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)
 
#define SCB_CTR_FORMAT_Pos   29U
 
#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)
 
#define SCB_CTR_CWG_Pos   24U
 
#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)
 
#define SCB_CTR_ERG_Pos   20U
 
#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)
 
#define SCB_CTR_DMINLINE_Pos   16U
 
#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)
 
#define SCB_CTR_IMINLINE_Pos   0U
 
#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)
 
#define SCB_CCSIDR_WT_Pos   31U
 
#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)
 
#define SCB_CCSIDR_WB_Pos   30U
 
#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)
 
#define SCB_CCSIDR_RA_Pos   29U
 
#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)
 
#define SCB_CCSIDR_WA_Pos   28U
 
#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)
 
#define SCB_CCSIDR_NUMSETS_Pos   13U
 
#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
 
#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U
 
#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
 
#define SCB_CCSIDR_LINESIZE_Pos   0U
 
#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)
 
#define SCB_CSSELR_LEVEL_Pos   1U
 
#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)
 
#define SCB_CSSELR_IND_Pos   0U
 
#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)
 
#define SCB_STIR_INTID_Pos   0U
 
#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)
 
#define SCB_DCISW_WAY_Pos   30U
 
#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)
 
#define SCB_DCISW_SET_Pos   5U
 
#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)
 
#define SCB_DCCSW_WAY_Pos   30U
 
#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)
 
#define SCB_DCCSW_SET_Pos   5U
 
#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)
 
#define SCB_DCCISW_WAY_Pos   30U
 
#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)
 
#define SCB_DCCISW_SET_Pos   5U
 
#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)
 
#define SCB_ITCMCR_SZ_Pos   3U
 
#define SCB_ITCMCR_SZ_Msk   (0xFUL << SCB_ITCMCR_SZ_Pos)
 
#define SCB_ITCMCR_RETEN_Pos   2U
 
#define SCB_ITCMCR_RETEN_Msk   (1UL << SCB_ITCMCR_RETEN_Pos)
 
#define SCB_ITCMCR_RMW_Pos   1U
 
#define SCB_ITCMCR_RMW_Msk   (1UL << SCB_ITCMCR_RMW_Pos)
 
#define SCB_ITCMCR_EN_Pos   0U
 
#define SCB_ITCMCR_EN_Msk   (1UL /*<< SCB_ITCMCR_EN_Pos*/)
 
#define SCB_DTCMCR_SZ_Pos   3U
 
#define SCB_DTCMCR_SZ_Msk   (0xFUL << SCB_DTCMCR_SZ_Pos)
 
#define SCB_DTCMCR_RETEN_Pos   2U
 
#define SCB_DTCMCR_RETEN_Msk   (1UL << SCB_DTCMCR_RETEN_Pos)
 
#define SCB_DTCMCR_RMW_Pos   1U
 
#define SCB_DTCMCR_RMW_Msk   (1UL << SCB_DTCMCR_RMW_Pos)
 
#define SCB_DTCMCR_EN_Pos   0U
 
#define SCB_DTCMCR_EN_Msk   (1UL /*<< SCB_DTCMCR_EN_Pos*/)
 
#define SCB_AHBPCR_SZ_Pos   1U
 
#define SCB_AHBPCR_SZ_Msk   (7UL << SCB_AHBPCR_SZ_Pos)
 
#define SCB_AHBPCR_EN_Pos   0U
 
#define SCB_AHBPCR_EN_Msk   (1UL /*<< SCB_AHBPCR_EN_Pos*/)
 
#define SCB_CACR_FORCEWT_Pos   2U
 
#define SCB_CACR_FORCEWT_Msk   (1UL << SCB_CACR_FORCEWT_Pos)
 
#define SCB_CACR_ECCEN_Pos   1U
 
#define SCB_CACR_ECCEN_Msk   (1UL << SCB_CACR_ECCEN_Pos)
 
#define SCB_CACR_SIWT_Pos   0U
 
#define SCB_CACR_SIWT_Msk   (1UL /*<< SCB_CACR_SIWT_Pos*/)
 
#define SCB_AHBSCR_INITCOUNT_Pos   11U
 
#define SCB_AHBSCR_INITCOUNT_Msk   (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)
 
#define SCB_AHBSCR_TPRI_Pos   2U
 
#define SCB_AHBSCR_TPRI_Msk   (0x1FFUL << SCB_AHBPCR_TPRI_Pos)
 
#define SCB_AHBSCR_CTL_Pos   0U
 
#define SCB_AHBSCR_CTL_Msk   (3UL /*<< SCB_AHBPCR_CTL_Pos*/)
 
#define SCB_ABFSR_AXIMTYPE_Pos   8U
 
#define SCB_ABFSR_AXIMTYPE_Msk   (3UL << SCB_ABFSR_AXIMTYPE_Pos)
 
#define SCB_ABFSR_EPPB_Pos   4U
 
#define SCB_ABFSR_EPPB_Msk   (1UL << SCB_ABFSR_EPPB_Pos)
 
#define SCB_ABFSR_AXIM_Pos   3U
 
#define SCB_ABFSR_AXIM_Msk   (1UL << SCB_ABFSR_AXIM_Pos)
 
#define SCB_ABFSR_AHBP_Pos   2U
 
#define SCB_ABFSR_AHBP_Msk   (1UL << SCB_ABFSR_AHBP_Pos)
 
#define SCB_ABFSR_DTCM_Pos   1U
 
#define SCB_ABFSR_DTCM_Msk   (1UL << SCB_ABFSR_DTCM_Pos)
 
#define SCB_ABFSR_ITCM_Pos   0U
 
#define SCB_ABFSR_ITCM_Msk   (1UL /*<< SCB_ABFSR_ITCM_Pos*/)
 
#define MPU_TYPE_RALIASES   4U
 
#define FPU_FPCCR_ASPEN_Pos   31U
 
#define FPU_FPCCR_ASPEN_Msk   (1UL << FPU_FPCCR_ASPEN_Pos)
 
#define FPU_FPCCR_LSPEN_Pos   30U
 
#define FPU_FPCCR_LSPEN_Msk   (1UL << FPU_FPCCR_LSPEN_Pos)
 
#define FPU_FPCCR_MONRDY_Pos   8U
 
#define FPU_FPCCR_MONRDY_Msk   (1UL << FPU_FPCCR_MONRDY_Pos)
 
#define FPU_FPCCR_BFRDY_Pos   6U
 
#define FPU_FPCCR_BFRDY_Msk   (1UL << FPU_FPCCR_BFRDY_Pos)
 
#define FPU_FPCCR_MMRDY_Pos   5U
 
#define FPU_FPCCR_MMRDY_Msk   (1UL << FPU_FPCCR_MMRDY_Pos)
 
#define FPU_FPCCR_HFRDY_Pos   4U
 
#define FPU_FPCCR_HFRDY_Msk   (1UL << FPU_FPCCR_HFRDY_Pos)
 
#define FPU_FPCCR_THREAD_Pos   3U
 
#define FPU_FPCCR_THREAD_Msk   (1UL << FPU_FPCCR_THREAD_Pos)
 
#define FPU_FPCCR_USER_Pos   1U
 
#define FPU_FPCCR_USER_Msk   (1UL << FPU_FPCCR_USER_Pos)
 
#define FPU_FPCCR_LSPACT_Pos   0U
 
#define FPU_FPCCR_LSPACT_Msk   (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)
 
#define FPU_FPCAR_ADDRESS_Pos   3U
 
#define FPU_FPCAR_ADDRESS_Msk   (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
 
#define FPU_FPDSCR_AHP_Pos   26U
 
#define FPU_FPDSCR_AHP_Msk   (1UL << FPU_FPDSCR_AHP_Pos)
 
#define FPU_FPDSCR_DN_Pos   25U
 
#define FPU_FPDSCR_DN_Msk   (1UL << FPU_FPDSCR_DN_Pos)
 
#define FPU_FPDSCR_FZ_Pos   24U
 
#define FPU_FPDSCR_FZ_Msk   (1UL << FPU_FPDSCR_FZ_Pos)
 
#define FPU_FPDSCR_RMode_Pos   22U
 
#define FPU_FPDSCR_RMode_Msk   (3UL << FPU_FPDSCR_RMode_Pos)
 
#define FPU_MVFR0_FP_rounding_modes_Pos   28U
 
#define FPU_MVFR0_FP_rounding_modes_Msk   (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)
 
#define FPU_MVFR0_Short_vectors_Pos   24U
 
#define FPU_MVFR0_Short_vectors_Msk   (0xFUL << FPU_MVFR0_Short_vectors_Pos)
 
#define FPU_MVFR0_Square_root_Pos   20U
 
#define FPU_MVFR0_Square_root_Msk   (0xFUL << FPU_MVFR0_Square_root_Pos)
 
#define FPU_MVFR0_Divide_Pos   16U
 
#define FPU_MVFR0_Divide_Msk   (0xFUL << FPU_MVFR0_Divide_Pos)
 
#define FPU_MVFR0_FP_excep_trapping_Pos   12U
 
#define FPU_MVFR0_FP_excep_trapping_Msk   (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)
 
#define FPU_MVFR0_Double_precision_Pos   8U
 
#define FPU_MVFR0_Double_precision_Msk   (0xFUL << FPU_MVFR0_Double_precision_Pos)
 
#define FPU_MVFR0_Single_precision_Pos   4U
 
#define FPU_MVFR0_Single_precision_Msk   (0xFUL << FPU_MVFR0_Single_precision_Pos)
 
#define FPU_MVFR0_A_SIMD_registers_Pos   0U
 
#define FPU_MVFR0_A_SIMD_registers_Msk   (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)
 
#define FPU_MVFR1_FP_fused_MAC_Pos   28U
 
#define FPU_MVFR1_FP_fused_MAC_Msk   (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)
 
#define FPU_MVFR1_FP_HPFP_Pos   24U
 
#define FPU_MVFR1_FP_HPFP_Msk   (0xFUL << FPU_MVFR1_FP_HPFP_Pos)
 
#define FPU_MVFR1_D_NaN_mode_Pos   4U
 
#define FPU_MVFR1_D_NaN_mode_Msk   (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)
 
#define FPU_MVFR1_FtZ_mode_Pos   0U
 
#define FPU_MVFR1_FtZ_mode_Msk   (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)
 
#define FPU_BASE   (SCS_BASE + 0x0F30UL)
 
#define FPU   ((FPU_Type *) FPU_BASE )
 
#define SCB_CFSR_MLSPERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 5U)
 
#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)
 
#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)
 
#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)
 
#define SCnSCB_ACTLR_DISFOLD_Pos   2U
 
#define SCnSCB_ACTLR_DISFOLD_Msk   (1UL << SCnSCB_ACTLR_DISFOLD_Pos)
 
#define MPU_TYPE_RALIASES   4U
 
#define FPU_FPCCR_ASPEN_Pos   31U
 
#define FPU_FPCCR_ASPEN_Msk   (1UL << FPU_FPCCR_ASPEN_Pos)
 
#define FPU_FPCCR_LSPEN_Pos   30U
 
#define FPU_FPCCR_LSPEN_Msk   (1UL << FPU_FPCCR_LSPEN_Pos)
 
#define FPU_FPCCR_MONRDY_Pos   8U
 
#define FPU_FPCCR_MONRDY_Msk   (1UL << FPU_FPCCR_MONRDY_Pos)
 
#define FPU_FPCCR_BFRDY_Pos   6U
 
#define FPU_FPCCR_BFRDY_Msk   (1UL << FPU_FPCCR_BFRDY_Pos)
 
#define FPU_FPCCR_MMRDY_Pos   5U
 
#define FPU_FPCCR_MMRDY_Msk   (1UL << FPU_FPCCR_MMRDY_Pos)
 
#define FPU_FPCCR_HFRDY_Pos   4U
 
#define FPU_FPCCR_HFRDY_Msk   (1UL << FPU_FPCCR_HFRDY_Pos)
 
#define FPU_FPCCR_THREAD_Pos   3U
 
#define FPU_FPCCR_THREAD_Msk   (1UL << FPU_FPCCR_THREAD_Pos)
 
#define FPU_FPCCR_USER_Pos   1U
 
#define FPU_FPCCR_USER_Msk   (1UL << FPU_FPCCR_USER_Pos)
 
#define FPU_FPCCR_LSPACT_Pos   0U
 
#define FPU_FPCCR_LSPACT_Msk   (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)
 
#define FPU_FPCAR_ADDRESS_Pos   3U
 
#define FPU_FPCAR_ADDRESS_Msk   (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
 
#define FPU_FPDSCR_AHP_Pos   26U
 
#define FPU_FPDSCR_AHP_Msk   (1UL << FPU_FPDSCR_AHP_Pos)
 
#define FPU_FPDSCR_DN_Pos   25U
 
#define FPU_FPDSCR_DN_Msk   (1UL << FPU_FPDSCR_DN_Pos)
 
#define FPU_FPDSCR_FZ_Pos   24U
 
#define FPU_FPDSCR_FZ_Msk   (1UL << FPU_FPDSCR_FZ_Pos)
 
#define FPU_FPDSCR_RMode_Pos   22U
 
#define FPU_FPDSCR_RMode_Msk   (3UL << FPU_FPDSCR_RMode_Pos)
 
#define FPU_MVFR0_FP_rounding_modes_Pos   28U
 
#define FPU_MVFR0_FP_rounding_modes_Msk   (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)
 
#define FPU_MVFR0_Short_vectors_Pos   24U
 
#define FPU_MVFR0_Short_vectors_Msk   (0xFUL << FPU_MVFR0_Short_vectors_Pos)
 
#define FPU_MVFR0_Square_root_Pos   20U
 
#define FPU_MVFR0_Square_root_Msk   (0xFUL << FPU_MVFR0_Square_root_Pos)
 
#define FPU_MVFR0_Divide_Pos   16U
 
#define FPU_MVFR0_Divide_Msk   (0xFUL << FPU_MVFR0_Divide_Pos)
 
#define FPU_MVFR0_FP_excep_trapping_Pos   12U
 
#define FPU_MVFR0_FP_excep_trapping_Msk   (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)
 
#define FPU_MVFR0_Double_precision_Pos   8U
 
#define FPU_MVFR0_Double_precision_Msk   (0xFUL << FPU_MVFR0_Double_precision_Pos)
 
#define FPU_MVFR0_Single_precision_Pos   4U
 
#define FPU_MVFR0_Single_precision_Msk   (0xFUL << FPU_MVFR0_Single_precision_Pos)
 
#define FPU_MVFR0_A_SIMD_registers_Pos   0U
 
#define FPU_MVFR0_A_SIMD_registers_Msk   (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)
 
#define FPU_MVFR1_FP_fused_MAC_Pos   28U
 
#define FPU_MVFR1_FP_fused_MAC_Msk   (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)
 
#define FPU_MVFR1_FP_HPFP_Pos   24U
 
#define FPU_MVFR1_FP_HPFP_Msk   (0xFUL << FPU_MVFR1_FP_HPFP_Pos)
 
#define FPU_MVFR1_D_NaN_mode_Pos   4U
 
#define FPU_MVFR1_D_NaN_mode_Msk   (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)
 
#define FPU_MVFR1_FtZ_mode_Pos   0U
 
#define FPU_MVFR1_FtZ_mode_Msk   (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)
 
#define FPU_BASE   (SCS_BASE + 0x0F30UL)
 
#define FPU   ((FPU_Type *) FPU_BASE )
 
#define EXC_RETURN_HANDLER_FPU   (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */
 
#define EXC_RETURN_THREAD_MSP_FPU   (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */
 
#define EXC_RETURN_THREAD_PSP_FPU   (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */
 
#define xPSR_IT_Pos   25U
 
#define xPSR_IT_Msk   (3UL << xPSR_IT_Pos)
 
#define CONTROL_SFPA_Pos   3U
 
#define CONTROL_SFPA_Msk   (1UL << CONTROL_SFPA_Pos)
 
#define xPSR_IT_Pos   25U
 
#define xPSR_IT_Msk   (3UL << xPSR_IT_Pos)
 
#define CONTROL_SFPA_Pos   3U
 
#define CONTROL_SFPA_Msk   (1UL << CONTROL_SFPA_Pos)
 
#define SCB_ICSR_PENDNMISET_Pos   31U
 
#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)
 
#define SCB_ICSR_PENDNMICLR_Pos   30U
 
#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)
 
#define SCB_ICSR_STTNS_Pos   24U
 
#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)
 
#define SCB_AIRCR_PRIS_Pos   14U
 
#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)
 
#define SCB_AIRCR_BFHFNMINS_Pos   13U
 
#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)
 
#define SCB_AIRCR_SYSRESETREQS_Pos   3U
 
#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
 
#define SCB_SCR_SLEEPDEEPS_Pos   3U
 
#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)
 
#define SCB_CCR_STKOFHFNMIGN_Pos   10U
 
#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
 
#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U
 
#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
 
#define SCB_SHCSR_SECUREFAULTPENDED_Pos   20U
 
#define SCB_SHCSR_SECUREFAULTPENDED_Msk   (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)
 
#define SCB_SHCSR_SECUREFAULTENA_Pos   19U
 
#define SCB_SHCSR_SECUREFAULTENA_Msk   (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)
 
#define SCB_SHCSR_NMIACT_Pos   5U
 
#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)
 
#define SCB_SHCSR_SECUREFAULTACT_Pos   4U
 
#define SCB_SHCSR_SECUREFAULTACT_Msk   (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)
 
#define SCB_SHCSR_HARDFAULTACT_Pos   2U
 
#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
 
#define SCB_CFSR_STKOF_Pos   (SCB_CFSR_USGFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKOF_Msk   (1UL << SCB_CFSR_STKOF_Pos)
 
#define SCB_NSACR_CP11_Pos   11U
 
#define SCB_NSACR_CP11_Msk   (1UL << SCB_NSACR_CP11_Pos)
 
#define SCB_NSACR_CP10_Pos   10U
 
#define SCB_NSACR_CP10_Msk   (1UL << SCB_NSACR_CP10_Pos)
 
#define SCB_NSACR_CPn_Pos   0U
 
#define SCB_NSACR_CPn_Msk   (1UL /*<< SCB_NSACR_CPn_Pos*/)
 
#define ITM_STIM_DISABLED_Pos   1U
 
#define ITM_STIM_DISABLED_Msk   (0x1UL << ITM_STIM_DISABLED_Pos)
 
#define ITM_STIM_FIFOREADY_Pos   0U
 
#define ITM_STIM_FIFOREADY_Msk   (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)
 
#define ITM_TCR_TRACEBUSID_Pos   16U
 
#define ITM_TCR_TRACEBUSID_Msk   (0x7FUL << ITM_TCR_TRACEBUSID_Pos)
 
#define ITM_TCR_TSPRESCALE_Pos   8U
 
#define ITM_TCR_TSPRESCALE_Msk   (3UL << ITM_TCR_TSPRESCALE_Pos)
 
#define ITM_TCR_STALLENA_Pos   5U
 
#define ITM_TCR_STALLENA_Msk   (1UL << ITM_TCR_STALLENA_Pos)
 
#define DWT_CTRL_CYCDISS_Pos   23U
 
#define DWT_CTRL_CYCDISS_Msk   (0x1UL << DWT_CTRL_CYCDISS_Pos)
 
#define DWT_FUNCTION_ID_Pos   27U
 
#define DWT_FUNCTION_ID_Msk   (0x1FUL << DWT_FUNCTION_ID_Pos)
 
#define DWT_FUNCTION_ACTION_Pos   4U
 
#define DWT_FUNCTION_ACTION_Msk   (0x1UL << DWT_FUNCTION_ACTION_Pos)
 
#define DWT_FUNCTION_MATCH_Pos   0U
 
#define DWT_FUNCTION_MATCH_Msk   (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)
 
#define TPI_FFCR_FOnMan_Pos   6U
 
#define TPI_FFCR_FOnMan_Msk   (0x1UL << TPI_FFCR_FOnMan_Pos)
 
#define TPI_DEVID_FIFOSZ_Pos   6U
 
#define TPI_DEVID_FIFOSZ_Msk   (0x7UL << TPI_DEVID_FIFOSZ_Pos)
 
#define MPU_RBAR_BASE_Pos   5U
 
#define MPU_RBAR_BASE_Msk   (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)
 
#define MPU_RBAR_SH_Pos   3U
 
#define MPU_RBAR_SH_Msk   (0x3UL << MPU_RBAR_SH_Pos)
 
#define MPU_RBAR_AP_Pos   1U
 
#define MPU_RBAR_AP_Msk   (0x3UL << MPU_RBAR_AP_Pos)
 
#define MPU_RBAR_XN_Pos   0U
 
#define MPU_RBAR_XN_Msk   (01UL /*<< MPU_RBAR_XN_Pos*/)
 
#define MPU_RLAR_LIMIT_Pos   5U
 
#define MPU_RLAR_LIMIT_Msk   (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)
 
#define MPU_RLAR_AttrIndx_Pos   1U
 
#define MPU_RLAR_AttrIndx_Msk   (0x7UL << MPU_RLAR_AttrIndx_Pos)
 
#define MPU_RLAR_EN_Pos   0U
 
#define MPU_RLAR_EN_Msk   (1UL /*<< MPU_RLAR_EN_Pos*/)
 
#define MPU_MAIR0_Attr3_Pos   24U
 
#define MPU_MAIR0_Attr3_Msk   (0xFFUL << MPU_MAIR0_Attr3_Pos)
 
#define MPU_MAIR0_Attr2_Pos   16U
 
#define MPU_MAIR0_Attr2_Msk   (0xFFUL << MPU_MAIR0_Attr2_Pos)
 
#define MPU_MAIR0_Attr1_Pos   8U
 
#define MPU_MAIR0_Attr1_Msk   (0xFFUL << MPU_MAIR0_Attr1_Pos)
 
#define MPU_MAIR0_Attr0_Pos   0U
 
#define MPU_MAIR0_Attr0_Msk   (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)
 
#define MPU_MAIR1_Attr7_Pos   24U
 
#define MPU_MAIR1_Attr7_Msk   (0xFFUL << MPU_MAIR1_Attr7_Pos)
 
#define MPU_MAIR1_Attr6_Pos   16U
 
#define MPU_MAIR1_Attr6_Msk   (0xFFUL << MPU_MAIR1_Attr6_Pos)
 
#define MPU_MAIR1_Attr5_Pos   8U
 
#define MPU_MAIR1_Attr5_Msk   (0xFFUL << MPU_MAIR1_Attr5_Pos)
 
#define MPU_MAIR1_Attr4_Pos   0U
 
#define MPU_MAIR1_Attr4_Msk   (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)
 
#define FPU_FPCCR_LSPENS_Pos   29U
 
#define FPU_FPCCR_LSPENS_Msk   (1UL << FPU_FPCCR_LSPENS_Pos)
 
#define FPU_FPCCR_CLRONRET_Pos   28U
 
#define FPU_FPCCR_CLRONRET_Msk   (1UL << FPU_FPCCR_CLRONRET_Pos)
 
#define FPU_FPCCR_CLRONRETS_Pos   27U
 
#define FPU_FPCCR_CLRONRETS_Msk   (1UL << FPU_FPCCR_CLRONRETS_Pos)
 
#define FPU_FPCCR_TS_Pos   26U
 
#define FPU_FPCCR_TS_Msk   (1UL << FPU_FPCCR_TS_Pos)
 
#define FPU_FPCCR_UFRDY_Pos   10U
 
#define FPU_FPCCR_UFRDY_Msk   (1UL << FPU_FPCCR_UFRDY_Pos)
 
#define FPU_FPCCR_SPLIMVIOL_Pos   9U
 
#define FPU_FPCCR_SPLIMVIOL_Msk   (1UL << FPU_FPCCR_SPLIMVIOL_Pos)
 
#define FPU_FPCCR_SFRDY_Pos   7U
 
#define FPU_FPCCR_SFRDY_Msk   (1UL << FPU_FPCCR_SFRDY_Pos)
 
#define FPU_FPCCR_S_Pos   2U
 
#define FPU_FPCCR_S_Msk   (1UL << FPU_FPCCR_S_Pos)
 
#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U
 
#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)
 
#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos   3U
 
#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)
 
#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos   2U
 
#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk   (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)
 
#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U
 
#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)
 
#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U
 
#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk   (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)
 
#define CoreDebug_DSCSR_CDS_Pos   16U
 
#define CoreDebug_DSCSR_CDS_Msk   (1UL << CoreDebug_DSCSR_CDS_Pos)
 
#define CoreDebug_DSCSR_SBRSEL_Pos   1U
 
#define CoreDebug_DSCSR_SBRSEL_Msk   (1UL << CoreDebug_DSCSR_SBRSEL_Pos)
 
#define CoreDebug_DSCSR_SBRSELEN_Pos   0U
 
#define CoreDebug_DSCSR_SBRSELEN_Msk   (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)
 
#define FNC_RETURN   (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
 
#define EXC_RETURN_PREFIX   (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
 
#define EXC_RETURN_S   (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
 
#define EXC_RETURN_DCRS   (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
 
#define EXC_RETURN_FTYPE   (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
 
#define EXC_RETURN_MODE   (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
 
#define EXC_RETURN_SPSEL   (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */
 
#define EXC_RETURN_ES   (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
 
#define EXC_INTEGRITY_SIGNATURE   (0xFEFA125BUL) /* Value for processors without floating-point extension */
 

Detailed Description

Core Register type definitions.

Macro Definition Documentation

◆ _FLD2VAL [1/12]

#define _FLD2VAL ( field,
value )
Value:
(((uint32_t)(value) & field ## _Msk) >> field ## _Pos)

Mask and shift a register value to extract a bit filed value.

Parameters
[in]fieldName of the register bit field.
[in]valueValue of register. This parameter is interpreted as an uint32_t type.
Returns
Masked and shifted bit field value.

◆ _FLD2VAL [2/12]

#define _FLD2VAL ( field,
value )
Value:
(((uint32_t)(value) & field ## _Msk) >> field ## _Pos)

Mask and shift a register value to extract a bit filed value.

Parameters
[in]fieldName of the register bit field.
[in]valueValue of register. This parameter is interpreted as an uint32_t type.
Returns
Masked and shifted bit field value.

◆ _FLD2VAL [3/12]

#define _FLD2VAL ( field,
value )
Value:
(((uint32_t)(value) & field ## _Msk) >> field ## _Pos)

Mask and shift a register value to extract a bit filed value.

Parameters
[in]fieldName of the register bit field.
[in]valueValue of register. This parameter is interpreted as an uint32_t type.
Returns
Masked and shifted bit field value.

◆ _FLD2VAL [4/12]

#define _FLD2VAL ( field,
value )
Value:
(((uint32_t)(value) & field ## _Msk) >> field ## _Pos)

Mask and shift a register value to extract a bit filed value.

Parameters
[in]fieldName of the register bit field.
[in]valueValue of register. This parameter is interpreted as an uint32_t type.
Returns
Masked and shifted bit field value.

◆ _FLD2VAL [5/12]

#define _FLD2VAL ( field,
value )
Value:
(((uint32_t)(value) & field ## _Msk) >> field ## _Pos)

Mask and shift a register value to extract a bit filed value.

Parameters
[in]fieldName of the register bit field.
[in]valueValue of register. This parameter is interpreted as an uint32_t type.
Returns
Masked and shifted bit field value.

◆ _FLD2VAL [6/12]

#define _FLD2VAL ( field,
value )
Value:
(((uint32_t)(value) & field ## _Msk) >> field ## _Pos)

Mask and shift a register value to extract a bit filed value.

Parameters
[in]fieldName of the register bit field.
[in]valueValue of register. This parameter is interpreted as an uint32_t type.
Returns
Masked and shifted bit field value.

◆ _FLD2VAL [7/12]

#define _FLD2VAL ( field,
value )
Value:
(((uint32_t)(value) & field ## _Msk) >> field ## _Pos)

Mask and shift a register value to extract a bit filed value.

Parameters
[in]fieldName of the register bit field.
[in]valueValue of register. This parameter is interpreted as an uint32_t type.
Returns
Masked and shifted bit field value.

◆ _FLD2VAL [8/12]

#define _FLD2VAL ( field,
value )
Value:
(((uint32_t)(value) & field ## _Msk) >> field ## _Pos)

Mask and shift a register value to extract a bit filed value.

Parameters
[in]fieldName of the register bit field.
[in]valueValue of register. This parameter is interpreted as an uint32_t type.
Returns
Masked and shifted bit field value.

◆ _FLD2VAL [9/12]

#define _FLD2VAL ( field,
value )
Value:
(((uint32_t)(value) & field ## _Msk) >> field ## _Pos)

Mask and shift a register value to extract a bit filed value.

Parameters
[in]fieldName of the register bit field.
[in]valueValue of register. This parameter is interpreted as an uint32_t type.
Returns
Masked and shifted bit field value.

◆ _FLD2VAL [10/12]

#define _FLD2VAL ( field,
value )
Value:
(((uint32_t)(value) & field ## _Msk) >> field ## _Pos)

Mask and shift a register value to extract a bit filed value.

Parameters
[in]fieldName of the register bit field.
[in]valueValue of register. This parameter is interpreted as an uint32_t type.
Returns
Masked and shifted bit field value.

◆ _FLD2VAL [11/12]

#define _FLD2VAL ( field,
value )
Value:
(((uint32_t)(value) & field ## _Msk) >> field ## _Pos)

Mask and shift a register value to extract a bit filed value.

Parameters
[in]fieldName of the register bit field.
[in]valueValue of register. This parameter is interpreted as an uint32_t type.
Returns
Masked and shifted bit field value.

◆ _FLD2VAL [12/12]

#define _FLD2VAL ( field,
value )
Value:
(((uint32_t)(value) & field ## _Msk) >> field ## _Pos)

Mask and shift a register value to extract a bit filed value.

Parameters
[in]fieldName of the register bit field.
[in]valueValue of register. This parameter is interpreted as an uint32_t type.
Returns
Masked and shifted bit field value.

◆ _VAL2FLD [1/12]

#define _VAL2FLD ( field,
value )
Value:
(((uint32_t)(value) << field ## _Pos) & field ## _Msk)

Mask and shift a bit field value for use in a register bit range.

Parameters
[in]fieldName of the register bit field.
[in]valueValue of the bit field. This parameter is interpreted as an uint32_t type.
Returns
Masked and shifted value.

◆ _VAL2FLD [2/12]

#define _VAL2FLD ( field,
value )
Value:
(((uint32_t)(value) << field ## _Pos) & field ## _Msk)

Mask and shift a bit field value for use in a register bit range.

Parameters
[in]fieldName of the register bit field.
[in]valueValue of the bit field. This parameter is interpreted as an uint32_t type.
Returns
Masked and shifted value.

◆ _VAL2FLD [3/12]

#define _VAL2FLD ( field,
value )
Value:
(((uint32_t)(value) << field ## _Pos) & field ## _Msk)

Mask and shift a bit field value for use in a register bit range.

Parameters
[in]fieldName of the register bit field.
[in]valueValue of the bit field. This parameter is interpreted as an uint32_t type.
Returns
Masked and shifted value.

◆ _VAL2FLD [4/12]

#define _VAL2FLD ( field,
value )
Value:
(((uint32_t)(value) << field ## _Pos) & field ## _Msk)

Mask and shift a bit field value for use in a register bit range.

Parameters
[in]fieldName of the register bit field.
[in]valueValue of the bit field. This parameter is interpreted as an uint32_t type.
Returns
Masked and shifted value.

◆ _VAL2FLD [5/12]

#define _VAL2FLD ( field,
value )
Value:
(((uint32_t)(value) << field ## _Pos) & field ## _Msk)

Mask and shift a bit field value for use in a register bit range.

Parameters
[in]fieldName of the register bit field.
[in]valueValue of the bit field. This parameter is interpreted as an uint32_t type.
Returns
Masked and shifted value.

◆ _VAL2FLD [6/12]

#define _VAL2FLD ( field,
value )
Value:
(((uint32_t)(value) << field ## _Pos) & field ## _Msk)

Mask and shift a bit field value for use in a register bit range.

Parameters
[in]fieldName of the register bit field.
[in]valueValue of the bit field. This parameter is interpreted as an uint32_t type.
Returns
Masked and shifted value.

◆ _VAL2FLD [7/12]

#define _VAL2FLD ( field,
value )
Value:
(((uint32_t)(value) << field ## _Pos) & field ## _Msk)

Mask and shift a bit field value for use in a register bit range.

Parameters
[in]fieldName of the register bit field.
[in]valueValue of the bit field. This parameter is interpreted as an uint32_t type.
Returns
Masked and shifted value.

◆ _VAL2FLD [8/12]

#define _VAL2FLD ( field,
value )
Value:
(((uint32_t)(value) << field ## _Pos) & field ## _Msk)

Mask and shift a bit field value for use in a register bit range.

Parameters
[in]fieldName of the register bit field.
[in]valueValue of the bit field. This parameter is interpreted as an uint32_t type.
Returns
Masked and shifted value.

◆ _VAL2FLD [9/12]

#define _VAL2FLD ( field,
value )
Value:
(((uint32_t)(value) << field ## _Pos) & field ## _Msk)

Mask and shift a bit field value for use in a register bit range.

Parameters
[in]fieldName of the register bit field.
[in]valueValue of the bit field. This parameter is interpreted as an uint32_t type.
Returns
Masked and shifted value.

◆ _VAL2FLD [10/12]

#define _VAL2FLD ( field,
value )
Value:
(((uint32_t)(value) << field ## _Pos) & field ## _Msk)

Mask and shift a bit field value for use in a register bit range.

Parameters
[in]fieldName of the register bit field.
[in]valueValue of the bit field. This parameter is interpreted as an uint32_t type.
Returns
Masked and shifted value.

◆ _VAL2FLD [11/12]

#define _VAL2FLD ( field,
value )
Value:
(((uint32_t)(value) << field ## _Pos) & field ## _Msk)

Mask and shift a bit field value for use in a register bit range.

Parameters
[in]fieldName of the register bit field.
[in]valueValue of the bit field. This parameter is interpreted as an uint32_t type.
Returns
Masked and shifted value.

◆ _VAL2FLD [12/12]

#define _VAL2FLD ( field,
value )
Value:
(((uint32_t)(value) << field ## _Pos) & field ## _Msk)

Mask and shift a bit field value for use in a register bit range.

Parameters
[in]fieldName of the register bit field.
[in]valueValue of the bit field. This parameter is interpreted as an uint32_t type.
Returns
Masked and shifted value.

◆ APSR_C_Msk [1/12]

#define APSR_C_Msk   (1UL << APSR_C_Pos)

APSR: C Mask

◆ APSR_C_Msk [2/12]

#define APSR_C_Msk   (1UL << APSR_C_Pos)

APSR: C Mask

◆ APSR_C_Msk [3/12]

#define APSR_C_Msk   (1UL << APSR_C_Pos)

APSR: C Mask

◆ APSR_C_Msk [4/12]

#define APSR_C_Msk   (1UL << APSR_C_Pos)

APSR: C Mask

◆ APSR_C_Msk [5/12]

#define APSR_C_Msk   (1UL << APSR_C_Pos)

APSR: C Mask

◆ APSR_C_Msk [6/12]

#define APSR_C_Msk   (1UL << APSR_C_Pos)

APSR: C Mask

◆ APSR_C_Msk [7/12]

#define APSR_C_Msk   (1UL << APSR_C_Pos)

APSR: C Mask

◆ APSR_C_Msk [8/12]

#define APSR_C_Msk   (1UL << APSR_C_Pos)

APSR: C Mask

◆ APSR_C_Msk [9/12]

#define APSR_C_Msk   (1UL << APSR_C_Pos)

APSR: C Mask

◆ APSR_C_Msk [10/12]

#define APSR_C_Msk   (1UL << APSR_C_Pos)

APSR: C Mask

◆ APSR_C_Msk [11/12]

#define APSR_C_Msk   (1UL << APSR_C_Pos)

APSR: C Mask

◆ APSR_C_Msk [12/12]

#define APSR_C_Msk   (1UL << APSR_C_Pos)

APSR: C Mask

◆ APSR_C_Pos [1/12]

#define APSR_C_Pos   29U

APSR: C Position

◆ APSR_C_Pos [2/12]

#define APSR_C_Pos   29U

APSR: C Position

◆ APSR_C_Pos [3/12]

#define APSR_C_Pos   29U

APSR: C Position

◆ APSR_C_Pos [4/12]

#define APSR_C_Pos   29U

APSR: C Position

◆ APSR_C_Pos [5/12]

#define APSR_C_Pos   29U

APSR: C Position

◆ APSR_C_Pos [6/12]

#define APSR_C_Pos   29U

APSR: C Position

◆ APSR_C_Pos [7/12]

#define APSR_C_Pos   29U

APSR: C Position

◆ APSR_C_Pos [8/12]

#define APSR_C_Pos   29U

APSR: C Position

◆ APSR_C_Pos [9/12]

#define APSR_C_Pos   29U

APSR: C Position

◆ APSR_C_Pos [10/12]

#define APSR_C_Pos   29U

APSR: C Position

◆ APSR_C_Pos [11/12]

#define APSR_C_Pos   29U

APSR: C Position

◆ APSR_C_Pos [12/12]

#define APSR_C_Pos   29U

APSR: C Position

◆ APSR_GE_Msk [1/4]

#define APSR_GE_Msk   (0xFUL << APSR_GE_Pos)

APSR: GE Mask

◆ APSR_GE_Msk [2/4]

#define APSR_GE_Msk   (0xFUL << APSR_GE_Pos)

APSR: GE Mask

◆ APSR_GE_Msk [3/4]

#define APSR_GE_Msk   (0xFUL << APSR_GE_Pos)

APSR: GE Mask

◆ APSR_GE_Msk [4/4]

#define APSR_GE_Msk   (0xFUL << APSR_GE_Pos)

APSR: GE Mask

◆ APSR_GE_Pos [1/4]

#define APSR_GE_Pos   16U

APSR: GE Position

◆ APSR_GE_Pos [2/4]

#define APSR_GE_Pos   16U

APSR: GE Position

◆ APSR_GE_Pos [3/4]

#define APSR_GE_Pos   16U

APSR: GE Position

◆ APSR_GE_Pos [4/4]

#define APSR_GE_Pos   16U

APSR: GE Position

◆ APSR_N_Msk [1/12]

#define APSR_N_Msk   (1UL << APSR_N_Pos)

APSR: N Mask

◆ APSR_N_Msk [2/12]

#define APSR_N_Msk   (1UL << APSR_N_Pos)

APSR: N Mask

◆ APSR_N_Msk [3/12]

#define APSR_N_Msk   (1UL << APSR_N_Pos)

APSR: N Mask

◆ APSR_N_Msk [4/12]

#define APSR_N_Msk   (1UL << APSR_N_Pos)

APSR: N Mask

◆ APSR_N_Msk [5/12]

#define APSR_N_Msk   (1UL << APSR_N_Pos)

APSR: N Mask

◆ APSR_N_Msk [6/12]

#define APSR_N_Msk   (1UL << APSR_N_Pos)

APSR: N Mask

◆ APSR_N_Msk [7/12]

#define APSR_N_Msk   (1UL << APSR_N_Pos)

APSR: N Mask

◆ APSR_N_Msk [8/12]

#define APSR_N_Msk   (1UL << APSR_N_Pos)

APSR: N Mask

◆ APSR_N_Msk [9/12]

#define APSR_N_Msk   (1UL << APSR_N_Pos)

APSR: N Mask

◆ APSR_N_Msk [10/12]

#define APSR_N_Msk   (1UL << APSR_N_Pos)

APSR: N Mask

◆ APSR_N_Msk [11/12]

#define APSR_N_Msk   (1UL << APSR_N_Pos)

APSR: N Mask

◆ APSR_N_Msk [12/12]

#define APSR_N_Msk   (1UL << APSR_N_Pos)

APSR: N Mask

◆ APSR_N_Pos [1/12]

#define APSR_N_Pos   31U

APSR: N Position

◆ APSR_N_Pos [2/12]

#define APSR_N_Pos   31U

APSR: N Position

◆ APSR_N_Pos [3/12]

#define APSR_N_Pos   31U

APSR: N Position

◆ APSR_N_Pos [4/12]

#define APSR_N_Pos   31U

APSR: N Position

◆ APSR_N_Pos [5/12]

#define APSR_N_Pos   31U

APSR: N Position

◆ APSR_N_Pos [6/12]

#define APSR_N_Pos   31U

APSR: N Position

◆ APSR_N_Pos [7/12]

#define APSR_N_Pos   31U

APSR: N Position

◆ APSR_N_Pos [8/12]

#define APSR_N_Pos   31U

APSR: N Position

◆ APSR_N_Pos [9/12]

#define APSR_N_Pos   31U

APSR: N Position

◆ APSR_N_Pos [10/12]

#define APSR_N_Pos   31U

APSR: N Position

◆ APSR_N_Pos [11/12]

#define APSR_N_Pos   31U

APSR: N Position

◆ APSR_N_Pos [12/12]

#define APSR_N_Pos   31U

APSR: N Position

◆ APSR_Q_Msk [1/6]

#define APSR_Q_Msk   (1UL << APSR_Q_Pos)

APSR: Q Mask

◆ APSR_Q_Msk [2/6]

#define APSR_Q_Msk   (1UL << APSR_Q_Pos)

APSR: Q Mask

◆ APSR_Q_Msk [3/6]

#define APSR_Q_Msk   (1UL << APSR_Q_Pos)

APSR: Q Mask

◆ APSR_Q_Msk [4/6]

#define APSR_Q_Msk   (1UL << APSR_Q_Pos)

APSR: Q Mask

◆ APSR_Q_Msk [5/6]

#define APSR_Q_Msk   (1UL << APSR_Q_Pos)

APSR: Q Mask

◆ APSR_Q_Msk [6/6]

#define APSR_Q_Msk   (1UL << APSR_Q_Pos)

APSR: Q Mask

◆ APSR_Q_Pos [1/6]

#define APSR_Q_Pos   27U

APSR: Q Position

◆ APSR_Q_Pos [2/6]

#define APSR_Q_Pos   27U

APSR: Q Position

◆ APSR_Q_Pos [3/6]

#define APSR_Q_Pos   27U

APSR: Q Position

◆ APSR_Q_Pos [4/6]

#define APSR_Q_Pos   27U

APSR: Q Position

◆ APSR_Q_Pos [5/6]

#define APSR_Q_Pos   27U

APSR: Q Position

◆ APSR_Q_Pos [6/6]

#define APSR_Q_Pos   27U

APSR: Q Position

◆ APSR_V_Msk [1/12]

#define APSR_V_Msk   (1UL << APSR_V_Pos)

APSR: V Mask

◆ APSR_V_Msk [2/12]

#define APSR_V_Msk   (1UL << APSR_V_Pos)

APSR: V Mask

◆ APSR_V_Msk [3/12]

#define APSR_V_Msk   (1UL << APSR_V_Pos)

APSR: V Mask

◆ APSR_V_Msk [4/12]

#define APSR_V_Msk   (1UL << APSR_V_Pos)

APSR: V Mask

◆ APSR_V_Msk [5/12]

#define APSR_V_Msk   (1UL << APSR_V_Pos)

APSR: V Mask

◆ APSR_V_Msk [6/12]

#define APSR_V_Msk   (1UL << APSR_V_Pos)

APSR: V Mask

◆ APSR_V_Msk [7/12]

#define APSR_V_Msk   (1UL << APSR_V_Pos)

APSR: V Mask

◆ APSR_V_Msk [8/12]

#define APSR_V_Msk   (1UL << APSR_V_Pos)

APSR: V Mask

◆ APSR_V_Msk [9/12]

#define APSR_V_Msk   (1UL << APSR_V_Pos)

APSR: V Mask

◆ APSR_V_Msk [10/12]

#define APSR_V_Msk   (1UL << APSR_V_Pos)

APSR: V Mask

◆ APSR_V_Msk [11/12]

#define APSR_V_Msk   (1UL << APSR_V_Pos)

APSR: V Mask

◆ APSR_V_Msk [12/12]

#define APSR_V_Msk   (1UL << APSR_V_Pos)

APSR: V Mask

◆ APSR_V_Pos [1/12]

#define APSR_V_Pos   28U

APSR: V Position

◆ APSR_V_Pos [2/12]

#define APSR_V_Pos   28U

APSR: V Position

◆ APSR_V_Pos [3/12]

#define APSR_V_Pos   28U

APSR: V Position

◆ APSR_V_Pos [4/12]

#define APSR_V_Pos   28U

APSR: V Position

◆ APSR_V_Pos [5/12]

#define APSR_V_Pos   28U

APSR: V Position

◆ APSR_V_Pos [6/12]

#define APSR_V_Pos   28U

APSR: V Position

◆ APSR_V_Pos [7/12]

#define APSR_V_Pos   28U

APSR: V Position

◆ APSR_V_Pos [8/12]

#define APSR_V_Pos   28U

APSR: V Position

◆ APSR_V_Pos [9/12]

#define APSR_V_Pos   28U

APSR: V Position

◆ APSR_V_Pos [10/12]

#define APSR_V_Pos   28U

APSR: V Position

◆ APSR_V_Pos [11/12]

#define APSR_V_Pos   28U

APSR: V Position

◆ APSR_V_Pos [12/12]

#define APSR_V_Pos   28U

APSR: V Position

◆ APSR_Z_Msk [1/12]

#define APSR_Z_Msk   (1UL << APSR_Z_Pos)

APSR: Z Mask

◆ APSR_Z_Msk [2/12]

#define APSR_Z_Msk   (1UL << APSR_Z_Pos)

APSR: Z Mask

◆ APSR_Z_Msk [3/12]

#define APSR_Z_Msk   (1UL << APSR_Z_Pos)

APSR: Z Mask

◆ APSR_Z_Msk [4/12]

#define APSR_Z_Msk   (1UL << APSR_Z_Pos)

APSR: Z Mask

◆ APSR_Z_Msk [5/12]

#define APSR_Z_Msk   (1UL << APSR_Z_Pos)

APSR: Z Mask

◆ APSR_Z_Msk [6/12]

#define APSR_Z_Msk   (1UL << APSR_Z_Pos)

APSR: Z Mask

◆ APSR_Z_Msk [7/12]

#define APSR_Z_Msk   (1UL << APSR_Z_Pos)

APSR: Z Mask

◆ APSR_Z_Msk [8/12]

#define APSR_Z_Msk   (1UL << APSR_Z_Pos)

APSR: Z Mask

◆ APSR_Z_Msk [9/12]

#define APSR_Z_Msk   (1UL << APSR_Z_Pos)

APSR: Z Mask

◆ APSR_Z_Msk [10/12]

#define APSR_Z_Msk   (1UL << APSR_Z_Pos)

APSR: Z Mask

◆ APSR_Z_Msk [11/12]

#define APSR_Z_Msk   (1UL << APSR_Z_Pos)

APSR: Z Mask

◆ APSR_Z_Msk [12/12]

#define APSR_Z_Msk   (1UL << APSR_Z_Pos)

APSR: Z Mask

◆ APSR_Z_Pos [1/12]

#define APSR_Z_Pos   30U

APSR: Z Position

◆ APSR_Z_Pos [2/12]

#define APSR_Z_Pos   30U

APSR: Z Position

◆ APSR_Z_Pos [3/12]

#define APSR_Z_Pos   30U

APSR: Z Position

◆ APSR_Z_Pos [4/12]

#define APSR_Z_Pos   30U

APSR: Z Position

◆ APSR_Z_Pos [5/12]

#define APSR_Z_Pos   30U

APSR: Z Position

◆ APSR_Z_Pos [6/12]

#define APSR_Z_Pos   30U

APSR: Z Position

◆ APSR_Z_Pos [7/12]

#define APSR_Z_Pos   30U

APSR: Z Position

◆ APSR_Z_Pos [8/12]

#define APSR_Z_Pos   30U

APSR: Z Position

◆ APSR_Z_Pos [9/12]

#define APSR_Z_Pos   30U

APSR: Z Position

◆ APSR_Z_Pos [10/12]

#define APSR_Z_Pos   30U

APSR: Z Position

◆ APSR_Z_Pos [11/12]

#define APSR_Z_Pos   30U

APSR: Z Position

◆ APSR_Z_Pos [12/12]

#define APSR_Z_Pos   30U

APSR: Z Position

◆ CONTROL_FPCA_Msk [1/4]

#define CONTROL_FPCA_Msk   (1UL << CONTROL_FPCA_Pos)

CONTROL: FPCA Mask

◆ CONTROL_FPCA_Msk [2/4]

#define CONTROL_FPCA_Msk   (1UL << CONTROL_FPCA_Pos)

CONTROL: FPCA Mask

◆ CONTROL_FPCA_Msk [3/4]

#define CONTROL_FPCA_Msk   (1UL << CONTROL_FPCA_Pos)

CONTROL: FPCA Mask

◆ CONTROL_FPCA_Msk [4/4]

#define CONTROL_FPCA_Msk   (1UL << CONTROL_FPCA_Pos)

CONTROL: FPCA Mask

◆ CONTROL_FPCA_Pos [1/4]

#define CONTROL_FPCA_Pos   2U

CONTROL: FPCA Position

◆ CONTROL_FPCA_Pos [2/4]

#define CONTROL_FPCA_Pos   2U

CONTROL: FPCA Position

◆ CONTROL_FPCA_Pos [3/4]

#define CONTROL_FPCA_Pos   2U

CONTROL: FPCA Position

◆ CONTROL_FPCA_Pos [4/4]

#define CONTROL_FPCA_Pos   2U

CONTROL: FPCA Position

◆ CONTROL_nPRIV_Msk [1/9]

#define CONTROL_nPRIV_Msk   (1UL /*<< CONTROL_nPRIV_Pos*/)

CONTROL: nPRIV Mask

◆ CONTROL_nPRIV_Msk [2/9]

#define CONTROL_nPRIV_Msk   (1UL /*<< CONTROL_nPRIV_Pos*/)

CONTROL: nPRIV Mask

◆ CONTROL_nPRIV_Msk [3/9]

#define CONTROL_nPRIV_Msk   (1UL /*<< CONTROL_nPRIV_Pos*/)

CONTROL: nPRIV Mask

◆ CONTROL_nPRIV_Msk [4/9]

#define CONTROL_nPRIV_Msk   (1UL /*<< CONTROL_nPRIV_Pos*/)

CONTROL: nPRIV Mask

◆ CONTROL_nPRIV_Msk [5/9]

#define CONTROL_nPRIV_Msk   (1UL /*<< CONTROL_nPRIV_Pos*/)

CONTROL: nPRIV Mask

◆ CONTROL_nPRIV_Msk [6/9]

#define CONTROL_nPRIV_Msk   (1UL /*<< CONTROL_nPRIV_Pos*/)

CONTROL: nPRIV Mask

◆ CONTROL_nPRIV_Msk [7/9]

#define CONTROL_nPRIV_Msk   (1UL /*<< CONTROL_nPRIV_Pos*/)

CONTROL: nPRIV Mask

◆ CONTROL_nPRIV_Msk [8/9]

#define CONTROL_nPRIV_Msk   (1UL /*<< CONTROL_nPRIV_Pos*/)

CONTROL: nPRIV Mask

◆ CONTROL_nPRIV_Msk [9/9]

#define CONTROL_nPRIV_Msk   (1UL /*<< CONTROL_nPRIV_Pos*/)

CONTROL: nPRIV Mask

◆ CONTROL_nPRIV_Pos [1/9]

#define CONTROL_nPRIV_Pos   0U

CONTROL: nPRIV Position

◆ CONTROL_nPRIV_Pos [2/9]

#define CONTROL_nPRIV_Pos   0U

CONTROL: nPRIV Position

◆ CONTROL_nPRIV_Pos [3/9]

#define CONTROL_nPRIV_Pos   0U

CONTROL: nPRIV Position

◆ CONTROL_nPRIV_Pos [4/9]

#define CONTROL_nPRIV_Pos   0U

CONTROL: nPRIV Position

◆ CONTROL_nPRIV_Pos [5/9]

#define CONTROL_nPRIV_Pos   0U

CONTROL: nPRIV Position

◆ CONTROL_nPRIV_Pos [6/9]

#define CONTROL_nPRIV_Pos   0U

CONTROL: nPRIV Position

◆ CONTROL_nPRIV_Pos [7/9]

#define CONTROL_nPRIV_Pos   0U

CONTROL: nPRIV Position

◆ CONTROL_nPRIV_Pos [8/9]

#define CONTROL_nPRIV_Pos   0U

CONTROL: nPRIV Position

◆ CONTROL_nPRIV_Pos [9/9]

#define CONTROL_nPRIV_Pos   0U

CONTROL: nPRIV Position

◆ CONTROL_SFPA_Msk [1/2]

#define CONTROL_SFPA_Msk   (1UL << CONTROL_SFPA_Pos)

CONTROL: SFPA Mask

◆ CONTROL_SFPA_Msk [2/2]

#define CONTROL_SFPA_Msk   (1UL << CONTROL_SFPA_Pos)

CONTROL: SFPA Mask

◆ CONTROL_SFPA_Pos [1/2]

#define CONTROL_SFPA_Pos   3U

CONTROL: SFPA Position

◆ CONTROL_SFPA_Pos [2/2]

#define CONTROL_SFPA_Pos   3U

CONTROL: SFPA Position

◆ CONTROL_SPSEL_Msk [1/12]

#define CONTROL_SPSEL_Msk   (1UL << CONTROL_SPSEL_Pos)

CONTROL: SPSEL Mask

◆ CONTROL_SPSEL_Msk [2/12]

#define CONTROL_SPSEL_Msk   (1UL << CONTROL_SPSEL_Pos)

CONTROL: SPSEL Mask

◆ CONTROL_SPSEL_Msk [3/12]

#define CONTROL_SPSEL_Msk   (1UL << CONTROL_SPSEL_Pos)

CONTROL: SPSEL Mask

◆ CONTROL_SPSEL_Msk [4/12]

#define CONTROL_SPSEL_Msk   (1UL << CONTROL_SPSEL_Pos)

CONTROL: SPSEL Mask

◆ CONTROL_SPSEL_Msk [5/12]

#define CONTROL_SPSEL_Msk   (1UL << CONTROL_SPSEL_Pos)

CONTROL: SPSEL Mask

◆ CONTROL_SPSEL_Msk [6/12]

#define CONTROL_SPSEL_Msk   (1UL << CONTROL_SPSEL_Pos)

CONTROL: SPSEL Mask

◆ CONTROL_SPSEL_Msk [7/12]

#define CONTROL_SPSEL_Msk   (1UL << CONTROL_SPSEL_Pos)

CONTROL: SPSEL Mask

◆ CONTROL_SPSEL_Msk [8/12]

#define CONTROL_SPSEL_Msk   (1UL << CONTROL_SPSEL_Pos)

CONTROL: SPSEL Mask

◆ CONTROL_SPSEL_Msk [9/12]

#define CONTROL_SPSEL_Msk   (1UL << CONTROL_SPSEL_Pos)

CONTROL: SPSEL Mask

◆ CONTROL_SPSEL_Msk [10/12]

#define CONTROL_SPSEL_Msk   (1UL << CONTROL_SPSEL_Pos)

CONTROL: SPSEL Mask

◆ CONTROL_SPSEL_Msk [11/12]

#define CONTROL_SPSEL_Msk   (1UL << CONTROL_SPSEL_Pos)

CONTROL: SPSEL Mask

◆ CONTROL_SPSEL_Msk [12/12]

#define CONTROL_SPSEL_Msk   (1UL << CONTROL_SPSEL_Pos)

CONTROL: SPSEL Mask

◆ CONTROL_SPSEL_Pos [1/12]

#define CONTROL_SPSEL_Pos   1U

CONTROL: SPSEL Position

◆ CONTROL_SPSEL_Pos [2/12]

#define CONTROL_SPSEL_Pos   1U

CONTROL: SPSEL Position

◆ CONTROL_SPSEL_Pos [3/12]

#define CONTROL_SPSEL_Pos   1U

CONTROL: SPSEL Position

◆ CONTROL_SPSEL_Pos [4/12]

#define CONTROL_SPSEL_Pos   1U

CONTROL: SPSEL Position

◆ CONTROL_SPSEL_Pos [5/12]

#define CONTROL_SPSEL_Pos   1U

CONTROL: SPSEL Position

◆ CONTROL_SPSEL_Pos [6/12]

#define CONTROL_SPSEL_Pos   1U

CONTROL: SPSEL Position

◆ CONTROL_SPSEL_Pos [7/12]

#define CONTROL_SPSEL_Pos   1U

CONTROL: SPSEL Position

◆ CONTROL_SPSEL_Pos [8/12]

#define CONTROL_SPSEL_Pos   1U

CONTROL: SPSEL Position

◆ CONTROL_SPSEL_Pos [9/12]

#define CONTROL_SPSEL_Pos   1U

CONTROL: SPSEL Position

◆ CONTROL_SPSEL_Pos [10/12]

#define CONTROL_SPSEL_Pos   1U

CONTROL: SPSEL Position

◆ CONTROL_SPSEL_Pos [11/12]

#define CONTROL_SPSEL_Pos   1U

CONTROL: SPSEL Position

◆ CONTROL_SPSEL_Pos [12/12]

#define CONTROL_SPSEL_Pos   1U

CONTROL: SPSEL Position

◆ CoreDebug [1/8]

#define CoreDebug   ((CoreDebug_Type *) CoreDebug_BASE )

Core Debug configuration struct

◆ CoreDebug [2/8]

#define CoreDebug   ((CoreDebug_Type *) CoreDebug_BASE )

Core Debug configuration struct

◆ CoreDebug [3/8]

#define CoreDebug   ((CoreDebug_Type *) CoreDebug_BASE )

Core Debug configuration struct

◆ CoreDebug [4/8]

#define CoreDebug   ((CoreDebug_Type *) CoreDebug_BASE)

Core Debug configuration struct

◆ CoreDebug [5/8]

#define CoreDebug   ((CoreDebug_Type *) CoreDebug_BASE )

Core Debug configuration struct

◆ CoreDebug [6/8]

#define CoreDebug   ((CoreDebug_Type *) CoreDebug_BASE)

Core Debug configuration struct

◆ CoreDebug [7/8]

#define CoreDebug   ((CoreDebug_Type *) CoreDebug_BASE)

Core Debug configuration struct

◆ CoreDebug [8/8]

#define CoreDebug   ((CoreDebug_Type *) CoreDebug_BASE)

Core Debug configuration struct

◆ CoreDebug_BASE [1/8]

#define CoreDebug_BASE   (0xE000EDF0UL)

Core Debug Base Address

◆ CoreDebug_BASE [2/8]

#define CoreDebug_BASE   (0xE000EDF0UL)

Core Debug Base Address

◆ CoreDebug_BASE [3/8]

#define CoreDebug_BASE   (0xE000EDF0UL)

Core Debug Base Address

◆ CoreDebug_BASE [4/8]

#define CoreDebug_BASE   (0xE000EDF0UL)

Core Debug Base Address

◆ CoreDebug_BASE [5/8]

#define CoreDebug_BASE   (0xE000EDF0UL)

Core Debug Base Address

◆ CoreDebug_BASE [6/8]

#define CoreDebug_BASE   (0xE000EDF0UL)

Core Debug Base Address

◆ CoreDebug_BASE [7/8]

#define CoreDebug_BASE   (0xE000EDF0UL)

Core Debug Base Address

◆ CoreDebug_BASE [8/8]

#define CoreDebug_BASE   (0xE000EDF0UL)

Core Debug Base Address

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Msk

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)

CoreDebug DAUTHCTRL: INTSPIDEN Mask

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Pos

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U

CoreDebug DAUTHCTRL: INTSPIDEN Position

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)

CoreDebug DAUTHCTRL: INTSPNIDEN, Mask

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos   3U

CoreDebug DAUTHCTRL: INTSPNIDEN, Position

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Msk

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk   (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)

CoreDebug DAUTHCTRL: SPIDENSEL Mask

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Pos

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U

CoreDebug DAUTHCTRL: SPIDENSEL Position

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk   (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)

CoreDebug DAUTHCTRL: SPNIDENSEL Mask

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos   2U

CoreDebug DAUTHCTRL: SPNIDENSEL Position

◆ CoreDebug_DCRSR_REGSEL_Msk [1/8]

#define CoreDebug_DCRSR_REGSEL_Msk   (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

◆ CoreDebug_DCRSR_REGSEL_Msk [2/8]

#define CoreDebug_DCRSR_REGSEL_Msk   (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

◆ CoreDebug_DCRSR_REGSEL_Msk [3/8]

#define CoreDebug_DCRSR_REGSEL_Msk   (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

◆ CoreDebug_DCRSR_REGSEL_Msk [4/8]

#define CoreDebug_DCRSR_REGSEL_Msk   (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

◆ CoreDebug_DCRSR_REGSEL_Msk [5/8]

#define CoreDebug_DCRSR_REGSEL_Msk   (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

◆ CoreDebug_DCRSR_REGSEL_Msk [6/8]

#define CoreDebug_DCRSR_REGSEL_Msk   (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

◆ CoreDebug_DCRSR_REGSEL_Msk [7/8]

#define CoreDebug_DCRSR_REGSEL_Msk   (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

◆ CoreDebug_DCRSR_REGSEL_Msk [8/8]

#define CoreDebug_DCRSR_REGSEL_Msk   (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

◆ CoreDebug_DCRSR_REGSEL_Pos [1/8]

#define CoreDebug_DCRSR_REGSEL_Pos   0U

CoreDebug DCRSR: REGSEL Position

◆ CoreDebug_DCRSR_REGSEL_Pos [2/8]

#define CoreDebug_DCRSR_REGSEL_Pos   0U

CoreDebug DCRSR: REGSEL Position

◆ CoreDebug_DCRSR_REGSEL_Pos [3/8]

#define CoreDebug_DCRSR_REGSEL_Pos   0U

CoreDebug DCRSR: REGSEL Position

◆ CoreDebug_DCRSR_REGSEL_Pos [4/8]

#define CoreDebug_DCRSR_REGSEL_Pos   0U

CoreDebug DCRSR: REGSEL Position

◆ CoreDebug_DCRSR_REGSEL_Pos [5/8]

#define CoreDebug_DCRSR_REGSEL_Pos   0U

CoreDebug DCRSR: REGSEL Position

◆ CoreDebug_DCRSR_REGSEL_Pos [6/8]

#define CoreDebug_DCRSR_REGSEL_Pos   0U

CoreDebug DCRSR: REGSEL Position

◆ CoreDebug_DCRSR_REGSEL_Pos [7/8]

#define CoreDebug_DCRSR_REGSEL_Pos   0U

CoreDebug DCRSR: REGSEL Position

◆ CoreDebug_DCRSR_REGSEL_Pos [8/8]

#define CoreDebug_DCRSR_REGSEL_Pos   0U

CoreDebug DCRSR: REGSEL Position

◆ CoreDebug_DCRSR_REGWnR_Msk [1/8]

#define CoreDebug_DCRSR_REGWnR_Msk   (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

◆ CoreDebug_DCRSR_REGWnR_Msk [2/8]

#define CoreDebug_DCRSR_REGWnR_Msk   (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

◆ CoreDebug_DCRSR_REGWnR_Msk [3/8]

#define CoreDebug_DCRSR_REGWnR_Msk   (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

◆ CoreDebug_DCRSR_REGWnR_Msk [4/8]

#define CoreDebug_DCRSR_REGWnR_Msk   (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

◆ CoreDebug_DCRSR_REGWnR_Msk [5/8]

#define CoreDebug_DCRSR_REGWnR_Msk   (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

◆ CoreDebug_DCRSR_REGWnR_Msk [6/8]

#define CoreDebug_DCRSR_REGWnR_Msk   (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

◆ CoreDebug_DCRSR_REGWnR_Msk [7/8]

#define CoreDebug_DCRSR_REGWnR_Msk   (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

◆ CoreDebug_DCRSR_REGWnR_Msk [8/8]

#define CoreDebug_DCRSR_REGWnR_Msk   (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

◆ CoreDebug_DCRSR_REGWnR_Pos [1/8]

#define CoreDebug_DCRSR_REGWnR_Pos   16U

CoreDebug DCRSR: REGWnR Position

◆ CoreDebug_DCRSR_REGWnR_Pos [2/8]

#define CoreDebug_DCRSR_REGWnR_Pos   16U

CoreDebug DCRSR: REGWnR Position

◆ CoreDebug_DCRSR_REGWnR_Pos [3/8]

#define CoreDebug_DCRSR_REGWnR_Pos   16U

CoreDebug DCRSR: REGWnR Position

◆ CoreDebug_DCRSR_REGWnR_Pos [4/8]

#define CoreDebug_DCRSR_REGWnR_Pos   16U

CoreDebug DCRSR: REGWnR Position

◆ CoreDebug_DCRSR_REGWnR_Pos [5/8]

#define CoreDebug_DCRSR_REGWnR_Pos   16U

CoreDebug DCRSR: REGWnR Position

◆ CoreDebug_DCRSR_REGWnR_Pos [6/8]

#define CoreDebug_DCRSR_REGWnR_Pos   16U

CoreDebug DCRSR: REGWnR Position

◆ CoreDebug_DCRSR_REGWnR_Pos [7/8]

#define CoreDebug_DCRSR_REGWnR_Pos   16U

CoreDebug DCRSR: REGWnR Position

◆ CoreDebug_DCRSR_REGWnR_Pos [8/8]

#define CoreDebug_DCRSR_REGWnR_Pos   16U

CoreDebug DCRSR: REGWnR Position

◆ CoreDebug_DEMCR_MON_EN_Msk [1/6]

#define CoreDebug_DEMCR_MON_EN_Msk   (1UL << CoreDebug_DEMCR_MON_EN_Pos)

CoreDebug DEMCR: MON_EN Mask

◆ CoreDebug_DEMCR_MON_EN_Msk [2/6]

#define CoreDebug_DEMCR_MON_EN_Msk   (1UL << CoreDebug_DEMCR_MON_EN_Pos)

CoreDebug DEMCR: MON_EN Mask

◆ CoreDebug_DEMCR_MON_EN_Msk [3/6]

#define CoreDebug_DEMCR_MON_EN_Msk   (1UL << CoreDebug_DEMCR_MON_EN_Pos)

CoreDebug DEMCR: MON_EN Mask

◆ CoreDebug_DEMCR_MON_EN_Msk [4/6]

#define CoreDebug_DEMCR_MON_EN_Msk   (1UL << CoreDebug_DEMCR_MON_EN_Pos)

CoreDebug DEMCR: MON_EN Mask

◆ CoreDebug_DEMCR_MON_EN_Msk [5/6]

#define CoreDebug_DEMCR_MON_EN_Msk   (1UL << CoreDebug_DEMCR_MON_EN_Pos)

CoreDebug DEMCR: MON_EN Mask

◆ CoreDebug_DEMCR_MON_EN_Msk [6/6]

#define CoreDebug_DEMCR_MON_EN_Msk   (1UL << CoreDebug_DEMCR_MON_EN_Pos)

CoreDebug DEMCR: MON_EN Mask

◆ CoreDebug_DEMCR_MON_EN_Pos [1/6]

#define CoreDebug_DEMCR_MON_EN_Pos   16U

CoreDebug DEMCR: MON_EN Position

◆ CoreDebug_DEMCR_MON_EN_Pos [2/6]

#define CoreDebug_DEMCR_MON_EN_Pos   16U

CoreDebug DEMCR: MON_EN Position

◆ CoreDebug_DEMCR_MON_EN_Pos [3/6]

#define CoreDebug_DEMCR_MON_EN_Pos   16U

CoreDebug DEMCR: MON_EN Position

◆ CoreDebug_DEMCR_MON_EN_Pos [4/6]

#define CoreDebug_DEMCR_MON_EN_Pos   16U

CoreDebug DEMCR: MON_EN Position

◆ CoreDebug_DEMCR_MON_EN_Pos [5/6]

#define CoreDebug_DEMCR_MON_EN_Pos   16U

CoreDebug DEMCR: MON_EN Position

◆ CoreDebug_DEMCR_MON_EN_Pos [6/6]

#define CoreDebug_DEMCR_MON_EN_Pos   16U

CoreDebug DEMCR: MON_EN Position

◆ CoreDebug_DEMCR_MON_PEND_Msk [1/6]

#define CoreDebug_DEMCR_MON_PEND_Msk   (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

CoreDebug DEMCR: MON_PEND Mask

◆ CoreDebug_DEMCR_MON_PEND_Msk [2/6]

#define CoreDebug_DEMCR_MON_PEND_Msk   (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

CoreDebug DEMCR: MON_PEND Mask

◆ CoreDebug_DEMCR_MON_PEND_Msk [3/6]

#define CoreDebug_DEMCR_MON_PEND_Msk   (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

CoreDebug DEMCR: MON_PEND Mask

◆ CoreDebug_DEMCR_MON_PEND_Msk [4/6]

#define CoreDebug_DEMCR_MON_PEND_Msk   (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

CoreDebug DEMCR: MON_PEND Mask

◆ CoreDebug_DEMCR_MON_PEND_Msk [5/6]

#define CoreDebug_DEMCR_MON_PEND_Msk   (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

CoreDebug DEMCR: MON_PEND Mask

◆ CoreDebug_DEMCR_MON_PEND_Msk [6/6]

#define CoreDebug_DEMCR_MON_PEND_Msk   (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

CoreDebug DEMCR: MON_PEND Mask

◆ CoreDebug_DEMCR_MON_PEND_Pos [1/6]

#define CoreDebug_DEMCR_MON_PEND_Pos   17U

CoreDebug DEMCR: MON_PEND Position

◆ CoreDebug_DEMCR_MON_PEND_Pos [2/6]

#define CoreDebug_DEMCR_MON_PEND_Pos   17U

CoreDebug DEMCR: MON_PEND Position

◆ CoreDebug_DEMCR_MON_PEND_Pos [3/6]

#define CoreDebug_DEMCR_MON_PEND_Pos   17U

CoreDebug DEMCR: MON_PEND Position

◆ CoreDebug_DEMCR_MON_PEND_Pos [4/6]

#define CoreDebug_DEMCR_MON_PEND_Pos   17U

CoreDebug DEMCR: MON_PEND Position

◆ CoreDebug_DEMCR_MON_PEND_Pos [5/6]

#define CoreDebug_DEMCR_MON_PEND_Pos   17U

CoreDebug DEMCR: MON_PEND Position

◆ CoreDebug_DEMCR_MON_PEND_Pos [6/6]

#define CoreDebug_DEMCR_MON_PEND_Pos   17U

CoreDebug DEMCR: MON_PEND Position

◆ CoreDebug_DEMCR_MON_REQ_Msk [1/6]

#define CoreDebug_DEMCR_MON_REQ_Msk   (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

CoreDebug DEMCR: MON_REQ Mask

◆ CoreDebug_DEMCR_MON_REQ_Msk [2/6]

#define CoreDebug_DEMCR_MON_REQ_Msk   (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

CoreDebug DEMCR: MON_REQ Mask

◆ CoreDebug_DEMCR_MON_REQ_Msk [3/6]

#define CoreDebug_DEMCR_MON_REQ_Msk   (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

CoreDebug DEMCR: MON_REQ Mask

◆ CoreDebug_DEMCR_MON_REQ_Msk [4/6]

#define CoreDebug_DEMCR_MON_REQ_Msk   (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

CoreDebug DEMCR: MON_REQ Mask

◆ CoreDebug_DEMCR_MON_REQ_Msk [5/6]

#define CoreDebug_DEMCR_MON_REQ_Msk   (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

CoreDebug DEMCR: MON_REQ Mask

◆ CoreDebug_DEMCR_MON_REQ_Msk [6/6]

#define CoreDebug_DEMCR_MON_REQ_Msk   (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

CoreDebug DEMCR: MON_REQ Mask

◆ CoreDebug_DEMCR_MON_REQ_Pos [1/6]

#define CoreDebug_DEMCR_MON_REQ_Pos   19U

CoreDebug DEMCR: MON_REQ Position

◆ CoreDebug_DEMCR_MON_REQ_Pos [2/6]

#define CoreDebug_DEMCR_MON_REQ_Pos   19U

CoreDebug DEMCR: MON_REQ Position

◆ CoreDebug_DEMCR_MON_REQ_Pos [3/6]

#define CoreDebug_DEMCR_MON_REQ_Pos   19U

CoreDebug DEMCR: MON_REQ Position

◆ CoreDebug_DEMCR_MON_REQ_Pos [4/6]

#define CoreDebug_DEMCR_MON_REQ_Pos   19U

CoreDebug DEMCR: MON_REQ Position

◆ CoreDebug_DEMCR_MON_REQ_Pos [5/6]

#define CoreDebug_DEMCR_MON_REQ_Pos   19U

CoreDebug DEMCR: MON_REQ Position

◆ CoreDebug_DEMCR_MON_REQ_Pos [6/6]

#define CoreDebug_DEMCR_MON_REQ_Pos   19U

CoreDebug DEMCR: MON_REQ Position

◆ CoreDebug_DEMCR_MON_STEP_Msk [1/6]

#define CoreDebug_DEMCR_MON_STEP_Msk   (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

CoreDebug DEMCR: MON_STEP Mask

◆ CoreDebug_DEMCR_MON_STEP_Msk [2/6]

#define CoreDebug_DEMCR_MON_STEP_Msk   (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

CoreDebug DEMCR: MON_STEP Mask

◆ CoreDebug_DEMCR_MON_STEP_Msk [3/6]

#define CoreDebug_DEMCR_MON_STEP_Msk   (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

CoreDebug DEMCR: MON_STEP Mask

◆ CoreDebug_DEMCR_MON_STEP_Msk [4/6]

#define CoreDebug_DEMCR_MON_STEP_Msk   (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

CoreDebug DEMCR: MON_STEP Mask

◆ CoreDebug_DEMCR_MON_STEP_Msk [5/6]

#define CoreDebug_DEMCR_MON_STEP_Msk   (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

CoreDebug DEMCR: MON_STEP Mask

◆ CoreDebug_DEMCR_MON_STEP_Msk [6/6]

#define CoreDebug_DEMCR_MON_STEP_Msk   (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

CoreDebug DEMCR: MON_STEP Mask

◆ CoreDebug_DEMCR_MON_STEP_Pos [1/6]

#define CoreDebug_DEMCR_MON_STEP_Pos   18U

CoreDebug DEMCR: MON_STEP Position

◆ CoreDebug_DEMCR_MON_STEP_Pos [2/6]

#define CoreDebug_DEMCR_MON_STEP_Pos   18U

CoreDebug DEMCR: MON_STEP Position

◆ CoreDebug_DEMCR_MON_STEP_Pos [3/6]

#define CoreDebug_DEMCR_MON_STEP_Pos   18U

CoreDebug DEMCR: MON_STEP Position

◆ CoreDebug_DEMCR_MON_STEP_Pos [4/6]

#define CoreDebug_DEMCR_MON_STEP_Pos   18U

CoreDebug DEMCR: MON_STEP Position

◆ CoreDebug_DEMCR_MON_STEP_Pos [5/6]

#define CoreDebug_DEMCR_MON_STEP_Pos   18U

CoreDebug DEMCR: MON_STEP Position

◆ CoreDebug_DEMCR_MON_STEP_Pos [6/6]

#define CoreDebug_DEMCR_MON_STEP_Pos   18U

CoreDebug DEMCR: MON_STEP Position

◆ CoreDebug_DEMCR_TRCENA_Msk [1/6]

#define CoreDebug_DEMCR_TRCENA_Msk   (1UL << CoreDebug_DEMCR_TRCENA_Pos)

CoreDebug DEMCR: TRCENA Mask

◆ CoreDebug_DEMCR_TRCENA_Msk [2/6]

#define CoreDebug_DEMCR_TRCENA_Msk   (1UL << CoreDebug_DEMCR_TRCENA_Pos)

CoreDebug DEMCR: TRCENA Mask

◆ CoreDebug_DEMCR_TRCENA_Msk [3/6]

#define CoreDebug_DEMCR_TRCENA_Msk   (1UL << CoreDebug_DEMCR_TRCENA_Pos)

CoreDebug DEMCR: TRCENA Mask

◆ CoreDebug_DEMCR_TRCENA_Msk [4/6]

#define CoreDebug_DEMCR_TRCENA_Msk   (1UL << CoreDebug_DEMCR_TRCENA_Pos)

CoreDebug DEMCR: TRCENA Mask

◆ CoreDebug_DEMCR_TRCENA_Msk [5/6]

#define CoreDebug_DEMCR_TRCENA_Msk   (1UL << CoreDebug_DEMCR_TRCENA_Pos)

CoreDebug DEMCR: TRCENA Mask

◆ CoreDebug_DEMCR_TRCENA_Msk [6/6]

#define CoreDebug_DEMCR_TRCENA_Msk   (1UL << CoreDebug_DEMCR_TRCENA_Pos)

CoreDebug DEMCR: TRCENA Mask

◆ CoreDebug_DEMCR_TRCENA_Pos [1/6]

#define CoreDebug_DEMCR_TRCENA_Pos   24U

CoreDebug DEMCR: TRCENA Position

◆ CoreDebug_DEMCR_TRCENA_Pos [2/6]

#define CoreDebug_DEMCR_TRCENA_Pos   24U

CoreDebug DEMCR: TRCENA Position

◆ CoreDebug_DEMCR_TRCENA_Pos [3/6]

#define CoreDebug_DEMCR_TRCENA_Pos   24U

CoreDebug DEMCR: TRCENA Position

◆ CoreDebug_DEMCR_TRCENA_Pos [4/6]

#define CoreDebug_DEMCR_TRCENA_Pos   24U

CoreDebug DEMCR: TRCENA Position

◆ CoreDebug_DEMCR_TRCENA_Pos [5/6]

#define CoreDebug_DEMCR_TRCENA_Pos   24U

CoreDebug DEMCR: TRCENA Position

◆ CoreDebug_DEMCR_TRCENA_Pos [6/6]

#define CoreDebug_DEMCR_TRCENA_Pos   24U

CoreDebug DEMCR: TRCENA Position

◆ CoreDebug_DEMCR_VC_BUSERR_Msk [1/6]

#define CoreDebug_DEMCR_VC_BUSERR_Msk   (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

CoreDebug DEMCR: VC_BUSERR Mask

◆ CoreDebug_DEMCR_VC_BUSERR_Msk [2/6]

#define CoreDebug_DEMCR_VC_BUSERR_Msk   (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

CoreDebug DEMCR: VC_BUSERR Mask

◆ CoreDebug_DEMCR_VC_BUSERR_Msk [3/6]

#define CoreDebug_DEMCR_VC_BUSERR_Msk   (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

CoreDebug DEMCR: VC_BUSERR Mask

◆ CoreDebug_DEMCR_VC_BUSERR_Msk [4/6]

#define CoreDebug_DEMCR_VC_BUSERR_Msk   (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

CoreDebug DEMCR: VC_BUSERR Mask

◆ CoreDebug_DEMCR_VC_BUSERR_Msk [5/6]

#define CoreDebug_DEMCR_VC_BUSERR_Msk   (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

CoreDebug DEMCR: VC_BUSERR Mask

◆ CoreDebug_DEMCR_VC_BUSERR_Msk [6/6]

#define CoreDebug_DEMCR_VC_BUSERR_Msk   (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

CoreDebug DEMCR: VC_BUSERR Mask

◆ CoreDebug_DEMCR_VC_BUSERR_Pos [1/6]

#define CoreDebug_DEMCR_VC_BUSERR_Pos   8U

CoreDebug DEMCR: VC_BUSERR Position

◆ CoreDebug_DEMCR_VC_BUSERR_Pos [2/6]

#define CoreDebug_DEMCR_VC_BUSERR_Pos   8U

CoreDebug DEMCR: VC_BUSERR Position

◆ CoreDebug_DEMCR_VC_BUSERR_Pos [3/6]

#define CoreDebug_DEMCR_VC_BUSERR_Pos   8U

CoreDebug DEMCR: VC_BUSERR Position

◆ CoreDebug_DEMCR_VC_BUSERR_Pos [4/6]

#define CoreDebug_DEMCR_VC_BUSERR_Pos   8U

CoreDebug DEMCR: VC_BUSERR Position

◆ CoreDebug_DEMCR_VC_BUSERR_Pos [5/6]

#define CoreDebug_DEMCR_VC_BUSERR_Pos   8U

CoreDebug DEMCR: VC_BUSERR Position

◆ CoreDebug_DEMCR_VC_BUSERR_Pos [6/6]

#define CoreDebug_DEMCR_VC_BUSERR_Pos   8U

CoreDebug DEMCR: VC_BUSERR Position

◆ CoreDebug_DEMCR_VC_CHKERR_Msk [1/6]

#define CoreDebug_DEMCR_VC_CHKERR_Msk   (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

CoreDebug DEMCR: VC_CHKERR Mask

◆ CoreDebug_DEMCR_VC_CHKERR_Msk [2/6]

#define CoreDebug_DEMCR_VC_CHKERR_Msk   (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

CoreDebug DEMCR: VC_CHKERR Mask

◆ CoreDebug_DEMCR_VC_CHKERR_Msk [3/6]

#define CoreDebug_DEMCR_VC_CHKERR_Msk   (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

CoreDebug DEMCR: VC_CHKERR Mask

◆ CoreDebug_DEMCR_VC_CHKERR_Msk [4/6]

#define CoreDebug_DEMCR_VC_CHKERR_Msk   (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

CoreDebug DEMCR: VC_CHKERR Mask

◆ CoreDebug_DEMCR_VC_CHKERR_Msk [5/6]

#define CoreDebug_DEMCR_VC_CHKERR_Msk   (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

CoreDebug DEMCR: VC_CHKERR Mask

◆ CoreDebug_DEMCR_VC_CHKERR_Msk [6/6]

#define CoreDebug_DEMCR_VC_CHKERR_Msk   (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

CoreDebug DEMCR: VC_CHKERR Mask

◆ CoreDebug_DEMCR_VC_CHKERR_Pos [1/6]

#define CoreDebug_DEMCR_VC_CHKERR_Pos   6U

CoreDebug DEMCR: VC_CHKERR Position

◆ CoreDebug_DEMCR_VC_CHKERR_Pos [2/6]

#define CoreDebug_DEMCR_VC_CHKERR_Pos   6U

CoreDebug DEMCR: VC_CHKERR Position

◆ CoreDebug_DEMCR_VC_CHKERR_Pos [3/6]

#define CoreDebug_DEMCR_VC_CHKERR_Pos   6U

CoreDebug DEMCR: VC_CHKERR Position

◆ CoreDebug_DEMCR_VC_CHKERR_Pos [4/6]

#define CoreDebug_DEMCR_VC_CHKERR_Pos   6U

CoreDebug DEMCR: VC_CHKERR Position

◆ CoreDebug_DEMCR_VC_CHKERR_Pos [5/6]

#define CoreDebug_DEMCR_VC_CHKERR_Pos   6U

CoreDebug DEMCR: VC_CHKERR Position

◆ CoreDebug_DEMCR_VC_CHKERR_Pos [6/6]

#define CoreDebug_DEMCR_VC_CHKERR_Pos   6U

CoreDebug DEMCR: VC_CHKERR Position

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [1/8]

#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [2/8]

#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [3/8]

#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [4/8]

#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [5/8]

#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [6/8]

#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [7/8]

#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [8/8]

#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [1/8]

#define CoreDebug_DEMCR_VC_CORERESET_Pos   0U

CoreDebug DEMCR: VC_CORERESET Position

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [2/8]

#define CoreDebug_DEMCR_VC_CORERESET_Pos   0U

CoreDebug DEMCR: VC_CORERESET Position

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [3/8]

#define CoreDebug_DEMCR_VC_CORERESET_Pos   0U

CoreDebug DEMCR: VC_CORERESET Position

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [4/8]

#define CoreDebug_DEMCR_VC_CORERESET_Pos   0U

CoreDebug DEMCR: VC_CORERESET Position

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [5/8]

#define CoreDebug_DEMCR_VC_CORERESET_Pos   0U

CoreDebug DEMCR: VC_CORERESET Position

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [6/8]

#define CoreDebug_DEMCR_VC_CORERESET_Pos   0U

CoreDebug DEMCR: VC_CORERESET Position

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [7/8]

#define CoreDebug_DEMCR_VC_CORERESET_Pos   0U

CoreDebug DEMCR: VC_CORERESET Position

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [8/8]

#define CoreDebug_DEMCR_VC_CORERESET_Pos   0U

CoreDebug DEMCR: VC_CORERESET Position

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [1/8]

#define CoreDebug_DEMCR_VC_HARDERR_Msk   (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [2/8]

#define CoreDebug_DEMCR_VC_HARDERR_Msk   (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [3/8]

#define CoreDebug_DEMCR_VC_HARDERR_Msk   (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [4/8]

#define CoreDebug_DEMCR_VC_HARDERR_Msk   (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [5/8]

#define CoreDebug_DEMCR_VC_HARDERR_Msk   (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [6/8]

#define CoreDebug_DEMCR_VC_HARDERR_Msk   (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [7/8]

#define CoreDebug_DEMCR_VC_HARDERR_Msk   (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [8/8]

#define CoreDebug_DEMCR_VC_HARDERR_Msk   (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [1/8]

#define CoreDebug_DEMCR_VC_HARDERR_Pos   10U

CoreDebug DEMCR: VC_HARDERR Position

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [2/8]

#define CoreDebug_DEMCR_VC_HARDERR_Pos   10U

CoreDebug DEMCR: VC_HARDERR Position

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [3/8]

#define CoreDebug_DEMCR_VC_HARDERR_Pos   10U

CoreDebug DEMCR: VC_HARDERR Position

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [4/8]

#define CoreDebug_DEMCR_VC_HARDERR_Pos   10U

CoreDebug DEMCR: VC_HARDERR Position

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [5/8]

#define CoreDebug_DEMCR_VC_HARDERR_Pos   10U

CoreDebug DEMCR: VC_HARDERR Position

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [6/8]

#define CoreDebug_DEMCR_VC_HARDERR_Pos   10U

CoreDebug DEMCR: VC_HARDERR Position

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [7/8]

#define CoreDebug_DEMCR_VC_HARDERR_Pos   10U

CoreDebug DEMCR: VC_HARDERR Position

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [8/8]

#define CoreDebug_DEMCR_VC_HARDERR_Pos   10U

CoreDebug DEMCR: VC_HARDERR Position

◆ CoreDebug_DEMCR_VC_INTERR_Msk [1/6]

#define CoreDebug_DEMCR_VC_INTERR_Msk   (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

CoreDebug DEMCR: VC_INTERR Mask

◆ CoreDebug_DEMCR_VC_INTERR_Msk [2/6]

#define CoreDebug_DEMCR_VC_INTERR_Msk   (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

CoreDebug DEMCR: VC_INTERR Mask

◆ CoreDebug_DEMCR_VC_INTERR_Msk [3/6]

#define CoreDebug_DEMCR_VC_INTERR_Msk   (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

CoreDebug DEMCR: VC_INTERR Mask

◆ CoreDebug_DEMCR_VC_INTERR_Msk [4/6]

#define CoreDebug_DEMCR_VC_INTERR_Msk   (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

CoreDebug DEMCR: VC_INTERR Mask

◆ CoreDebug_DEMCR_VC_INTERR_Msk [5/6]

#define CoreDebug_DEMCR_VC_INTERR_Msk   (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

CoreDebug DEMCR: VC_INTERR Mask

◆ CoreDebug_DEMCR_VC_INTERR_Msk [6/6]

#define CoreDebug_DEMCR_VC_INTERR_Msk   (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

CoreDebug DEMCR: VC_INTERR Mask

◆ CoreDebug_DEMCR_VC_INTERR_Pos [1/6]

#define CoreDebug_DEMCR_VC_INTERR_Pos   9U

CoreDebug DEMCR: VC_INTERR Position

◆ CoreDebug_DEMCR_VC_INTERR_Pos [2/6]

#define CoreDebug_DEMCR_VC_INTERR_Pos   9U

CoreDebug DEMCR: VC_INTERR Position

◆ CoreDebug_DEMCR_VC_INTERR_Pos [3/6]

#define CoreDebug_DEMCR_VC_INTERR_Pos   9U

CoreDebug DEMCR: VC_INTERR Position

◆ CoreDebug_DEMCR_VC_INTERR_Pos [4/6]

#define CoreDebug_DEMCR_VC_INTERR_Pos   9U

CoreDebug DEMCR: VC_INTERR Position

◆ CoreDebug_DEMCR_VC_INTERR_Pos [5/6]

#define CoreDebug_DEMCR_VC_INTERR_Pos   9U

CoreDebug DEMCR: VC_INTERR Position

◆ CoreDebug_DEMCR_VC_INTERR_Pos [6/6]

#define CoreDebug_DEMCR_VC_INTERR_Pos   9U

CoreDebug DEMCR: VC_INTERR Position

◆ CoreDebug_DEMCR_VC_MMERR_Msk [1/6]

#define CoreDebug_DEMCR_VC_MMERR_Msk   (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

CoreDebug DEMCR: VC_MMERR Mask

◆ CoreDebug_DEMCR_VC_MMERR_Msk [2/6]

#define CoreDebug_DEMCR_VC_MMERR_Msk   (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

CoreDebug DEMCR: VC_MMERR Mask

◆ CoreDebug_DEMCR_VC_MMERR_Msk [3/6]

#define CoreDebug_DEMCR_VC_MMERR_Msk   (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

CoreDebug DEMCR: VC_MMERR Mask

◆ CoreDebug_DEMCR_VC_MMERR_Msk [4/6]

#define CoreDebug_DEMCR_VC_MMERR_Msk   (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

CoreDebug DEMCR: VC_MMERR Mask

◆ CoreDebug_DEMCR_VC_MMERR_Msk [5/6]

#define CoreDebug_DEMCR_VC_MMERR_Msk   (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

CoreDebug DEMCR: VC_MMERR Mask

◆ CoreDebug_DEMCR_VC_MMERR_Msk [6/6]

#define CoreDebug_DEMCR_VC_MMERR_Msk   (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

CoreDebug DEMCR: VC_MMERR Mask

◆ CoreDebug_DEMCR_VC_MMERR_Pos [1/6]

#define CoreDebug_DEMCR_VC_MMERR_Pos   4U

CoreDebug DEMCR: VC_MMERR Position

◆ CoreDebug_DEMCR_VC_MMERR_Pos [2/6]

#define CoreDebug_DEMCR_VC_MMERR_Pos   4U

CoreDebug DEMCR: VC_MMERR Position

◆ CoreDebug_DEMCR_VC_MMERR_Pos [3/6]

#define CoreDebug_DEMCR_VC_MMERR_Pos   4U

CoreDebug DEMCR: VC_MMERR Position

◆ CoreDebug_DEMCR_VC_MMERR_Pos [4/6]

#define CoreDebug_DEMCR_VC_MMERR_Pos   4U

CoreDebug DEMCR: VC_MMERR Position

◆ CoreDebug_DEMCR_VC_MMERR_Pos [5/6]

#define CoreDebug_DEMCR_VC_MMERR_Pos   4U

CoreDebug DEMCR: VC_MMERR Position

◆ CoreDebug_DEMCR_VC_MMERR_Pos [6/6]

#define CoreDebug_DEMCR_VC_MMERR_Pos   4U

CoreDebug DEMCR: VC_MMERR Position

◆ CoreDebug_DEMCR_VC_NOCPERR_Msk [1/6]

#define CoreDebug_DEMCR_VC_NOCPERR_Msk   (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

CoreDebug DEMCR: VC_NOCPERR Mask

◆ CoreDebug_DEMCR_VC_NOCPERR_Msk [2/6]

#define CoreDebug_DEMCR_VC_NOCPERR_Msk   (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

CoreDebug DEMCR: VC_NOCPERR Mask

◆ CoreDebug_DEMCR_VC_NOCPERR_Msk [3/6]

#define CoreDebug_DEMCR_VC_NOCPERR_Msk   (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

CoreDebug DEMCR: VC_NOCPERR Mask

◆ CoreDebug_DEMCR_VC_NOCPERR_Msk [4/6]

#define CoreDebug_DEMCR_VC_NOCPERR_Msk   (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

CoreDebug DEMCR: VC_NOCPERR Mask

◆ CoreDebug_DEMCR_VC_NOCPERR_Msk [5/6]

#define CoreDebug_DEMCR_VC_NOCPERR_Msk   (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

CoreDebug DEMCR: VC_NOCPERR Mask

◆ CoreDebug_DEMCR_VC_NOCPERR_Msk [6/6]

#define CoreDebug_DEMCR_VC_NOCPERR_Msk   (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

CoreDebug DEMCR: VC_NOCPERR Mask

◆ CoreDebug_DEMCR_VC_NOCPERR_Pos [1/6]

#define CoreDebug_DEMCR_VC_NOCPERR_Pos   5U

CoreDebug DEMCR: VC_NOCPERR Position

◆ CoreDebug_DEMCR_VC_NOCPERR_Pos [2/6]

#define CoreDebug_DEMCR_VC_NOCPERR_Pos   5U

CoreDebug DEMCR: VC_NOCPERR Position

◆ CoreDebug_DEMCR_VC_NOCPERR_Pos [3/6]

#define CoreDebug_DEMCR_VC_NOCPERR_Pos   5U

CoreDebug DEMCR: VC_NOCPERR Position

◆ CoreDebug_DEMCR_VC_NOCPERR_Pos [4/6]

#define CoreDebug_DEMCR_VC_NOCPERR_Pos   5U

CoreDebug DEMCR: VC_NOCPERR Position

◆ CoreDebug_DEMCR_VC_NOCPERR_Pos [5/6]

#define CoreDebug_DEMCR_VC_NOCPERR_Pos   5U

CoreDebug DEMCR: VC_NOCPERR Position

◆ CoreDebug_DEMCR_VC_NOCPERR_Pos [6/6]

#define CoreDebug_DEMCR_VC_NOCPERR_Pos   5U

CoreDebug DEMCR: VC_NOCPERR Position

◆ CoreDebug_DEMCR_VC_STATERR_Msk [1/6]

#define CoreDebug_DEMCR_VC_STATERR_Msk   (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

CoreDebug DEMCR: VC_STATERR Mask

◆ CoreDebug_DEMCR_VC_STATERR_Msk [2/6]

#define CoreDebug_DEMCR_VC_STATERR_Msk   (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

CoreDebug DEMCR: VC_STATERR Mask

◆ CoreDebug_DEMCR_VC_STATERR_Msk [3/6]

#define CoreDebug_DEMCR_VC_STATERR_Msk   (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

CoreDebug DEMCR: VC_STATERR Mask

◆ CoreDebug_DEMCR_VC_STATERR_Msk [4/6]

#define CoreDebug_DEMCR_VC_STATERR_Msk   (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

CoreDebug DEMCR: VC_STATERR Mask

◆ CoreDebug_DEMCR_VC_STATERR_Msk [5/6]

#define CoreDebug_DEMCR_VC_STATERR_Msk   (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

CoreDebug DEMCR: VC_STATERR Mask

◆ CoreDebug_DEMCR_VC_STATERR_Msk [6/6]

#define CoreDebug_DEMCR_VC_STATERR_Msk   (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

CoreDebug DEMCR: VC_STATERR Mask

◆ CoreDebug_DEMCR_VC_STATERR_Pos [1/6]

#define CoreDebug_DEMCR_VC_STATERR_Pos   7U

CoreDebug DEMCR: VC_STATERR Position

◆ CoreDebug_DEMCR_VC_STATERR_Pos [2/6]

#define CoreDebug_DEMCR_VC_STATERR_Pos   7U

CoreDebug DEMCR: VC_STATERR Position

◆ CoreDebug_DEMCR_VC_STATERR_Pos [3/6]

#define CoreDebug_DEMCR_VC_STATERR_Pos   7U

CoreDebug DEMCR: VC_STATERR Position

◆ CoreDebug_DEMCR_VC_STATERR_Pos [4/6]

#define CoreDebug_DEMCR_VC_STATERR_Pos   7U

CoreDebug DEMCR: VC_STATERR Position

◆ CoreDebug_DEMCR_VC_STATERR_Pos [5/6]

#define CoreDebug_DEMCR_VC_STATERR_Pos   7U

CoreDebug DEMCR: VC_STATERR Position

◆ CoreDebug_DEMCR_VC_STATERR_Pos [6/6]

#define CoreDebug_DEMCR_VC_STATERR_Pos   7U

CoreDebug DEMCR: VC_STATERR Position

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [1/8]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk   (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [2/8]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk   (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [3/8]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk   (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [4/8]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk   (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [5/8]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk   (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [6/8]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk   (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [7/8]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk   (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [8/8]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk   (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [1/8]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos   0U

CoreDebug DHCSR: C_DEBUGEN Position

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [2/8]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos   0U

CoreDebug DHCSR: C_DEBUGEN Position

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [3/8]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos   0U

CoreDebug DHCSR: C_DEBUGEN Position

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [4/8]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos   0U

CoreDebug DHCSR: C_DEBUGEN Position

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [5/8]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos   0U

CoreDebug DHCSR: C_DEBUGEN Position

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [6/8]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos   0U

CoreDebug DHCSR: C_DEBUGEN Position

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [7/8]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos   0U

CoreDebug DHCSR: C_DEBUGEN Position

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [8/8]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos   0U

CoreDebug DHCSR: C_DEBUGEN Position

◆ CoreDebug_DHCSR_C_HALT_Msk [1/8]

#define CoreDebug_DHCSR_C_HALT_Msk   (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

◆ CoreDebug_DHCSR_C_HALT_Msk [2/8]

#define CoreDebug_DHCSR_C_HALT_Msk   (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

◆ CoreDebug_DHCSR_C_HALT_Msk [3/8]

#define CoreDebug_DHCSR_C_HALT_Msk   (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

◆ CoreDebug_DHCSR_C_HALT_Msk [4/8]

#define CoreDebug_DHCSR_C_HALT_Msk   (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

◆ CoreDebug_DHCSR_C_HALT_Msk [5/8]

#define CoreDebug_DHCSR_C_HALT_Msk   (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

◆ CoreDebug_DHCSR_C_HALT_Msk [6/8]

#define CoreDebug_DHCSR_C_HALT_Msk   (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

◆ CoreDebug_DHCSR_C_HALT_Msk [7/8]

#define CoreDebug_DHCSR_C_HALT_Msk   (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

◆ CoreDebug_DHCSR_C_HALT_Msk [8/8]

#define CoreDebug_DHCSR_C_HALT_Msk   (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

◆ CoreDebug_DHCSR_C_HALT_Pos [1/8]

#define CoreDebug_DHCSR_C_HALT_Pos   1U

CoreDebug DHCSR: C_HALT Position

◆ CoreDebug_DHCSR_C_HALT_Pos [2/8]

#define CoreDebug_DHCSR_C_HALT_Pos   1U

CoreDebug DHCSR: C_HALT Position

◆ CoreDebug_DHCSR_C_HALT_Pos [3/8]

#define CoreDebug_DHCSR_C_HALT_Pos   1U

CoreDebug DHCSR: C_HALT Position

◆ CoreDebug_DHCSR_C_HALT_Pos [4/8]

#define CoreDebug_DHCSR_C_HALT_Pos   1U

CoreDebug DHCSR: C_HALT Position

◆ CoreDebug_DHCSR_C_HALT_Pos [5/8]

#define CoreDebug_DHCSR_C_HALT_Pos   1U

CoreDebug DHCSR: C_HALT Position

◆ CoreDebug_DHCSR_C_HALT_Pos [6/8]

#define CoreDebug_DHCSR_C_HALT_Pos   1U

CoreDebug DHCSR: C_HALT Position

◆ CoreDebug_DHCSR_C_HALT_Pos [7/8]

#define CoreDebug_DHCSR_C_HALT_Pos   1U

CoreDebug DHCSR: C_HALT Position

◆ CoreDebug_DHCSR_C_HALT_Pos [8/8]

#define CoreDebug_DHCSR_C_HALT_Pos   1U

CoreDebug DHCSR: C_HALT Position

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [1/8]

#define CoreDebug_DHCSR_C_MASKINTS_Msk   (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [2/8]

#define CoreDebug_DHCSR_C_MASKINTS_Msk   (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [3/8]

#define CoreDebug_DHCSR_C_MASKINTS_Msk   (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [4/8]

#define CoreDebug_DHCSR_C_MASKINTS_Msk   (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [5/8]

#define CoreDebug_DHCSR_C_MASKINTS_Msk   (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [6/8]

#define CoreDebug_DHCSR_C_MASKINTS_Msk   (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [7/8]

#define CoreDebug_DHCSR_C_MASKINTS_Msk   (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [8/8]

#define CoreDebug_DHCSR_C_MASKINTS_Msk   (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [1/8]

#define CoreDebug_DHCSR_C_MASKINTS_Pos   3U

CoreDebug DHCSR: C_MASKINTS Position

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [2/8]

#define CoreDebug_DHCSR_C_MASKINTS_Pos   3U

CoreDebug DHCSR: C_MASKINTS Position

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [3/8]

#define CoreDebug_DHCSR_C_MASKINTS_Pos   3U

CoreDebug DHCSR: C_MASKINTS Position

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [4/8]

#define CoreDebug_DHCSR_C_MASKINTS_Pos   3U

CoreDebug DHCSR: C_MASKINTS Position

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [5/8]

#define CoreDebug_DHCSR_C_MASKINTS_Pos   3U

CoreDebug DHCSR: C_MASKINTS Position

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [6/8]

#define CoreDebug_DHCSR_C_MASKINTS_Pos   3U

CoreDebug DHCSR: C_MASKINTS Position

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [7/8]

#define CoreDebug_DHCSR_C_MASKINTS_Pos   3U

CoreDebug DHCSR: C_MASKINTS Position

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [8/8]

#define CoreDebug_DHCSR_C_MASKINTS_Pos   3U

CoreDebug DHCSR: C_MASKINTS Position

◆ CoreDebug_DHCSR_C_SNAPSTALL_Msk [1/6]

#define CoreDebug_DHCSR_C_SNAPSTALL_Msk   (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

CoreDebug DHCSR: C_SNAPSTALL Mask

◆ CoreDebug_DHCSR_C_SNAPSTALL_Msk [2/6]

#define CoreDebug_DHCSR_C_SNAPSTALL_Msk   (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

CoreDebug DHCSR: C_SNAPSTALL Mask

◆ CoreDebug_DHCSR_C_SNAPSTALL_Msk [3/6]

#define CoreDebug_DHCSR_C_SNAPSTALL_Msk   (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

CoreDebug DHCSR: C_SNAPSTALL Mask

◆ CoreDebug_DHCSR_C_SNAPSTALL_Msk [4/6]

#define CoreDebug_DHCSR_C_SNAPSTALL_Msk   (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

CoreDebug DHCSR: C_SNAPSTALL Mask

◆ CoreDebug_DHCSR_C_SNAPSTALL_Msk [5/6]

#define CoreDebug_DHCSR_C_SNAPSTALL_Msk   (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

CoreDebug DHCSR: C_SNAPSTALL Mask

◆ CoreDebug_DHCSR_C_SNAPSTALL_Msk [6/6]

#define CoreDebug_DHCSR_C_SNAPSTALL_Msk   (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

CoreDebug DHCSR: C_SNAPSTALL Mask

◆ CoreDebug_DHCSR_C_SNAPSTALL_Pos [1/6]

#define CoreDebug_DHCSR_C_SNAPSTALL_Pos   5U

CoreDebug DHCSR: C_SNAPSTALL Position

◆ CoreDebug_DHCSR_C_SNAPSTALL_Pos [2/6]

#define CoreDebug_DHCSR_C_SNAPSTALL_Pos   5U

CoreDebug DHCSR: C_SNAPSTALL Position

◆ CoreDebug_DHCSR_C_SNAPSTALL_Pos [3/6]

#define CoreDebug_DHCSR_C_SNAPSTALL_Pos   5U

CoreDebug DHCSR: C_SNAPSTALL Position

◆ CoreDebug_DHCSR_C_SNAPSTALL_Pos [4/6]

#define CoreDebug_DHCSR_C_SNAPSTALL_Pos   5U

CoreDebug DHCSR: C_SNAPSTALL Position

◆ CoreDebug_DHCSR_C_SNAPSTALL_Pos [5/6]

#define CoreDebug_DHCSR_C_SNAPSTALL_Pos   5U

CoreDebug DHCSR: C_SNAPSTALL Position

◆ CoreDebug_DHCSR_C_SNAPSTALL_Pos [6/6]

#define CoreDebug_DHCSR_C_SNAPSTALL_Pos   5U

CoreDebug DHCSR: C_SNAPSTALL Position

◆ CoreDebug_DHCSR_C_STEP_Msk [1/8]

#define CoreDebug_DHCSR_C_STEP_Msk   (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

◆ CoreDebug_DHCSR_C_STEP_Msk [2/8]

#define CoreDebug_DHCSR_C_STEP_Msk   (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

◆ CoreDebug_DHCSR_C_STEP_Msk [3/8]

#define CoreDebug_DHCSR_C_STEP_Msk   (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

◆ CoreDebug_DHCSR_C_STEP_Msk [4/8]

#define CoreDebug_DHCSR_C_STEP_Msk   (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

◆ CoreDebug_DHCSR_C_STEP_Msk [5/8]

#define CoreDebug_DHCSR_C_STEP_Msk   (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

◆ CoreDebug_DHCSR_C_STEP_Msk [6/8]

#define CoreDebug_DHCSR_C_STEP_Msk   (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

◆ CoreDebug_DHCSR_C_STEP_Msk [7/8]

#define CoreDebug_DHCSR_C_STEP_Msk   (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

◆ CoreDebug_DHCSR_C_STEP_Msk [8/8]

#define CoreDebug_DHCSR_C_STEP_Msk   (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

◆ CoreDebug_DHCSR_C_STEP_Pos [1/8]

#define CoreDebug_DHCSR_C_STEP_Pos   2U

CoreDebug DHCSR: C_STEP Position

◆ CoreDebug_DHCSR_C_STEP_Pos [2/8]

#define CoreDebug_DHCSR_C_STEP_Pos   2U

CoreDebug DHCSR: C_STEP Position

◆ CoreDebug_DHCSR_C_STEP_Pos [3/8]

#define CoreDebug_DHCSR_C_STEP_Pos   2U

CoreDebug DHCSR: C_STEP Position

◆ CoreDebug_DHCSR_C_STEP_Pos [4/8]

#define CoreDebug_DHCSR_C_STEP_Pos   2U

CoreDebug DHCSR: C_STEP Position

◆ CoreDebug_DHCSR_C_STEP_Pos [5/8]

#define CoreDebug_DHCSR_C_STEP_Pos   2U

CoreDebug DHCSR: C_STEP Position

◆ CoreDebug_DHCSR_C_STEP_Pos [6/8]

#define CoreDebug_DHCSR_C_STEP_Pos   2U

CoreDebug DHCSR: C_STEP Position

◆ CoreDebug_DHCSR_C_STEP_Pos [7/8]

#define CoreDebug_DHCSR_C_STEP_Pos   2U

CoreDebug DHCSR: C_STEP Position

◆ CoreDebug_DHCSR_C_STEP_Pos [8/8]

#define CoreDebug_DHCSR_C_STEP_Pos   2U

CoreDebug DHCSR: C_STEP Position

◆ CoreDebug_DHCSR_DBGKEY_Msk [1/8]

#define CoreDebug_DHCSR_DBGKEY_Msk   (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

◆ CoreDebug_DHCSR_DBGKEY_Msk [2/8]

#define CoreDebug_DHCSR_DBGKEY_Msk   (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

◆ CoreDebug_DHCSR_DBGKEY_Msk [3/8]

#define CoreDebug_DHCSR_DBGKEY_Msk   (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

◆ CoreDebug_DHCSR_DBGKEY_Msk [4/8]

#define CoreDebug_DHCSR_DBGKEY_Msk   (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

◆ CoreDebug_DHCSR_DBGKEY_Msk [5/8]

#define CoreDebug_DHCSR_DBGKEY_Msk   (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

◆ CoreDebug_DHCSR_DBGKEY_Msk [6/8]

#define CoreDebug_DHCSR_DBGKEY_Msk   (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

◆ CoreDebug_DHCSR_DBGKEY_Msk [7/8]

#define CoreDebug_DHCSR_DBGKEY_Msk   (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

◆ CoreDebug_DHCSR_DBGKEY_Msk [8/8]

#define CoreDebug_DHCSR_DBGKEY_Msk   (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

◆ CoreDebug_DHCSR_DBGKEY_Pos [1/8]

#define CoreDebug_DHCSR_DBGKEY_Pos   16U

CoreDebug DHCSR: DBGKEY Position

◆ CoreDebug_DHCSR_DBGKEY_Pos [2/8]

#define CoreDebug_DHCSR_DBGKEY_Pos   16U

CoreDebug DHCSR: DBGKEY Position

◆ CoreDebug_DHCSR_DBGKEY_Pos [3/8]

#define CoreDebug_DHCSR_DBGKEY_Pos   16U

CoreDebug DHCSR: DBGKEY Position

◆ CoreDebug_DHCSR_DBGKEY_Pos [4/8]

#define CoreDebug_DHCSR_DBGKEY_Pos   16U

CoreDebug DHCSR: DBGKEY Position

◆ CoreDebug_DHCSR_DBGKEY_Pos [5/8]

#define CoreDebug_DHCSR_DBGKEY_Pos   16U

CoreDebug DHCSR: DBGKEY Position

◆ CoreDebug_DHCSR_DBGKEY_Pos [6/8]

#define CoreDebug_DHCSR_DBGKEY_Pos   16U

CoreDebug DHCSR: DBGKEY Position

◆ CoreDebug_DHCSR_DBGKEY_Pos [7/8]

#define CoreDebug_DHCSR_DBGKEY_Pos   16U

CoreDebug DHCSR: DBGKEY Position

◆ CoreDebug_DHCSR_DBGKEY_Pos [8/8]

#define CoreDebug_DHCSR_DBGKEY_Pos   16U

CoreDebug DHCSR: DBGKEY Position

◆ CoreDebug_DHCSR_S_HALT_Msk [1/8]

#define CoreDebug_DHCSR_S_HALT_Msk   (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

◆ CoreDebug_DHCSR_S_HALT_Msk [2/8]

#define CoreDebug_DHCSR_S_HALT_Msk   (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

◆ CoreDebug_DHCSR_S_HALT_Msk [3/8]

#define CoreDebug_DHCSR_S_HALT_Msk   (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

◆ CoreDebug_DHCSR_S_HALT_Msk [4/8]

#define CoreDebug_DHCSR_S_HALT_Msk   (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

◆ CoreDebug_DHCSR_S_HALT_Msk [5/8]

#define CoreDebug_DHCSR_S_HALT_Msk   (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

◆ CoreDebug_DHCSR_S_HALT_Msk [6/8]

#define CoreDebug_DHCSR_S_HALT_Msk   (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

◆ CoreDebug_DHCSR_S_HALT_Msk [7/8]

#define CoreDebug_DHCSR_S_HALT_Msk   (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

◆ CoreDebug_DHCSR_S_HALT_Msk [8/8]

#define CoreDebug_DHCSR_S_HALT_Msk   (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

◆ CoreDebug_DHCSR_S_HALT_Pos [1/8]

#define CoreDebug_DHCSR_S_HALT_Pos   17U

CoreDebug DHCSR: S_HALT Position

◆ CoreDebug_DHCSR_S_HALT_Pos [2/8]

#define CoreDebug_DHCSR_S_HALT_Pos   17U

CoreDebug DHCSR: S_HALT Position

◆ CoreDebug_DHCSR_S_HALT_Pos [3/8]

#define CoreDebug_DHCSR_S_HALT_Pos   17U

CoreDebug DHCSR: S_HALT Position

◆ CoreDebug_DHCSR_S_HALT_Pos [4/8]

#define CoreDebug_DHCSR_S_HALT_Pos   17U

CoreDebug DHCSR: S_HALT Position

◆ CoreDebug_DHCSR_S_HALT_Pos [5/8]

#define CoreDebug_DHCSR_S_HALT_Pos   17U

CoreDebug DHCSR: S_HALT Position

◆ CoreDebug_DHCSR_S_HALT_Pos [6/8]

#define CoreDebug_DHCSR_S_HALT_Pos   17U

CoreDebug DHCSR: S_HALT Position

◆ CoreDebug_DHCSR_S_HALT_Pos [7/8]

#define CoreDebug_DHCSR_S_HALT_Pos   17U

CoreDebug DHCSR: S_HALT Position

◆ CoreDebug_DHCSR_S_HALT_Pos [8/8]

#define CoreDebug_DHCSR_S_HALT_Pos   17U

CoreDebug DHCSR: S_HALT Position

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [1/8]

#define CoreDebug_DHCSR_S_LOCKUP_Msk   (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [2/8]

#define CoreDebug_DHCSR_S_LOCKUP_Msk   (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [3/8]

#define CoreDebug_DHCSR_S_LOCKUP_Msk   (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [4/8]

#define CoreDebug_DHCSR_S_LOCKUP_Msk   (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [5/8]

#define CoreDebug_DHCSR_S_LOCKUP_Msk   (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [6/8]

#define CoreDebug_DHCSR_S_LOCKUP_Msk   (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [7/8]

#define CoreDebug_DHCSR_S_LOCKUP_Msk   (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [8/8]

#define CoreDebug_DHCSR_S_LOCKUP_Msk   (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [1/8]

#define CoreDebug_DHCSR_S_LOCKUP_Pos   19U

CoreDebug DHCSR: S_LOCKUP Position

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [2/8]

#define CoreDebug_DHCSR_S_LOCKUP_Pos   19U

CoreDebug DHCSR: S_LOCKUP Position

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [3/8]

#define CoreDebug_DHCSR_S_LOCKUP_Pos   19U

CoreDebug DHCSR: S_LOCKUP Position

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [4/8]

#define CoreDebug_DHCSR_S_LOCKUP_Pos   19U

CoreDebug DHCSR: S_LOCKUP Position

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [5/8]

#define CoreDebug_DHCSR_S_LOCKUP_Pos   19U

CoreDebug DHCSR: S_LOCKUP Position

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [6/8]

#define CoreDebug_DHCSR_S_LOCKUP_Pos   19U

CoreDebug DHCSR: S_LOCKUP Position

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [7/8]

#define CoreDebug_DHCSR_S_LOCKUP_Pos   19U

CoreDebug DHCSR: S_LOCKUP Position

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [8/8]

#define CoreDebug_DHCSR_S_LOCKUP_Pos   19U

CoreDebug DHCSR: S_LOCKUP Position

◆ CoreDebug_DHCSR_S_REGRDY_Msk [1/8]

#define CoreDebug_DHCSR_S_REGRDY_Msk   (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

◆ CoreDebug_DHCSR_S_REGRDY_Msk [2/8]

#define CoreDebug_DHCSR_S_REGRDY_Msk   (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

◆ CoreDebug_DHCSR_S_REGRDY_Msk [3/8]

#define CoreDebug_DHCSR_S_REGRDY_Msk   (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

◆ CoreDebug_DHCSR_S_REGRDY_Msk [4/8]

#define CoreDebug_DHCSR_S_REGRDY_Msk   (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

◆ CoreDebug_DHCSR_S_REGRDY_Msk [5/8]

#define CoreDebug_DHCSR_S_REGRDY_Msk   (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

◆ CoreDebug_DHCSR_S_REGRDY_Msk [6/8]

#define CoreDebug_DHCSR_S_REGRDY_Msk   (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

◆ CoreDebug_DHCSR_S_REGRDY_Msk [7/8]

#define CoreDebug_DHCSR_S_REGRDY_Msk   (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

◆ CoreDebug_DHCSR_S_REGRDY_Msk [8/8]

#define CoreDebug_DHCSR_S_REGRDY_Msk   (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

◆ CoreDebug_DHCSR_S_REGRDY_Pos [1/8]

#define CoreDebug_DHCSR_S_REGRDY_Pos   16U

CoreDebug DHCSR: S_REGRDY Position

◆ CoreDebug_DHCSR_S_REGRDY_Pos [2/8]

#define CoreDebug_DHCSR_S_REGRDY_Pos   16U

CoreDebug DHCSR: S_REGRDY Position

◆ CoreDebug_DHCSR_S_REGRDY_Pos [3/8]

#define CoreDebug_DHCSR_S_REGRDY_Pos   16U

CoreDebug DHCSR: S_REGRDY Position

◆ CoreDebug_DHCSR_S_REGRDY_Pos [4/8]

#define CoreDebug_DHCSR_S_REGRDY_Pos   16U

CoreDebug DHCSR: S_REGRDY Position

◆ CoreDebug_DHCSR_S_REGRDY_Pos [5/8]

#define CoreDebug_DHCSR_S_REGRDY_Pos   16U

CoreDebug DHCSR: S_REGRDY Position

◆ CoreDebug_DHCSR_S_REGRDY_Pos [6/8]

#define CoreDebug_DHCSR_S_REGRDY_Pos   16U

CoreDebug DHCSR: S_REGRDY Position

◆ CoreDebug_DHCSR_S_REGRDY_Pos [7/8]

#define CoreDebug_DHCSR_S_REGRDY_Pos   16U

CoreDebug DHCSR: S_REGRDY Position

◆ CoreDebug_DHCSR_S_REGRDY_Pos [8/8]

#define CoreDebug_DHCSR_S_REGRDY_Pos   16U

CoreDebug DHCSR: S_REGRDY Position

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [1/8]

#define CoreDebug_DHCSR_S_RESET_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [2/8]

#define CoreDebug_DHCSR_S_RESET_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [3/8]

#define CoreDebug_DHCSR_S_RESET_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [4/8]

#define CoreDebug_DHCSR_S_RESET_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [5/8]

#define CoreDebug_DHCSR_S_RESET_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [6/8]

#define CoreDebug_DHCSR_S_RESET_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [7/8]

#define CoreDebug_DHCSR_S_RESET_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [8/8]

#define CoreDebug_DHCSR_S_RESET_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [1/8]

#define CoreDebug_DHCSR_S_RESET_ST_Pos   25U

CoreDebug DHCSR: S_RESET_ST Position

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [2/8]

#define CoreDebug_DHCSR_S_RESET_ST_Pos   25U

CoreDebug DHCSR: S_RESET_ST Position

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [3/8]

#define CoreDebug_DHCSR_S_RESET_ST_Pos   25U

CoreDebug DHCSR: S_RESET_ST Position

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [4/8]

#define CoreDebug_DHCSR_S_RESET_ST_Pos   25U

CoreDebug DHCSR: S_RESET_ST Position

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [5/8]

#define CoreDebug_DHCSR_S_RESET_ST_Pos   25U

CoreDebug DHCSR: S_RESET_ST Position

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [6/8]

#define CoreDebug_DHCSR_S_RESET_ST_Pos   25U

CoreDebug DHCSR: S_RESET_ST Position

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [7/8]

#define CoreDebug_DHCSR_S_RESET_ST_Pos   25U

CoreDebug DHCSR: S_RESET_ST Position

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [8/8]

#define CoreDebug_DHCSR_S_RESET_ST_Pos   25U

CoreDebug DHCSR: S_RESET_ST Position

◆ CoreDebug_DHCSR_S_RESTART_ST_Msk

#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)

CoreDebug DHCSR: S_RESTART_ST Mask

◆ CoreDebug_DHCSR_S_RESTART_ST_Pos

#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U

CoreDebug DHCSR: S_RESTART_ST Position

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [1/8]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk   (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [2/8]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk   (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [3/8]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk   (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [4/8]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk   (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [5/8]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk   (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [6/8]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk   (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [7/8]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk   (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [8/8]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk   (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

◆ CoreDebug_DHCSR_S_RETIRE_ST_Pos [1/8]

#define CoreDebug_DHCSR_S_RETIRE_ST_Pos   24U

CoreDebug DHCSR: S_RETIRE_ST Position

◆ CoreDebug_DHCSR_S_RETIRE_ST_Pos [2/8]

#define CoreDebug_DHCSR_S_RETIRE_ST_Pos   24U

CoreDebug DHCSR: S_RETIRE_ST Position

◆ CoreDebug_DHCSR_S_RETIRE_ST_Pos [3/8]

#define CoreDebug_DHCSR_S_RETIRE_ST_Pos   24U

CoreDebug DHCSR: S_RETIRE_ST Position

◆ CoreDebug_DHCSR_S_RETIRE_ST_Pos [4/8]

#define CoreDebug_DHCSR_S_RETIRE_ST_Pos   24U

CoreDebug DHCSR: S_RETIRE_ST Position

◆ CoreDebug_DHCSR_S_RETIRE_ST_Pos [5/8]

#define CoreDebug_DHCSR_S_RETIRE_ST_Pos   24U

CoreDebug DHCSR: S_RETIRE_ST Position

◆ CoreDebug_DHCSR_S_RETIRE_ST_Pos [6/8]

#define CoreDebug_DHCSR_S_RETIRE_ST_Pos   24U

CoreDebug DHCSR: S_RETIRE_ST Position

◆ CoreDebug_DHCSR_S_RETIRE_ST_Pos [7/8]

#define CoreDebug_DHCSR_S_RETIRE_ST_Pos   24U

CoreDebug DHCSR: S_RETIRE_ST Position

◆ CoreDebug_DHCSR_S_RETIRE_ST_Pos [8/8]

#define CoreDebug_DHCSR_S_RETIRE_ST_Pos   24U

CoreDebug DHCSR: S_RETIRE_ST Position

◆ CoreDebug_DHCSR_S_SLEEP_Msk [1/8]

#define CoreDebug_DHCSR_S_SLEEP_Msk   (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

CoreDebug DHCSR: S_SLEEP Mask

◆ CoreDebug_DHCSR_S_SLEEP_Msk [2/8]

#define CoreDebug_DHCSR_S_SLEEP_Msk   (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

CoreDebug DHCSR: S_SLEEP Mask

◆ CoreDebug_DHCSR_S_SLEEP_Msk [3/8]

#define CoreDebug_DHCSR_S_SLEEP_Msk   (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

CoreDebug DHCSR: S_SLEEP Mask

◆ CoreDebug_DHCSR_S_SLEEP_Msk [4/8]

#define CoreDebug_DHCSR_S_SLEEP_Msk   (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

CoreDebug DHCSR: S_SLEEP Mask

◆ CoreDebug_DHCSR_S_SLEEP_Msk [5/8]

#define CoreDebug_DHCSR_S_SLEEP_Msk   (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

CoreDebug DHCSR: S_SLEEP Mask

◆ CoreDebug_DHCSR_S_SLEEP_Msk [6/8]

#define CoreDebug_DHCSR_S_SLEEP_Msk   (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

CoreDebug DHCSR: S_SLEEP Mask

◆ CoreDebug_DHCSR_S_SLEEP_Msk [7/8]

#define CoreDebug_DHCSR_S_SLEEP_Msk   (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

CoreDebug DHCSR: S_SLEEP Mask

◆ CoreDebug_DHCSR_S_SLEEP_Msk [8/8]

#define CoreDebug_DHCSR_S_SLEEP_Msk   (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

CoreDebug DHCSR: S_SLEEP Mask

◆ CoreDebug_DHCSR_S_SLEEP_Pos [1/8]

#define CoreDebug_DHCSR_S_SLEEP_Pos   18U

CoreDebug DHCSR: S_SLEEP Position

◆ CoreDebug_DHCSR_S_SLEEP_Pos [2/8]

#define CoreDebug_DHCSR_S_SLEEP_Pos   18U

CoreDebug DHCSR: S_SLEEP Position

◆ CoreDebug_DHCSR_S_SLEEP_Pos [3/8]

#define CoreDebug_DHCSR_S_SLEEP_Pos   18U

CoreDebug DHCSR: S_SLEEP Position

◆ CoreDebug_DHCSR_S_SLEEP_Pos [4/8]

#define CoreDebug_DHCSR_S_SLEEP_Pos   18U

CoreDebug DHCSR: S_SLEEP Position

◆ CoreDebug_DHCSR_S_SLEEP_Pos [5/8]

#define CoreDebug_DHCSR_S_SLEEP_Pos   18U

CoreDebug DHCSR: S_SLEEP Position

◆ CoreDebug_DHCSR_S_SLEEP_Pos [6/8]

#define CoreDebug_DHCSR_S_SLEEP_Pos   18U

CoreDebug DHCSR: S_SLEEP Position

◆ CoreDebug_DHCSR_S_SLEEP_Pos [7/8]

#define CoreDebug_DHCSR_S_SLEEP_Pos   18U

CoreDebug DHCSR: S_SLEEP Position

◆ CoreDebug_DHCSR_S_SLEEP_Pos [8/8]

#define CoreDebug_DHCSR_S_SLEEP_Pos   18U

CoreDebug DHCSR: S_SLEEP Position

◆ CoreDebug_DSCSR_CDS_Msk

#define CoreDebug_DSCSR_CDS_Msk   (1UL << CoreDebug_DSCSR_CDS_Pos)

CoreDebug DSCSR: CDS Mask

◆ CoreDebug_DSCSR_CDS_Pos

#define CoreDebug_DSCSR_CDS_Pos   16U

CoreDebug DSCSR: CDS Position

◆ CoreDebug_DSCSR_SBRSEL_Msk

#define CoreDebug_DSCSR_SBRSEL_Msk   (1UL << CoreDebug_DSCSR_SBRSEL_Pos)

CoreDebug DSCSR: SBRSEL Mask

◆ CoreDebug_DSCSR_SBRSEL_Pos

#define CoreDebug_DSCSR_SBRSEL_Pos   1U

CoreDebug DSCSR: SBRSEL Position

◆ CoreDebug_DSCSR_SBRSELEN_Msk

#define CoreDebug_DSCSR_SBRSELEN_Msk   (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)

CoreDebug DSCSR: SBRSELEN Mask

◆ CoreDebug_DSCSR_SBRSELEN_Pos

#define CoreDebug_DSCSR_SBRSELEN_Pos   0U

CoreDebug DSCSR: SBRSELEN Position

◆ DWT [1/8]

#define DWT   ((DWT_Type *) DWT_BASE )

DWT configuration struct

◆ DWT [2/8]

#define DWT   ((DWT_Type *) DWT_BASE )

DWT configuration struct

◆ DWT [3/8]

#define DWT   ((DWT_Type *) DWT_BASE )

DWT configuration struct

◆ DWT [4/8]

#define DWT   ((DWT_Type *) DWT_BASE )

DWT configuration struct

◆ DWT [5/8]

#define DWT   ((DWT_Type *) DWT_BASE )

DWT configuration struct

◆ DWT [6/8]

#define DWT   ((DWT_Type *) DWT_BASE )

DWT configuration struct

◆ DWT [7/8]

#define DWT   ((DWT_Type *) DWT_BASE )

DWT configuration struct

◆ DWT [8/8]

#define DWT   ((DWT_Type *) DWT_BASE )

DWT configuration struct

◆ DWT_BASE [1/8]

#define DWT_BASE   (0xE0001000UL)

DWT Base Address

◆ DWT_BASE [2/8]

#define DWT_BASE   (0xE0001000UL)

DWT Base Address

◆ DWT_BASE [3/8]

#define DWT_BASE   (0xE0001000UL)

DWT Base Address

◆ DWT_BASE [4/8]

#define DWT_BASE   (0xE0001000UL)

DWT Base Address

◆ DWT_BASE [5/8]

#define DWT_BASE   (0xE0001000UL)

DWT Base Address

◆ DWT_BASE [6/8]

#define DWT_BASE   (0xE0001000UL)

DWT Base Address

◆ DWT_BASE [7/8]

#define DWT_BASE   (0xE0001000UL)

DWT Base Address

◆ DWT_BASE [8/8]

#define DWT_BASE   (0xE0001000UL)

DWT Base Address

◆ DWT_CPICNT_CPICNT_Msk [1/6]

#define DWT_CPICNT_CPICNT_Msk   (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)

DWT CPICNT: CPICNT Mask

◆ DWT_CPICNT_CPICNT_Msk [2/6]

#define DWT_CPICNT_CPICNT_Msk   (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)

DWT CPICNT: CPICNT Mask

◆ DWT_CPICNT_CPICNT_Msk [3/6]

#define DWT_CPICNT_CPICNT_Msk   (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)

DWT CPICNT: CPICNT Mask

◆ DWT_CPICNT_CPICNT_Msk [4/6]

#define DWT_CPICNT_CPICNT_Msk   (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)

DWT CPICNT: CPICNT Mask

◆ DWT_CPICNT_CPICNT_Msk [5/6]

#define DWT_CPICNT_CPICNT_Msk   (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)

DWT CPICNT: CPICNT Mask

◆ DWT_CPICNT_CPICNT_Msk [6/6]

#define DWT_CPICNT_CPICNT_Msk   (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)

DWT CPICNT: CPICNT Mask

◆ DWT_CPICNT_CPICNT_Pos [1/6]

#define DWT_CPICNT_CPICNT_Pos   0U

DWT CPICNT: CPICNT Position

◆ DWT_CPICNT_CPICNT_Pos [2/6]

#define DWT_CPICNT_CPICNT_Pos   0U

DWT CPICNT: CPICNT Position

◆ DWT_CPICNT_CPICNT_Pos [3/6]

#define DWT_CPICNT_CPICNT_Pos   0U

DWT CPICNT: CPICNT Position

◆ DWT_CPICNT_CPICNT_Pos [4/6]

#define DWT_CPICNT_CPICNT_Pos   0U

DWT CPICNT: CPICNT Position

◆ DWT_CPICNT_CPICNT_Pos [5/6]

#define DWT_CPICNT_CPICNT_Pos   0U

DWT CPICNT: CPICNT Position

◆ DWT_CPICNT_CPICNT_Pos [6/6]

#define DWT_CPICNT_CPICNT_Pos   0U

DWT CPICNT: CPICNT Position

◆ DWT_CTRL_CPIEVTENA_Msk [1/6]

#define DWT_CTRL_CPIEVTENA_Msk   (0x1UL << DWT_CTRL_CPIEVTENA_Pos)

DWT CTRL: CPIEVTENA Mask

◆ DWT_CTRL_CPIEVTENA_Msk [2/6]

#define DWT_CTRL_CPIEVTENA_Msk   (0x1UL << DWT_CTRL_CPIEVTENA_Pos)

DWT CTRL: CPIEVTENA Mask

◆ DWT_CTRL_CPIEVTENA_Msk [3/6]

#define DWT_CTRL_CPIEVTENA_Msk   (0x1UL << DWT_CTRL_CPIEVTENA_Pos)

DWT CTRL: CPIEVTENA Mask

◆ DWT_CTRL_CPIEVTENA_Msk [4/6]

#define DWT_CTRL_CPIEVTENA_Msk   (0x1UL << DWT_CTRL_CPIEVTENA_Pos)

DWT CTRL: CPIEVTENA Mask

◆ DWT_CTRL_CPIEVTENA_Msk [5/6]

#define DWT_CTRL_CPIEVTENA_Msk   (0x1UL << DWT_CTRL_CPIEVTENA_Pos)

DWT CTRL: CPIEVTENA Mask

◆ DWT_CTRL_CPIEVTENA_Msk [6/6]

#define DWT_CTRL_CPIEVTENA_Msk   (0x1UL << DWT_CTRL_CPIEVTENA_Pos)

DWT CTRL: CPIEVTENA Mask

◆ DWT_CTRL_CPIEVTENA_Pos [1/6]

#define DWT_CTRL_CPIEVTENA_Pos   17U

DWT CTRL: CPIEVTENA Position

◆ DWT_CTRL_CPIEVTENA_Pos [2/6]

#define DWT_CTRL_CPIEVTENA_Pos   17U

DWT CTRL: CPIEVTENA Position

◆ DWT_CTRL_CPIEVTENA_Pos [3/6]

#define DWT_CTRL_CPIEVTENA_Pos   17U

DWT CTRL: CPIEVTENA Position

◆ DWT_CTRL_CPIEVTENA_Pos [4/6]

#define DWT_CTRL_CPIEVTENA_Pos   17U

DWT CTRL: CPIEVTENA Position

◆ DWT_CTRL_CPIEVTENA_Pos [5/6]

#define DWT_CTRL_CPIEVTENA_Pos   17U

DWT CTRL: CPIEVTENA Position

◆ DWT_CTRL_CPIEVTENA_Pos [6/6]

#define DWT_CTRL_CPIEVTENA_Pos   17U

DWT CTRL: CPIEVTENA Position

◆ DWT_CTRL_CYCCNTENA_Msk [1/6]

#define DWT_CTRL_CYCCNTENA_Msk   (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)

DWT CTRL: CYCCNTENA Mask

◆ DWT_CTRL_CYCCNTENA_Msk [2/6]

#define DWT_CTRL_CYCCNTENA_Msk   (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)

DWT CTRL: CYCCNTENA Mask

◆ DWT_CTRL_CYCCNTENA_Msk [3/6]

#define DWT_CTRL_CYCCNTENA_Msk   (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)

DWT CTRL: CYCCNTENA Mask

◆ DWT_CTRL_CYCCNTENA_Msk [4/6]

#define DWT_CTRL_CYCCNTENA_Msk   (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)

DWT CTRL: CYCCNTENA Mask

◆ DWT_CTRL_CYCCNTENA_Msk [5/6]

#define DWT_CTRL_CYCCNTENA_Msk   (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)

DWT CTRL: CYCCNTENA Mask

◆ DWT_CTRL_CYCCNTENA_Msk [6/6]

#define DWT_CTRL_CYCCNTENA_Msk   (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)

DWT CTRL: CYCCNTENA Mask

◆ DWT_CTRL_CYCCNTENA_Pos [1/6]

#define DWT_CTRL_CYCCNTENA_Pos   0U

DWT CTRL: CYCCNTENA Position

◆ DWT_CTRL_CYCCNTENA_Pos [2/6]

#define DWT_CTRL_CYCCNTENA_Pos   0U

DWT CTRL: CYCCNTENA Position

◆ DWT_CTRL_CYCCNTENA_Pos [3/6]

#define DWT_CTRL_CYCCNTENA_Pos   0U

DWT CTRL: CYCCNTENA Position

◆ DWT_CTRL_CYCCNTENA_Pos [4/6]

#define DWT_CTRL_CYCCNTENA_Pos   0U

DWT CTRL: CYCCNTENA Position

◆ DWT_CTRL_CYCCNTENA_Pos [5/6]

#define DWT_CTRL_CYCCNTENA_Pos   0U

DWT CTRL: CYCCNTENA Position

◆ DWT_CTRL_CYCCNTENA_Pos [6/6]

#define DWT_CTRL_CYCCNTENA_Pos   0U

DWT CTRL: CYCCNTENA Position

◆ DWT_CTRL_CYCDISS_Msk

#define DWT_CTRL_CYCDISS_Msk   (0x1UL << DWT_CTRL_CYCDISS_Pos)

DWT CTRL: CYCDISS Mask

◆ DWT_CTRL_CYCDISS_Pos

#define DWT_CTRL_CYCDISS_Pos   23U

DWT CTRL: CYCDISS Position

◆ DWT_CTRL_CYCEVTENA_Msk [1/6]

#define DWT_CTRL_CYCEVTENA_Msk   (0x1UL << DWT_CTRL_CYCEVTENA_Pos)

DWT CTRL: CYCEVTENA Mask

◆ DWT_CTRL_CYCEVTENA_Msk [2/6]

#define DWT_CTRL_CYCEVTENA_Msk   (0x1UL << DWT_CTRL_CYCEVTENA_Pos)

DWT CTRL: CYCEVTENA Mask

◆ DWT_CTRL_CYCEVTENA_Msk [3/6]

#define DWT_CTRL_CYCEVTENA_Msk   (0x1UL << DWT_CTRL_CYCEVTENA_Pos)

DWT CTRL: CYCEVTENA Mask

◆ DWT_CTRL_CYCEVTENA_Msk [4/6]

#define DWT_CTRL_CYCEVTENA_Msk   (0x1UL << DWT_CTRL_CYCEVTENA_Pos)

DWT CTRL: CYCEVTENA Mask

◆ DWT_CTRL_CYCEVTENA_Msk [5/6]

#define DWT_CTRL_CYCEVTENA_Msk   (0x1UL << DWT_CTRL_CYCEVTENA_Pos)

DWT CTRL: CYCEVTENA Mask

◆ DWT_CTRL_CYCEVTENA_Msk [6/6]

#define DWT_CTRL_CYCEVTENA_Msk   (0x1UL << DWT_CTRL_CYCEVTENA_Pos)

DWT CTRL: CYCEVTENA Mask

◆ DWT_CTRL_CYCEVTENA_Pos [1/6]

#define DWT_CTRL_CYCEVTENA_Pos   22U

DWT CTRL: CYCEVTENA Position

◆ DWT_CTRL_CYCEVTENA_Pos [2/6]

#define DWT_CTRL_CYCEVTENA_Pos   22U

DWT CTRL: CYCEVTENA Position

◆ DWT_CTRL_CYCEVTENA_Pos [3/6]

#define DWT_CTRL_CYCEVTENA_Pos   22U

DWT CTRL: CYCEVTENA Position

◆ DWT_CTRL_CYCEVTENA_Pos [4/6]

#define DWT_CTRL_CYCEVTENA_Pos   22U

DWT CTRL: CYCEVTENA Position

◆ DWT_CTRL_CYCEVTENA_Pos [5/6]

#define DWT_CTRL_CYCEVTENA_Pos   22U

DWT CTRL: CYCEVTENA Position

◆ DWT_CTRL_CYCEVTENA_Pos [6/6]

#define DWT_CTRL_CYCEVTENA_Pos   22U

DWT CTRL: CYCEVTENA Position

◆ DWT_CTRL_CYCTAP_Msk [1/6]

#define DWT_CTRL_CYCTAP_Msk   (0x1UL << DWT_CTRL_CYCTAP_Pos)

DWT CTRL: CYCTAP Mask

◆ DWT_CTRL_CYCTAP_Msk [2/6]

#define DWT_CTRL_CYCTAP_Msk   (0x1UL << DWT_CTRL_CYCTAP_Pos)

DWT CTRL: CYCTAP Mask

◆ DWT_CTRL_CYCTAP_Msk [3/6]

#define DWT_CTRL_CYCTAP_Msk   (0x1UL << DWT_CTRL_CYCTAP_Pos)

DWT CTRL: CYCTAP Mask

◆ DWT_CTRL_CYCTAP_Msk [4/6]

#define DWT_CTRL_CYCTAP_Msk   (0x1UL << DWT_CTRL_CYCTAP_Pos)

DWT CTRL: CYCTAP Mask

◆ DWT_CTRL_CYCTAP_Msk [5/6]

#define DWT_CTRL_CYCTAP_Msk   (0x1UL << DWT_CTRL_CYCTAP_Pos)

DWT CTRL: CYCTAP Mask

◆ DWT_CTRL_CYCTAP_Msk [6/6]

#define DWT_CTRL_CYCTAP_Msk   (0x1UL << DWT_CTRL_CYCTAP_Pos)

DWT CTRL: CYCTAP Mask

◆ DWT_CTRL_CYCTAP_Pos [1/6]

#define DWT_CTRL_CYCTAP_Pos   9U

DWT CTRL: CYCTAP Position

◆ DWT_CTRL_CYCTAP_Pos [2/6]

#define DWT_CTRL_CYCTAP_Pos   9U

DWT CTRL: CYCTAP Position

◆ DWT_CTRL_CYCTAP_Pos [3/6]

#define DWT_CTRL_CYCTAP_Pos   9U

DWT CTRL: CYCTAP Position

◆ DWT_CTRL_CYCTAP_Pos [4/6]

#define DWT_CTRL_CYCTAP_Pos   9U

DWT CTRL: CYCTAP Position

◆ DWT_CTRL_CYCTAP_Pos [5/6]

#define DWT_CTRL_CYCTAP_Pos   9U

DWT CTRL: CYCTAP Position

◆ DWT_CTRL_CYCTAP_Pos [6/6]

#define DWT_CTRL_CYCTAP_Pos   9U

DWT CTRL: CYCTAP Position

◆ DWT_CTRL_EXCEVTENA_Msk [1/6]

#define DWT_CTRL_EXCEVTENA_Msk   (0x1UL << DWT_CTRL_EXCEVTENA_Pos)

DWT CTRL: EXCEVTENA Mask

◆ DWT_CTRL_EXCEVTENA_Msk [2/6]

#define DWT_CTRL_EXCEVTENA_Msk   (0x1UL << DWT_CTRL_EXCEVTENA_Pos)

DWT CTRL: EXCEVTENA Mask

◆ DWT_CTRL_EXCEVTENA_Msk [3/6]

#define DWT_CTRL_EXCEVTENA_Msk   (0x1UL << DWT_CTRL_EXCEVTENA_Pos)

DWT CTRL: EXCEVTENA Mask

◆ DWT_CTRL_EXCEVTENA_Msk [4/6]

#define DWT_CTRL_EXCEVTENA_Msk   (0x1UL << DWT_CTRL_EXCEVTENA_Pos)

DWT CTRL: EXCEVTENA Mask

◆ DWT_CTRL_EXCEVTENA_Msk [5/6]

#define DWT_CTRL_EXCEVTENA_Msk   (0x1UL << DWT_CTRL_EXCEVTENA_Pos)

DWT CTRL: EXCEVTENA Mask

◆ DWT_CTRL_EXCEVTENA_Msk [6/6]

#define DWT_CTRL_EXCEVTENA_Msk   (0x1UL << DWT_CTRL_EXCEVTENA_Pos)

DWT CTRL: EXCEVTENA Mask

◆ DWT_CTRL_EXCEVTENA_Pos [1/6]

#define DWT_CTRL_EXCEVTENA_Pos   18U

DWT CTRL: EXCEVTENA Position

◆ DWT_CTRL_EXCEVTENA_Pos [2/6]

#define DWT_CTRL_EXCEVTENA_Pos   18U

DWT CTRL: EXCEVTENA Position

◆ DWT_CTRL_EXCEVTENA_Pos [3/6]

#define DWT_CTRL_EXCEVTENA_Pos   18U

DWT CTRL: EXCEVTENA Position

◆ DWT_CTRL_EXCEVTENA_Pos [4/6]

#define DWT_CTRL_EXCEVTENA_Pos   18U

DWT CTRL: EXCEVTENA Position

◆ DWT_CTRL_EXCEVTENA_Pos [5/6]

#define DWT_CTRL_EXCEVTENA_Pos   18U

DWT CTRL: EXCEVTENA Position

◆ DWT_CTRL_EXCEVTENA_Pos [6/6]

#define DWT_CTRL_EXCEVTENA_Pos   18U

DWT CTRL: EXCEVTENA Position

◆ DWT_CTRL_EXCTRCENA_Msk [1/6]

#define DWT_CTRL_EXCTRCENA_Msk   (0x1UL << DWT_CTRL_EXCTRCENA_Pos)

DWT CTRL: EXCTRCENA Mask

◆ DWT_CTRL_EXCTRCENA_Msk [2/6]

#define DWT_CTRL_EXCTRCENA_Msk   (0x1UL << DWT_CTRL_EXCTRCENA_Pos)

DWT CTRL: EXCTRCENA Mask

◆ DWT_CTRL_EXCTRCENA_Msk [3/6]

#define DWT_CTRL_EXCTRCENA_Msk   (0x1UL << DWT_CTRL_EXCTRCENA_Pos)

DWT CTRL: EXCTRCENA Mask

◆ DWT_CTRL_EXCTRCENA_Msk [4/6]

#define DWT_CTRL_EXCTRCENA_Msk   (0x1UL << DWT_CTRL_EXCTRCENA_Pos)

DWT CTRL: EXCTRCENA Mask

◆ DWT_CTRL_EXCTRCENA_Msk [5/6]

#define DWT_CTRL_EXCTRCENA_Msk   (0x1UL << DWT_CTRL_EXCTRCENA_Pos)

DWT CTRL: EXCTRCENA Mask

◆ DWT_CTRL_EXCTRCENA_Msk [6/6]

#define DWT_CTRL_EXCTRCENA_Msk   (0x1UL << DWT_CTRL_EXCTRCENA_Pos)

DWT CTRL: EXCTRCENA Mask

◆ DWT_CTRL_EXCTRCENA_Pos [1/6]

#define DWT_CTRL_EXCTRCENA_Pos   16U

DWT CTRL: EXCTRCENA Position

◆ DWT_CTRL_EXCTRCENA_Pos [2/6]

#define DWT_CTRL_EXCTRCENA_Pos   16U

DWT CTRL: EXCTRCENA Position

◆ DWT_CTRL_EXCTRCENA_Pos [3/6]

#define DWT_CTRL_EXCTRCENA_Pos   16U

DWT CTRL: EXCTRCENA Position

◆ DWT_CTRL_EXCTRCENA_Pos [4/6]

#define DWT_CTRL_EXCTRCENA_Pos   16U

DWT CTRL: EXCTRCENA Position

◆ DWT_CTRL_EXCTRCENA_Pos [5/6]

#define DWT_CTRL_EXCTRCENA_Pos   16U

DWT CTRL: EXCTRCENA Position

◆ DWT_CTRL_EXCTRCENA_Pos [6/6]

#define DWT_CTRL_EXCTRCENA_Pos   16U

DWT CTRL: EXCTRCENA Position

◆ DWT_CTRL_FOLDEVTENA_Msk [1/6]

#define DWT_CTRL_FOLDEVTENA_Msk   (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)

DWT CTRL: FOLDEVTENA Mask

◆ DWT_CTRL_FOLDEVTENA_Msk [2/6]

#define DWT_CTRL_FOLDEVTENA_Msk   (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)

DWT CTRL: FOLDEVTENA Mask

◆ DWT_CTRL_FOLDEVTENA_Msk [3/6]

#define DWT_CTRL_FOLDEVTENA_Msk   (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)

DWT CTRL: FOLDEVTENA Mask

◆ DWT_CTRL_FOLDEVTENA_Msk [4/6]

#define DWT_CTRL_FOLDEVTENA_Msk   (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)

DWT CTRL: FOLDEVTENA Mask

◆ DWT_CTRL_FOLDEVTENA_Msk [5/6]

#define DWT_CTRL_FOLDEVTENA_Msk   (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)

DWT CTRL: FOLDEVTENA Mask

◆ DWT_CTRL_FOLDEVTENA_Msk [6/6]

#define DWT_CTRL_FOLDEVTENA_Msk   (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)

DWT CTRL: FOLDEVTENA Mask

◆ DWT_CTRL_FOLDEVTENA_Pos [1/6]

#define DWT_CTRL_FOLDEVTENA_Pos   21U

DWT CTRL: FOLDEVTENA Position

◆ DWT_CTRL_FOLDEVTENA_Pos [2/6]

#define DWT_CTRL_FOLDEVTENA_Pos   21U

DWT CTRL: FOLDEVTENA Position

◆ DWT_CTRL_FOLDEVTENA_Pos [3/6]

#define DWT_CTRL_FOLDEVTENA_Pos   21U

DWT CTRL: FOLDEVTENA Position

◆ DWT_CTRL_FOLDEVTENA_Pos [4/6]

#define DWT_CTRL_FOLDEVTENA_Pos   21U

DWT CTRL: FOLDEVTENA Position

◆ DWT_CTRL_FOLDEVTENA_Pos [5/6]

#define DWT_CTRL_FOLDEVTENA_Pos   21U

DWT CTRL: FOLDEVTENA Position

◆ DWT_CTRL_FOLDEVTENA_Pos [6/6]

#define DWT_CTRL_FOLDEVTENA_Pos   21U

DWT CTRL: FOLDEVTENA Position

◆ DWT_CTRL_LSUEVTENA_Msk [1/6]

#define DWT_CTRL_LSUEVTENA_Msk   (0x1UL << DWT_CTRL_LSUEVTENA_Pos)

DWT CTRL: LSUEVTENA Mask

◆ DWT_CTRL_LSUEVTENA_Msk [2/6]

#define DWT_CTRL_LSUEVTENA_Msk   (0x1UL << DWT_CTRL_LSUEVTENA_Pos)

DWT CTRL: LSUEVTENA Mask

◆ DWT_CTRL_LSUEVTENA_Msk [3/6]

#define DWT_CTRL_LSUEVTENA_Msk   (0x1UL << DWT_CTRL_LSUEVTENA_Pos)

DWT CTRL: LSUEVTENA Mask

◆ DWT_CTRL_LSUEVTENA_Msk [4/6]

#define DWT_CTRL_LSUEVTENA_Msk   (0x1UL << DWT_CTRL_LSUEVTENA_Pos)

DWT CTRL: LSUEVTENA Mask

◆ DWT_CTRL_LSUEVTENA_Msk [5/6]

#define DWT_CTRL_LSUEVTENA_Msk   (0x1UL << DWT_CTRL_LSUEVTENA_Pos)

DWT CTRL: LSUEVTENA Mask

◆ DWT_CTRL_LSUEVTENA_Msk [6/6]

#define DWT_CTRL_LSUEVTENA_Msk   (0x1UL << DWT_CTRL_LSUEVTENA_Pos)

DWT CTRL: LSUEVTENA Mask

◆ DWT_CTRL_LSUEVTENA_Pos [1/6]

#define DWT_CTRL_LSUEVTENA_Pos   20U

DWT CTRL: LSUEVTENA Position

◆ DWT_CTRL_LSUEVTENA_Pos [2/6]

#define DWT_CTRL_LSUEVTENA_Pos   20U

DWT CTRL: LSUEVTENA Position

◆ DWT_CTRL_LSUEVTENA_Pos [3/6]

#define DWT_CTRL_LSUEVTENA_Pos   20U

DWT CTRL: LSUEVTENA Position

◆ DWT_CTRL_LSUEVTENA_Pos [4/6]

#define DWT_CTRL_LSUEVTENA_Pos   20U

DWT CTRL: LSUEVTENA Position

◆ DWT_CTRL_LSUEVTENA_Pos [5/6]

#define DWT_CTRL_LSUEVTENA_Pos   20U

DWT CTRL: LSUEVTENA Position

◆ DWT_CTRL_LSUEVTENA_Pos [6/6]

#define DWT_CTRL_LSUEVTENA_Pos   20U

DWT CTRL: LSUEVTENA Position

◆ DWT_CTRL_NOCYCCNT_Msk [1/8]

#define DWT_CTRL_NOCYCCNT_Msk   (0x1UL << DWT_CTRL_NOCYCCNT_Pos)

DWT CTRL: NOCYCCNT Mask

◆ DWT_CTRL_NOCYCCNT_Msk [2/8]

#define DWT_CTRL_NOCYCCNT_Msk   (0x1UL << DWT_CTRL_NOCYCCNT_Pos)

DWT CTRL: NOCYCCNT Mask

◆ DWT_CTRL_NOCYCCNT_Msk [3/8]

#define DWT_CTRL_NOCYCCNT_Msk   (0x1UL << DWT_CTRL_NOCYCCNT_Pos)

DWT CTRL: NOCYCCNT Mask

◆ DWT_CTRL_NOCYCCNT_Msk [4/8]

#define DWT_CTRL_NOCYCCNT_Msk   (0x1UL << DWT_CTRL_NOCYCCNT_Pos)

DWT CTRL: NOCYCCNT Mask

◆ DWT_CTRL_NOCYCCNT_Msk [5/8]

#define DWT_CTRL_NOCYCCNT_Msk   (0x1UL << DWT_CTRL_NOCYCCNT_Pos)

DWT CTRL: NOCYCCNT Mask

◆ DWT_CTRL_NOCYCCNT_Msk [6/8]

#define DWT_CTRL_NOCYCCNT_Msk   (0x1UL << DWT_CTRL_NOCYCCNT_Pos)

DWT CTRL: NOCYCCNT Mask

◆ DWT_CTRL_NOCYCCNT_Msk [7/8]

#define DWT_CTRL_NOCYCCNT_Msk   (0x1UL << DWT_CTRL_NOCYCCNT_Pos)

DWT CTRL: NOCYCCNT Mask

◆ DWT_CTRL_NOCYCCNT_Msk [8/8]

#define DWT_CTRL_NOCYCCNT_Msk   (0x1UL << DWT_CTRL_NOCYCCNT_Pos)

DWT CTRL: NOCYCCNT Mask

◆ DWT_CTRL_NOCYCCNT_Pos [1/8]

#define DWT_CTRL_NOCYCCNT_Pos   25U

DWT CTRL: NOCYCCNT Position

◆ DWT_CTRL_NOCYCCNT_Pos [2/8]

#define DWT_CTRL_NOCYCCNT_Pos   25U

DWT CTRL: NOCYCCNT Position

◆ DWT_CTRL_NOCYCCNT_Pos [3/8]

#define DWT_CTRL_NOCYCCNT_Pos   25U

DWT CTRL: NOCYCCNT Position

◆ DWT_CTRL_NOCYCCNT_Pos [4/8]

#define DWT_CTRL_NOCYCCNT_Pos   25U

DWT CTRL: NOCYCCNT Position

◆ DWT_CTRL_NOCYCCNT_Pos [5/8]

#define DWT_CTRL_NOCYCCNT_Pos   25U

DWT CTRL: NOCYCCNT Position

◆ DWT_CTRL_NOCYCCNT_Pos [6/8]

#define DWT_CTRL_NOCYCCNT_Pos   25U

DWT CTRL: NOCYCCNT Position

◆ DWT_CTRL_NOCYCCNT_Pos [7/8]

#define DWT_CTRL_NOCYCCNT_Pos   25U

DWT CTRL: NOCYCCNT Position

◆ DWT_CTRL_NOCYCCNT_Pos [8/8]

#define DWT_CTRL_NOCYCCNT_Pos   25U

DWT CTRL: NOCYCCNT Position

◆ DWT_CTRL_NOEXTTRIG_Msk [1/8]

#define DWT_CTRL_NOEXTTRIG_Msk   (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)

DWT CTRL: NOEXTTRIG Mask

◆ DWT_CTRL_NOEXTTRIG_Msk [2/8]

#define DWT_CTRL_NOEXTTRIG_Msk   (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)

DWT CTRL: NOEXTTRIG Mask

◆ DWT_CTRL_NOEXTTRIG_Msk [3/8]

#define DWT_CTRL_NOEXTTRIG_Msk   (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)

DWT CTRL: NOEXTTRIG Mask

◆ DWT_CTRL_NOEXTTRIG_Msk [4/8]

#define DWT_CTRL_NOEXTTRIG_Msk   (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)

DWT CTRL: NOEXTTRIG Mask

◆ DWT_CTRL_NOEXTTRIG_Msk [5/8]

#define DWT_CTRL_NOEXTTRIG_Msk   (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)

DWT CTRL: NOEXTTRIG Mask

◆ DWT_CTRL_NOEXTTRIG_Msk [6/8]

#define DWT_CTRL_NOEXTTRIG_Msk   (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)

DWT CTRL: NOEXTTRIG Mask

◆ DWT_CTRL_NOEXTTRIG_Msk [7/8]

#define DWT_CTRL_NOEXTTRIG_Msk   (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)

DWT CTRL: NOEXTTRIG Mask

◆ DWT_CTRL_NOEXTTRIG_Msk [8/8]

#define DWT_CTRL_NOEXTTRIG_Msk   (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)

DWT CTRL: NOEXTTRIG Mask

◆ DWT_CTRL_NOEXTTRIG_Pos [1/8]

#define DWT_CTRL_NOEXTTRIG_Pos   26U

DWT CTRL: NOEXTTRIG Position

◆ DWT_CTRL_NOEXTTRIG_Pos [2/8]

#define DWT_CTRL_NOEXTTRIG_Pos   26U

DWT CTRL: NOEXTTRIG Position

◆ DWT_CTRL_NOEXTTRIG_Pos [3/8]

#define DWT_CTRL_NOEXTTRIG_Pos   26U

DWT CTRL: NOEXTTRIG Position

◆ DWT_CTRL_NOEXTTRIG_Pos [4/8]

#define DWT_CTRL_NOEXTTRIG_Pos   26U

DWT CTRL: NOEXTTRIG Position

◆ DWT_CTRL_NOEXTTRIG_Pos [5/8]

#define DWT_CTRL_NOEXTTRIG_Pos   26U

DWT CTRL: NOEXTTRIG Position

◆ DWT_CTRL_NOEXTTRIG_Pos [6/8]

#define DWT_CTRL_NOEXTTRIG_Pos   26U

DWT CTRL: NOEXTTRIG Position

◆ DWT_CTRL_NOEXTTRIG_Pos [7/8]

#define DWT_CTRL_NOEXTTRIG_Pos   26U

DWT CTRL: NOEXTTRIG Position

◆ DWT_CTRL_NOEXTTRIG_Pos [8/8]

#define DWT_CTRL_NOEXTTRIG_Pos   26U

DWT CTRL: NOEXTTRIG Position

◆ DWT_CTRL_NOPRFCNT_Msk [1/8]

#define DWT_CTRL_NOPRFCNT_Msk   (0x1UL << DWT_CTRL_NOPRFCNT_Pos)

DWT CTRL: NOPRFCNT Mask

◆ DWT_CTRL_NOPRFCNT_Msk [2/8]

#define DWT_CTRL_NOPRFCNT_Msk   (0x1UL << DWT_CTRL_NOPRFCNT_Pos)

DWT CTRL: NOPRFCNT Mask

◆ DWT_CTRL_NOPRFCNT_Msk [3/8]

#define DWT_CTRL_NOPRFCNT_Msk   (0x1UL << DWT_CTRL_NOPRFCNT_Pos)

DWT CTRL: NOPRFCNT Mask

◆ DWT_CTRL_NOPRFCNT_Msk [4/8]

#define DWT_CTRL_NOPRFCNT_Msk   (0x1UL << DWT_CTRL_NOPRFCNT_Pos)

DWT CTRL: NOPRFCNT Mask

◆ DWT_CTRL_NOPRFCNT_Msk [5/8]

#define DWT_CTRL_NOPRFCNT_Msk   (0x1UL << DWT_CTRL_NOPRFCNT_Pos)

DWT CTRL: NOPRFCNT Mask

◆ DWT_CTRL_NOPRFCNT_Msk [6/8]

#define DWT_CTRL_NOPRFCNT_Msk   (0x1UL << DWT_CTRL_NOPRFCNT_Pos)

DWT CTRL: NOPRFCNT Mask

◆ DWT_CTRL_NOPRFCNT_Msk [7/8]

#define DWT_CTRL_NOPRFCNT_Msk   (0x1UL << DWT_CTRL_NOPRFCNT_Pos)

DWT CTRL: NOPRFCNT Mask

◆ DWT_CTRL_NOPRFCNT_Msk [8/8]

#define DWT_CTRL_NOPRFCNT_Msk   (0x1UL << DWT_CTRL_NOPRFCNT_Pos)

DWT CTRL: NOPRFCNT Mask

◆ DWT_CTRL_NOPRFCNT_Pos [1/8]

#define DWT_CTRL_NOPRFCNT_Pos   24U

DWT CTRL: NOPRFCNT Position

◆ DWT_CTRL_NOPRFCNT_Pos [2/8]

#define DWT_CTRL_NOPRFCNT_Pos   24U

DWT CTRL: NOPRFCNT Position

◆ DWT_CTRL_NOPRFCNT_Pos [3/8]

#define DWT_CTRL_NOPRFCNT_Pos   24U

DWT CTRL: NOPRFCNT Position

◆ DWT_CTRL_NOPRFCNT_Pos [4/8]

#define DWT_CTRL_NOPRFCNT_Pos   24U

DWT CTRL: NOPRFCNT Position

◆ DWT_CTRL_NOPRFCNT_Pos [5/8]

#define DWT_CTRL_NOPRFCNT_Pos   24U

DWT CTRL: NOPRFCNT Position

◆ DWT_CTRL_NOPRFCNT_Pos [6/8]

#define DWT_CTRL_NOPRFCNT_Pos   24U

DWT CTRL: NOPRFCNT Position

◆ DWT_CTRL_NOPRFCNT_Pos [7/8]

#define DWT_CTRL_NOPRFCNT_Pos   24U

DWT CTRL: NOPRFCNT Position

◆ DWT_CTRL_NOPRFCNT_Pos [8/8]

#define DWT_CTRL_NOPRFCNT_Pos   24U

DWT CTRL: NOPRFCNT Position

◆ DWT_CTRL_NOTRCPKT_Msk [1/8]

#define DWT_CTRL_NOTRCPKT_Msk   (0x1UL << DWT_CTRL_NOTRCPKT_Pos)

DWT CTRL: NOTRCPKT Mask

◆ DWT_CTRL_NOTRCPKT_Msk [2/8]

#define DWT_CTRL_NOTRCPKT_Msk   (0x1UL << DWT_CTRL_NOTRCPKT_Pos)

DWT CTRL: NOTRCPKT Mask

◆ DWT_CTRL_NOTRCPKT_Msk [3/8]

#define DWT_CTRL_NOTRCPKT_Msk   (0x1UL << DWT_CTRL_NOTRCPKT_Pos)

DWT CTRL: NOTRCPKT Mask

◆ DWT_CTRL_NOTRCPKT_Msk [4/8]

#define DWT_CTRL_NOTRCPKT_Msk   (0x1UL << DWT_CTRL_NOTRCPKT_Pos)

DWT CTRL: NOTRCPKT Mask

◆ DWT_CTRL_NOTRCPKT_Msk [5/8]

#define DWT_CTRL_NOTRCPKT_Msk   (0x1UL << DWT_CTRL_NOTRCPKT_Pos)

DWT CTRL: NOTRCPKT Mask

◆ DWT_CTRL_NOTRCPKT_Msk [6/8]

#define DWT_CTRL_NOTRCPKT_Msk   (0x1UL << DWT_CTRL_NOTRCPKT_Pos)

DWT CTRL: NOTRCPKT Mask

◆ DWT_CTRL_NOTRCPKT_Msk [7/8]

#define DWT_CTRL_NOTRCPKT_Msk   (0x1UL << DWT_CTRL_NOTRCPKT_Pos)

DWT CTRL: NOTRCPKT Mask

◆ DWT_CTRL_NOTRCPKT_Msk [8/8]

#define DWT_CTRL_NOTRCPKT_Msk   (0x1UL << DWT_CTRL_NOTRCPKT_Pos)

DWT CTRL: NOTRCPKT Mask

◆ DWT_CTRL_NOTRCPKT_Pos [1/8]

#define DWT_CTRL_NOTRCPKT_Pos   27U

DWT CTRL: NOTRCPKT Position

◆ DWT_CTRL_NOTRCPKT_Pos [2/8]

#define DWT_CTRL_NOTRCPKT_Pos   27U

DWT CTRL: NOTRCPKT Position

◆ DWT_CTRL_NOTRCPKT_Pos [3/8]

#define DWT_CTRL_NOTRCPKT_Pos   27U

DWT CTRL: NOTRCPKT Position

◆ DWT_CTRL_NOTRCPKT_Pos [4/8]

#define DWT_CTRL_NOTRCPKT_Pos   27U

DWT CTRL: NOTRCPKT Position

◆ DWT_CTRL_NOTRCPKT_Pos [5/8]

#define DWT_CTRL_NOTRCPKT_Pos   27U

DWT CTRL: NOTRCPKT Position

◆ DWT_CTRL_NOTRCPKT_Pos [6/8]

#define DWT_CTRL_NOTRCPKT_Pos   27U

DWT CTRL: NOTRCPKT Position

◆ DWT_CTRL_NOTRCPKT_Pos [7/8]

#define DWT_CTRL_NOTRCPKT_Pos   27U

DWT CTRL: NOTRCPKT Position

◆ DWT_CTRL_NOTRCPKT_Pos [8/8]

#define DWT_CTRL_NOTRCPKT_Pos   27U

DWT CTRL: NOTRCPKT Position

◆ DWT_CTRL_NUMCOMP_Msk [1/8]

#define DWT_CTRL_NUMCOMP_Msk   (0xFUL << DWT_CTRL_NUMCOMP_Pos)

DWT CTRL: NUMCOMP Mask

◆ DWT_CTRL_NUMCOMP_Msk [2/8]

#define DWT_CTRL_NUMCOMP_Msk   (0xFUL << DWT_CTRL_NUMCOMP_Pos)

DWT CTRL: NUMCOMP Mask

◆ DWT_CTRL_NUMCOMP_Msk [3/8]

#define DWT_CTRL_NUMCOMP_Msk   (0xFUL << DWT_CTRL_NUMCOMP_Pos)

DWT CTRL: NUMCOMP Mask

◆ DWT_CTRL_NUMCOMP_Msk [4/8]

#define DWT_CTRL_NUMCOMP_Msk   (0xFUL << DWT_CTRL_NUMCOMP_Pos)

DWT CTRL: NUMCOMP Mask

◆ DWT_CTRL_NUMCOMP_Msk [5/8]

#define DWT_CTRL_NUMCOMP_Msk   (0xFUL << DWT_CTRL_NUMCOMP_Pos)

DWT CTRL: NUMCOMP Mask

◆ DWT_CTRL_NUMCOMP_Msk [6/8]

#define DWT_CTRL_NUMCOMP_Msk   (0xFUL << DWT_CTRL_NUMCOMP_Pos)

DWT CTRL: NUMCOMP Mask

◆ DWT_CTRL_NUMCOMP_Msk [7/8]

#define DWT_CTRL_NUMCOMP_Msk   (0xFUL << DWT_CTRL_NUMCOMP_Pos)

DWT CTRL: NUMCOMP Mask

◆ DWT_CTRL_NUMCOMP_Msk [8/8]

#define DWT_CTRL_NUMCOMP_Msk   (0xFUL << DWT_CTRL_NUMCOMP_Pos)

DWT CTRL: NUMCOMP Mask

◆ DWT_CTRL_NUMCOMP_Pos [1/8]

#define DWT_CTRL_NUMCOMP_Pos   28U

DWT CTRL: NUMCOMP Position

◆ DWT_CTRL_NUMCOMP_Pos [2/8]

#define DWT_CTRL_NUMCOMP_Pos   28U

DWT CTRL: NUMCOMP Position

◆ DWT_CTRL_NUMCOMP_Pos [3/8]

#define DWT_CTRL_NUMCOMP_Pos   28U

DWT CTRL: NUMCOMP Position

◆ DWT_CTRL_NUMCOMP_Pos [4/8]

#define DWT_CTRL_NUMCOMP_Pos   28U

DWT CTRL: NUMCOMP Position

◆ DWT_CTRL_NUMCOMP_Pos [5/8]

#define DWT_CTRL_NUMCOMP_Pos   28U

DWT CTRL: NUMCOMP Position

◆ DWT_CTRL_NUMCOMP_Pos [6/8]

#define DWT_CTRL_NUMCOMP_Pos   28U

DWT CTRL: NUMCOMP Position

◆ DWT_CTRL_NUMCOMP_Pos [7/8]

#define DWT_CTRL_NUMCOMP_Pos   28U

DWT CTRL: NUMCOMP Position

◆ DWT_CTRL_NUMCOMP_Pos [8/8]

#define DWT_CTRL_NUMCOMP_Pos   28U

DWT CTRL: NUMCOMP Position

◆ DWT_CTRL_PCSAMPLENA_Msk [1/6]

#define DWT_CTRL_PCSAMPLENA_Msk   (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)

DWT CTRL: PCSAMPLENA Mask

◆ DWT_CTRL_PCSAMPLENA_Msk [2/6]

#define DWT_CTRL_PCSAMPLENA_Msk   (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)

DWT CTRL: PCSAMPLENA Mask

◆ DWT_CTRL_PCSAMPLENA_Msk [3/6]

#define DWT_CTRL_PCSAMPLENA_Msk   (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)

DWT CTRL: PCSAMPLENA Mask

◆ DWT_CTRL_PCSAMPLENA_Msk [4/6]

#define DWT_CTRL_PCSAMPLENA_Msk   (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)

DWT CTRL: PCSAMPLENA Mask

◆ DWT_CTRL_PCSAMPLENA_Msk [5/6]

#define DWT_CTRL_PCSAMPLENA_Msk   (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)

DWT CTRL: PCSAMPLENA Mask

◆ DWT_CTRL_PCSAMPLENA_Msk [6/6]

#define DWT_CTRL_PCSAMPLENA_Msk   (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)

DWT CTRL: PCSAMPLENA Mask

◆ DWT_CTRL_PCSAMPLENA_Pos [1/6]

#define DWT_CTRL_PCSAMPLENA_Pos   12U

DWT CTRL: PCSAMPLENA Position

◆ DWT_CTRL_PCSAMPLENA_Pos [2/6]

#define DWT_CTRL_PCSAMPLENA_Pos   12U

DWT CTRL: PCSAMPLENA Position

◆ DWT_CTRL_PCSAMPLENA_Pos [3/6]

#define DWT_CTRL_PCSAMPLENA_Pos   12U

DWT CTRL: PCSAMPLENA Position

◆ DWT_CTRL_PCSAMPLENA_Pos [4/6]

#define DWT_CTRL_PCSAMPLENA_Pos   12U

DWT CTRL: PCSAMPLENA Position

◆ DWT_CTRL_PCSAMPLENA_Pos [5/6]

#define DWT_CTRL_PCSAMPLENA_Pos   12U

DWT CTRL: PCSAMPLENA Position

◆ DWT_CTRL_PCSAMPLENA_Pos [6/6]

#define DWT_CTRL_PCSAMPLENA_Pos   12U

DWT CTRL: PCSAMPLENA Position

◆ DWT_CTRL_POSTINIT_Msk [1/6]

#define DWT_CTRL_POSTINIT_Msk   (0xFUL << DWT_CTRL_POSTINIT_Pos)

DWT CTRL: POSTINIT Mask

◆ DWT_CTRL_POSTINIT_Msk [2/6]

#define DWT_CTRL_POSTINIT_Msk   (0xFUL << DWT_CTRL_POSTINIT_Pos)

DWT CTRL: POSTINIT Mask

◆ DWT_CTRL_POSTINIT_Msk [3/6]

#define DWT_CTRL_POSTINIT_Msk   (0xFUL << DWT_CTRL_POSTINIT_Pos)

DWT CTRL: POSTINIT Mask

◆ DWT_CTRL_POSTINIT_Msk [4/6]

#define DWT_CTRL_POSTINIT_Msk   (0xFUL << DWT_CTRL_POSTINIT_Pos)

DWT CTRL: POSTINIT Mask

◆ DWT_CTRL_POSTINIT_Msk [5/6]

#define DWT_CTRL_POSTINIT_Msk   (0xFUL << DWT_CTRL_POSTINIT_Pos)

DWT CTRL: POSTINIT Mask

◆ DWT_CTRL_POSTINIT_Msk [6/6]

#define DWT_CTRL_POSTINIT_Msk   (0xFUL << DWT_CTRL_POSTINIT_Pos)

DWT CTRL: POSTINIT Mask

◆ DWT_CTRL_POSTINIT_Pos [1/6]

#define DWT_CTRL_POSTINIT_Pos   5U

DWT CTRL: POSTINIT Position

◆ DWT_CTRL_POSTINIT_Pos [2/6]

#define DWT_CTRL_POSTINIT_Pos   5U

DWT CTRL: POSTINIT Position

◆ DWT_CTRL_POSTINIT_Pos [3/6]

#define DWT_CTRL_POSTINIT_Pos   5U

DWT CTRL: POSTINIT Position

◆ DWT_CTRL_POSTINIT_Pos [4/6]

#define DWT_CTRL_POSTINIT_Pos   5U

DWT CTRL: POSTINIT Position

◆ DWT_CTRL_POSTINIT_Pos [5/6]

#define DWT_CTRL_POSTINIT_Pos   5U

DWT CTRL: POSTINIT Position

◆ DWT_CTRL_POSTINIT_Pos [6/6]

#define DWT_CTRL_POSTINIT_Pos   5U

DWT CTRL: POSTINIT Position

◆ DWT_CTRL_POSTPRESET_Msk [1/6]

#define DWT_CTRL_POSTPRESET_Msk   (0xFUL << DWT_CTRL_POSTPRESET_Pos)

DWT CTRL: POSTPRESET Mask

◆ DWT_CTRL_POSTPRESET_Msk [2/6]

#define DWT_CTRL_POSTPRESET_Msk   (0xFUL << DWT_CTRL_POSTPRESET_Pos)

DWT CTRL: POSTPRESET Mask

◆ DWT_CTRL_POSTPRESET_Msk [3/6]

#define DWT_CTRL_POSTPRESET_Msk   (0xFUL << DWT_CTRL_POSTPRESET_Pos)

DWT CTRL: POSTPRESET Mask

◆ DWT_CTRL_POSTPRESET_Msk [4/6]

#define DWT_CTRL_POSTPRESET_Msk   (0xFUL << DWT_CTRL_POSTPRESET_Pos)

DWT CTRL: POSTPRESET Mask

◆ DWT_CTRL_POSTPRESET_Msk [5/6]

#define DWT_CTRL_POSTPRESET_Msk   (0xFUL << DWT_CTRL_POSTPRESET_Pos)

DWT CTRL: POSTPRESET Mask

◆ DWT_CTRL_POSTPRESET_Msk [6/6]

#define DWT_CTRL_POSTPRESET_Msk   (0xFUL << DWT_CTRL_POSTPRESET_Pos)

DWT CTRL: POSTPRESET Mask

◆ DWT_CTRL_POSTPRESET_Pos [1/6]

#define DWT_CTRL_POSTPRESET_Pos   1U

DWT CTRL: POSTPRESET Position

◆ DWT_CTRL_POSTPRESET_Pos [2/6]

#define DWT_CTRL_POSTPRESET_Pos   1U

DWT CTRL: POSTPRESET Position

◆ DWT_CTRL_POSTPRESET_Pos [3/6]

#define DWT_CTRL_POSTPRESET_Pos   1U

DWT CTRL: POSTPRESET Position

◆ DWT_CTRL_POSTPRESET_Pos [4/6]

#define DWT_CTRL_POSTPRESET_Pos   1U

DWT CTRL: POSTPRESET Position

◆ DWT_CTRL_POSTPRESET_Pos [5/6]

#define DWT_CTRL_POSTPRESET_Pos   1U

DWT CTRL: POSTPRESET Position

◆ DWT_CTRL_POSTPRESET_Pos [6/6]

#define DWT_CTRL_POSTPRESET_Pos   1U

DWT CTRL: POSTPRESET Position

◆ DWT_CTRL_SLEEPEVTENA_Msk [1/6]

#define DWT_CTRL_SLEEPEVTENA_Msk   (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)

DWT CTRL: SLEEPEVTENA Mask

◆ DWT_CTRL_SLEEPEVTENA_Msk [2/6]

#define DWT_CTRL_SLEEPEVTENA_Msk   (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)

DWT CTRL: SLEEPEVTENA Mask

◆ DWT_CTRL_SLEEPEVTENA_Msk [3/6]

#define DWT_CTRL_SLEEPEVTENA_Msk   (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)

DWT CTRL: SLEEPEVTENA Mask

◆ DWT_CTRL_SLEEPEVTENA_Msk [4/6]

#define DWT_CTRL_SLEEPEVTENA_Msk   (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)

DWT CTRL: SLEEPEVTENA Mask

◆ DWT_CTRL_SLEEPEVTENA_Msk [5/6]

#define DWT_CTRL_SLEEPEVTENA_Msk   (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)

DWT CTRL: SLEEPEVTENA Mask

◆ DWT_CTRL_SLEEPEVTENA_Msk [6/6]

#define DWT_CTRL_SLEEPEVTENA_Msk   (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)

DWT CTRL: SLEEPEVTENA Mask

◆ DWT_CTRL_SLEEPEVTENA_Pos [1/6]

#define DWT_CTRL_SLEEPEVTENA_Pos   19U

DWT CTRL: SLEEPEVTENA Position

◆ DWT_CTRL_SLEEPEVTENA_Pos [2/6]

#define DWT_CTRL_SLEEPEVTENA_Pos   19U

DWT CTRL: SLEEPEVTENA Position

◆ DWT_CTRL_SLEEPEVTENA_Pos [3/6]

#define DWT_CTRL_SLEEPEVTENA_Pos   19U

DWT CTRL: SLEEPEVTENA Position

◆ DWT_CTRL_SLEEPEVTENA_Pos [4/6]

#define DWT_CTRL_SLEEPEVTENA_Pos   19U

DWT CTRL: SLEEPEVTENA Position

◆ DWT_CTRL_SLEEPEVTENA_Pos [5/6]

#define DWT_CTRL_SLEEPEVTENA_Pos   19U

DWT CTRL: SLEEPEVTENA Position

◆ DWT_CTRL_SLEEPEVTENA_Pos [6/6]

#define DWT_CTRL_SLEEPEVTENA_Pos   19U

DWT CTRL: SLEEPEVTENA Position

◆ DWT_CTRL_SYNCTAP_Msk [1/6]

#define DWT_CTRL_SYNCTAP_Msk   (0x3UL << DWT_CTRL_SYNCTAP_Pos)

DWT CTRL: SYNCTAP Mask

◆ DWT_CTRL_SYNCTAP_Msk [2/6]

#define DWT_CTRL_SYNCTAP_Msk   (0x3UL << DWT_CTRL_SYNCTAP_Pos)

DWT CTRL: SYNCTAP Mask

◆ DWT_CTRL_SYNCTAP_Msk [3/6]

#define DWT_CTRL_SYNCTAP_Msk   (0x3UL << DWT_CTRL_SYNCTAP_Pos)

DWT CTRL: SYNCTAP Mask

◆ DWT_CTRL_SYNCTAP_Msk [4/6]

#define DWT_CTRL_SYNCTAP_Msk   (0x3UL << DWT_CTRL_SYNCTAP_Pos)

DWT CTRL: SYNCTAP Mask

◆ DWT_CTRL_SYNCTAP_Msk [5/6]

#define DWT_CTRL_SYNCTAP_Msk   (0x3UL << DWT_CTRL_SYNCTAP_Pos)

DWT CTRL: SYNCTAP Mask

◆ DWT_CTRL_SYNCTAP_Msk [6/6]

#define DWT_CTRL_SYNCTAP_Msk   (0x3UL << DWT_CTRL_SYNCTAP_Pos)

DWT CTRL: SYNCTAP Mask

◆ DWT_CTRL_SYNCTAP_Pos [1/6]

#define DWT_CTRL_SYNCTAP_Pos   10U

DWT CTRL: SYNCTAP Position

◆ DWT_CTRL_SYNCTAP_Pos [2/6]

#define DWT_CTRL_SYNCTAP_Pos   10U

DWT CTRL: SYNCTAP Position

◆ DWT_CTRL_SYNCTAP_Pos [3/6]

#define DWT_CTRL_SYNCTAP_Pos   10U

DWT CTRL: SYNCTAP Position

◆ DWT_CTRL_SYNCTAP_Pos [4/6]

#define DWT_CTRL_SYNCTAP_Pos   10U

DWT CTRL: SYNCTAP Position

◆ DWT_CTRL_SYNCTAP_Pos [5/6]

#define DWT_CTRL_SYNCTAP_Pos   10U

DWT CTRL: SYNCTAP Position

◆ DWT_CTRL_SYNCTAP_Pos [6/6]

#define DWT_CTRL_SYNCTAP_Pos   10U

DWT CTRL: SYNCTAP Position

◆ DWT_EXCCNT_EXCCNT_Msk [1/6]

#define DWT_EXCCNT_EXCCNT_Msk   (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)

DWT EXCCNT: EXCCNT Mask

◆ DWT_EXCCNT_EXCCNT_Msk [2/6]

#define DWT_EXCCNT_EXCCNT_Msk   (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)

DWT EXCCNT: EXCCNT Mask

◆ DWT_EXCCNT_EXCCNT_Msk [3/6]

#define DWT_EXCCNT_EXCCNT_Msk   (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)

DWT EXCCNT: EXCCNT Mask

◆ DWT_EXCCNT_EXCCNT_Msk [4/6]

#define DWT_EXCCNT_EXCCNT_Msk   (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)

DWT EXCCNT: EXCCNT Mask

◆ DWT_EXCCNT_EXCCNT_Msk [5/6]

#define DWT_EXCCNT_EXCCNT_Msk   (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)

DWT EXCCNT: EXCCNT Mask

◆ DWT_EXCCNT_EXCCNT_Msk [6/6]

#define DWT_EXCCNT_EXCCNT_Msk   (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)

DWT EXCCNT: EXCCNT Mask

◆ DWT_EXCCNT_EXCCNT_Pos [1/6]

#define DWT_EXCCNT_EXCCNT_Pos   0U

DWT EXCCNT: EXCCNT Position

◆ DWT_EXCCNT_EXCCNT_Pos [2/6]

#define DWT_EXCCNT_EXCCNT_Pos   0U

DWT EXCCNT: EXCCNT Position

◆ DWT_EXCCNT_EXCCNT_Pos [3/6]

#define DWT_EXCCNT_EXCCNT_Pos   0U

DWT EXCCNT: EXCCNT Position

◆ DWT_EXCCNT_EXCCNT_Pos [4/6]

#define DWT_EXCCNT_EXCCNT_Pos   0U

DWT EXCCNT: EXCCNT Position

◆ DWT_EXCCNT_EXCCNT_Pos [5/6]

#define DWT_EXCCNT_EXCCNT_Pos   0U

DWT EXCCNT: EXCCNT Position

◆ DWT_EXCCNT_EXCCNT_Pos [6/6]

#define DWT_EXCCNT_EXCCNT_Pos   0U

DWT EXCCNT: EXCCNT Position

◆ DWT_FOLDCNT_FOLDCNT_Msk [1/6]

#define DWT_FOLDCNT_FOLDCNT_Msk   (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)

DWT FOLDCNT: FOLDCNT Mask

◆ DWT_FOLDCNT_FOLDCNT_Msk [2/6]

#define DWT_FOLDCNT_FOLDCNT_Msk   (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)

DWT FOLDCNT: FOLDCNT Mask

◆ DWT_FOLDCNT_FOLDCNT_Msk [3/6]

#define DWT_FOLDCNT_FOLDCNT_Msk   (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)

DWT FOLDCNT: FOLDCNT Mask

◆ DWT_FOLDCNT_FOLDCNT_Msk [4/6]

#define DWT_FOLDCNT_FOLDCNT_Msk   (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)

DWT FOLDCNT: FOLDCNT Mask

◆ DWT_FOLDCNT_FOLDCNT_Msk [5/6]

#define DWT_FOLDCNT_FOLDCNT_Msk   (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)

DWT FOLDCNT: FOLDCNT Mask

◆ DWT_FOLDCNT_FOLDCNT_Msk [6/6]

#define DWT_FOLDCNT_FOLDCNT_Msk   (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)

DWT FOLDCNT: FOLDCNT Mask

◆ DWT_FOLDCNT_FOLDCNT_Pos [1/6]

#define DWT_FOLDCNT_FOLDCNT_Pos   0U

DWT FOLDCNT: FOLDCNT Position

◆ DWT_FOLDCNT_FOLDCNT_Pos [2/6]

#define DWT_FOLDCNT_FOLDCNT_Pos   0U

DWT FOLDCNT: FOLDCNT Position

◆ DWT_FOLDCNT_FOLDCNT_Pos [3/6]

#define DWT_FOLDCNT_FOLDCNT_Pos   0U

DWT FOLDCNT: FOLDCNT Position

◆ DWT_FOLDCNT_FOLDCNT_Pos [4/6]

#define DWT_FOLDCNT_FOLDCNT_Pos   0U

DWT FOLDCNT: FOLDCNT Position

◆ DWT_FOLDCNT_FOLDCNT_Pos [5/6]

#define DWT_FOLDCNT_FOLDCNT_Pos   0U

DWT FOLDCNT: FOLDCNT Position

◆ DWT_FOLDCNT_FOLDCNT_Pos [6/6]

#define DWT_FOLDCNT_FOLDCNT_Pos   0U

DWT FOLDCNT: FOLDCNT Position

◆ DWT_FUNCTION_ACTION_Msk

#define DWT_FUNCTION_ACTION_Msk   (0x1UL << DWT_FUNCTION_ACTION_Pos)

DWT FUNCTION: ACTION Mask

◆ DWT_FUNCTION_ACTION_Pos

#define DWT_FUNCTION_ACTION_Pos   4U

DWT FUNCTION: ACTION Position

◆ DWT_FUNCTION_CYCMATCH_Msk [1/4]

#define DWT_FUNCTION_CYCMATCH_Msk   (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)

DWT FUNCTION: CYCMATCH Mask

◆ DWT_FUNCTION_CYCMATCH_Msk [2/4]

#define DWT_FUNCTION_CYCMATCH_Msk   (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)

DWT FUNCTION: CYCMATCH Mask

◆ DWT_FUNCTION_CYCMATCH_Msk [3/4]

#define DWT_FUNCTION_CYCMATCH_Msk   (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)

DWT FUNCTION: CYCMATCH Mask

◆ DWT_FUNCTION_CYCMATCH_Msk [4/4]

#define DWT_FUNCTION_CYCMATCH_Msk   (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)

DWT FUNCTION: CYCMATCH Mask

◆ DWT_FUNCTION_CYCMATCH_Pos [1/4]

#define DWT_FUNCTION_CYCMATCH_Pos   7U

DWT FUNCTION: CYCMATCH Position

◆ DWT_FUNCTION_CYCMATCH_Pos [2/4]

#define DWT_FUNCTION_CYCMATCH_Pos   7U

DWT FUNCTION: CYCMATCH Position

◆ DWT_FUNCTION_CYCMATCH_Pos [3/4]

#define DWT_FUNCTION_CYCMATCH_Pos   7U

DWT FUNCTION: CYCMATCH Position

◆ DWT_FUNCTION_CYCMATCH_Pos [4/4]

#define DWT_FUNCTION_CYCMATCH_Pos   7U

DWT FUNCTION: CYCMATCH Position

◆ DWT_FUNCTION_DATAVADDR0_Msk [1/4]

#define DWT_FUNCTION_DATAVADDR0_Msk   (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)

DWT FUNCTION: DATAVADDR0 Mask

◆ DWT_FUNCTION_DATAVADDR0_Msk [2/4]

#define DWT_FUNCTION_DATAVADDR0_Msk   (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)

DWT FUNCTION: DATAVADDR0 Mask

◆ DWT_FUNCTION_DATAVADDR0_Msk [3/4]

#define DWT_FUNCTION_DATAVADDR0_Msk   (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)

DWT FUNCTION: DATAVADDR0 Mask

◆ DWT_FUNCTION_DATAVADDR0_Msk [4/4]

#define DWT_FUNCTION_DATAVADDR0_Msk   (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)

DWT FUNCTION: DATAVADDR0 Mask

◆ DWT_FUNCTION_DATAVADDR0_Pos [1/4]

#define DWT_FUNCTION_DATAVADDR0_Pos   12U

DWT FUNCTION: DATAVADDR0 Position

◆ DWT_FUNCTION_DATAVADDR0_Pos [2/4]

#define DWT_FUNCTION_DATAVADDR0_Pos   12U

DWT FUNCTION: DATAVADDR0 Position

◆ DWT_FUNCTION_DATAVADDR0_Pos [3/4]

#define DWT_FUNCTION_DATAVADDR0_Pos   12U

DWT FUNCTION: DATAVADDR0 Position

◆ DWT_FUNCTION_DATAVADDR0_Pos [4/4]

#define DWT_FUNCTION_DATAVADDR0_Pos   12U

DWT FUNCTION: DATAVADDR0 Position

◆ DWT_FUNCTION_DATAVADDR1_Msk [1/4]

#define DWT_FUNCTION_DATAVADDR1_Msk   (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)

DWT FUNCTION: DATAVADDR1 Mask

◆ DWT_FUNCTION_DATAVADDR1_Msk [2/4]

#define DWT_FUNCTION_DATAVADDR1_Msk   (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)

DWT FUNCTION: DATAVADDR1 Mask

◆ DWT_FUNCTION_DATAVADDR1_Msk [3/4]

#define DWT_FUNCTION_DATAVADDR1_Msk   (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)

DWT FUNCTION: DATAVADDR1 Mask

◆ DWT_FUNCTION_DATAVADDR1_Msk [4/4]

#define DWT_FUNCTION_DATAVADDR1_Msk   (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)

DWT FUNCTION: DATAVADDR1 Mask

◆ DWT_FUNCTION_DATAVADDR1_Pos [1/4]

#define DWT_FUNCTION_DATAVADDR1_Pos   16U

DWT FUNCTION: DATAVADDR1 Position

◆ DWT_FUNCTION_DATAVADDR1_Pos [2/4]

#define DWT_FUNCTION_DATAVADDR1_Pos   16U

DWT FUNCTION: DATAVADDR1 Position

◆ DWT_FUNCTION_DATAVADDR1_Pos [3/4]

#define DWT_FUNCTION_DATAVADDR1_Pos   16U

DWT FUNCTION: DATAVADDR1 Position

◆ DWT_FUNCTION_DATAVADDR1_Pos [4/4]

#define DWT_FUNCTION_DATAVADDR1_Pos   16U

DWT FUNCTION: DATAVADDR1 Position

◆ DWT_FUNCTION_DATAVMATCH_Msk [1/4]

#define DWT_FUNCTION_DATAVMATCH_Msk   (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)

DWT FUNCTION: DATAVMATCH Mask

◆ DWT_FUNCTION_DATAVMATCH_Msk [2/4]

#define DWT_FUNCTION_DATAVMATCH_Msk   (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)

DWT FUNCTION: DATAVMATCH Mask

◆ DWT_FUNCTION_DATAVMATCH_Msk [3/4]

#define DWT_FUNCTION_DATAVMATCH_Msk   (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)

DWT FUNCTION: DATAVMATCH Mask

◆ DWT_FUNCTION_DATAVMATCH_Msk [4/4]

#define DWT_FUNCTION_DATAVMATCH_Msk   (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)

DWT FUNCTION: DATAVMATCH Mask

◆ DWT_FUNCTION_DATAVMATCH_Pos [1/4]

#define DWT_FUNCTION_DATAVMATCH_Pos   8U

DWT FUNCTION: DATAVMATCH Position

◆ DWT_FUNCTION_DATAVMATCH_Pos [2/4]

#define DWT_FUNCTION_DATAVMATCH_Pos   8U

DWT FUNCTION: DATAVMATCH Position

◆ DWT_FUNCTION_DATAVMATCH_Pos [3/4]

#define DWT_FUNCTION_DATAVMATCH_Pos   8U

DWT FUNCTION: DATAVMATCH Position

◆ DWT_FUNCTION_DATAVMATCH_Pos [4/4]

#define DWT_FUNCTION_DATAVMATCH_Pos   8U

DWT FUNCTION: DATAVMATCH Position

◆ DWT_FUNCTION_DATAVSIZE_Msk [1/8]

#define DWT_FUNCTION_DATAVSIZE_Msk   (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)

DWT FUNCTION: DATAVSIZE Mask

◆ DWT_FUNCTION_DATAVSIZE_Msk [2/8]

#define DWT_FUNCTION_DATAVSIZE_Msk   (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)

DWT FUNCTION: DATAVSIZE Mask

◆ DWT_FUNCTION_DATAVSIZE_Msk [3/8]

#define DWT_FUNCTION_DATAVSIZE_Msk   (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)

DWT FUNCTION: DATAVSIZE Mask

◆ DWT_FUNCTION_DATAVSIZE_Msk [4/8]

#define DWT_FUNCTION_DATAVSIZE_Msk   (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)

DWT FUNCTION: DATAVSIZE Mask

◆ DWT_FUNCTION_DATAVSIZE_Msk [5/8]

#define DWT_FUNCTION_DATAVSIZE_Msk   (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)

DWT FUNCTION: DATAVSIZE Mask

◆ DWT_FUNCTION_DATAVSIZE_Msk [6/8]

#define DWT_FUNCTION_DATAVSIZE_Msk   (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)

DWT FUNCTION: DATAVSIZE Mask

◆ DWT_FUNCTION_DATAVSIZE_Msk [7/8]

#define DWT_FUNCTION_DATAVSIZE_Msk   (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)

DWT FUNCTION: DATAVSIZE Mask

◆ DWT_FUNCTION_DATAVSIZE_Msk [8/8]

#define DWT_FUNCTION_DATAVSIZE_Msk   (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)

DWT FUNCTION: DATAVSIZE Mask

◆ DWT_FUNCTION_DATAVSIZE_Pos [1/8]

#define DWT_FUNCTION_DATAVSIZE_Pos   10U

DWT FUNCTION: DATAVSIZE Position

◆ DWT_FUNCTION_DATAVSIZE_Pos [2/8]

#define DWT_FUNCTION_DATAVSIZE_Pos   10U

DWT FUNCTION: DATAVSIZE Position

◆ DWT_FUNCTION_DATAVSIZE_Pos [3/8]

#define DWT_FUNCTION_DATAVSIZE_Pos   10U

DWT FUNCTION: DATAVSIZE Position

◆ DWT_FUNCTION_DATAVSIZE_Pos [4/8]

#define DWT_FUNCTION_DATAVSIZE_Pos   10U

DWT FUNCTION: DATAVSIZE Position

◆ DWT_FUNCTION_DATAVSIZE_Pos [5/8]

#define DWT_FUNCTION_DATAVSIZE_Pos   10U

DWT FUNCTION: DATAVSIZE Position

◆ DWT_FUNCTION_DATAVSIZE_Pos [6/8]

#define DWT_FUNCTION_DATAVSIZE_Pos   10U

DWT FUNCTION: DATAVSIZE Position

◆ DWT_FUNCTION_DATAVSIZE_Pos [7/8]

#define DWT_FUNCTION_DATAVSIZE_Pos   10U

DWT FUNCTION: DATAVSIZE Position

◆ DWT_FUNCTION_DATAVSIZE_Pos [8/8]

#define DWT_FUNCTION_DATAVSIZE_Pos   10U

DWT FUNCTION: DATAVSIZE Position

◆ DWT_FUNCTION_EMITRANGE_Msk [1/4]

#define DWT_FUNCTION_EMITRANGE_Msk   (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)

DWT FUNCTION: EMITRANGE Mask

◆ DWT_FUNCTION_EMITRANGE_Msk [2/4]

#define DWT_FUNCTION_EMITRANGE_Msk   (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)

DWT FUNCTION: EMITRANGE Mask

◆ DWT_FUNCTION_EMITRANGE_Msk [3/4]

#define DWT_FUNCTION_EMITRANGE_Msk   (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)

DWT FUNCTION: EMITRANGE Mask

◆ DWT_FUNCTION_EMITRANGE_Msk [4/4]

#define DWT_FUNCTION_EMITRANGE_Msk   (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)

DWT FUNCTION: EMITRANGE Mask

◆ DWT_FUNCTION_EMITRANGE_Pos [1/4]

#define DWT_FUNCTION_EMITRANGE_Pos   5U

DWT FUNCTION: EMITRANGE Position

◆ DWT_FUNCTION_EMITRANGE_Pos [2/4]

#define DWT_FUNCTION_EMITRANGE_Pos   5U

DWT FUNCTION: EMITRANGE Position

◆ DWT_FUNCTION_EMITRANGE_Pos [3/4]

#define DWT_FUNCTION_EMITRANGE_Pos   5U

DWT FUNCTION: EMITRANGE Position

◆ DWT_FUNCTION_EMITRANGE_Pos [4/4]

#define DWT_FUNCTION_EMITRANGE_Pos   5U

DWT FUNCTION: EMITRANGE Position

◆ DWT_FUNCTION_FUNCTION_Msk [1/4]

#define DWT_FUNCTION_FUNCTION_Msk   (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)

DWT FUNCTION: FUNCTION Mask

◆ DWT_FUNCTION_FUNCTION_Msk [2/4]

#define DWT_FUNCTION_FUNCTION_Msk   (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)

DWT FUNCTION: FUNCTION Mask

◆ DWT_FUNCTION_FUNCTION_Msk [3/4]

#define DWT_FUNCTION_FUNCTION_Msk   (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)

DWT FUNCTION: FUNCTION Mask

◆ DWT_FUNCTION_FUNCTION_Msk [4/4]

#define DWT_FUNCTION_FUNCTION_Msk   (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)

DWT FUNCTION: FUNCTION Mask

◆ DWT_FUNCTION_FUNCTION_Pos [1/4]

#define DWT_FUNCTION_FUNCTION_Pos   0U

DWT FUNCTION: FUNCTION Position

◆ DWT_FUNCTION_FUNCTION_Pos [2/4]

#define DWT_FUNCTION_FUNCTION_Pos   0U

DWT FUNCTION: FUNCTION Position

◆ DWT_FUNCTION_FUNCTION_Pos [3/4]

#define DWT_FUNCTION_FUNCTION_Pos   0U

DWT FUNCTION: FUNCTION Position

◆ DWT_FUNCTION_FUNCTION_Pos [4/4]

#define DWT_FUNCTION_FUNCTION_Pos   0U

DWT FUNCTION: FUNCTION Position

◆ DWT_FUNCTION_ID_Msk

#define DWT_FUNCTION_ID_Msk   (0x1FUL << DWT_FUNCTION_ID_Pos)

DWT FUNCTION: ID Mask

◆ DWT_FUNCTION_ID_Pos

#define DWT_FUNCTION_ID_Pos   27U

DWT FUNCTION: ID Position

◆ DWT_FUNCTION_LNK1ENA_Msk [1/4]

#define DWT_FUNCTION_LNK1ENA_Msk   (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)

DWT FUNCTION: LNK1ENA Mask

◆ DWT_FUNCTION_LNK1ENA_Msk [2/4]

#define DWT_FUNCTION_LNK1ENA_Msk   (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)

DWT FUNCTION: LNK1ENA Mask

◆ DWT_FUNCTION_LNK1ENA_Msk [3/4]

#define DWT_FUNCTION_LNK1ENA_Msk   (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)

DWT FUNCTION: LNK1ENA Mask

◆ DWT_FUNCTION_LNK1ENA_Msk [4/4]

#define DWT_FUNCTION_LNK1ENA_Msk   (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)

DWT FUNCTION: LNK1ENA Mask

◆ DWT_FUNCTION_LNK1ENA_Pos [1/4]

#define DWT_FUNCTION_LNK1ENA_Pos   9U

DWT FUNCTION: LNK1ENA Position

◆ DWT_FUNCTION_LNK1ENA_Pos [2/4]

#define DWT_FUNCTION_LNK1ENA_Pos   9U

DWT FUNCTION: LNK1ENA Position

◆ DWT_FUNCTION_LNK1ENA_Pos [3/4]

#define DWT_FUNCTION_LNK1ENA_Pos   9U

DWT FUNCTION: LNK1ENA Position

◆ DWT_FUNCTION_LNK1ENA_Pos [4/4]

#define DWT_FUNCTION_LNK1ENA_Pos   9U

DWT FUNCTION: LNK1ENA Position

◆ DWT_FUNCTION_MATCH_Msk

#define DWT_FUNCTION_MATCH_Msk   (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)

DWT FUNCTION: MATCH Mask

◆ DWT_FUNCTION_MATCH_Pos

#define DWT_FUNCTION_MATCH_Pos   0U

DWT FUNCTION: MATCH Position

◆ DWT_FUNCTION_MATCHED_Msk [1/8]

#define DWT_FUNCTION_MATCHED_Msk   (0x1UL << DWT_FUNCTION_MATCHED_Pos)

DWT FUNCTION: MATCHED Mask

◆ DWT_FUNCTION_MATCHED_Msk [2/8]

#define DWT_FUNCTION_MATCHED_Msk   (0x1UL << DWT_FUNCTION_MATCHED_Pos)

DWT FUNCTION: MATCHED Mask

◆ DWT_FUNCTION_MATCHED_Msk [3/8]

#define DWT_FUNCTION_MATCHED_Msk   (0x1UL << DWT_FUNCTION_MATCHED_Pos)

DWT FUNCTION: MATCHED Mask

◆ DWT_FUNCTION_MATCHED_Msk [4/8]

#define DWT_FUNCTION_MATCHED_Msk   (0x1UL << DWT_FUNCTION_MATCHED_Pos)

DWT FUNCTION: MATCHED Mask

◆ DWT_FUNCTION_MATCHED_Msk [5/8]

#define DWT_FUNCTION_MATCHED_Msk   (0x1UL << DWT_FUNCTION_MATCHED_Pos)

DWT FUNCTION: MATCHED Mask

◆ DWT_FUNCTION_MATCHED_Msk [6/8]

#define DWT_FUNCTION_MATCHED_Msk   (0x1UL << DWT_FUNCTION_MATCHED_Pos)

DWT FUNCTION: MATCHED Mask

◆ DWT_FUNCTION_MATCHED_Msk [7/8]

#define DWT_FUNCTION_MATCHED_Msk   (0x1UL << DWT_FUNCTION_MATCHED_Pos)

DWT FUNCTION: MATCHED Mask

◆ DWT_FUNCTION_MATCHED_Msk [8/8]

#define DWT_FUNCTION_MATCHED_Msk   (0x1UL << DWT_FUNCTION_MATCHED_Pos)

DWT FUNCTION: MATCHED Mask

◆ DWT_FUNCTION_MATCHED_Pos [1/8]

#define DWT_FUNCTION_MATCHED_Pos   24U

DWT FUNCTION: MATCHED Position

◆ DWT_FUNCTION_MATCHED_Pos [2/8]

#define DWT_FUNCTION_MATCHED_Pos   24U

DWT FUNCTION: MATCHED Position

◆ DWT_FUNCTION_MATCHED_Pos [3/8]

#define DWT_FUNCTION_MATCHED_Pos   24U

DWT FUNCTION: MATCHED Position

◆ DWT_FUNCTION_MATCHED_Pos [4/8]

#define DWT_FUNCTION_MATCHED_Pos   24U

DWT FUNCTION: MATCHED Position

◆ DWT_FUNCTION_MATCHED_Pos [5/8]

#define DWT_FUNCTION_MATCHED_Pos   24U

DWT FUNCTION: MATCHED Position

◆ DWT_FUNCTION_MATCHED_Pos [6/8]

#define DWT_FUNCTION_MATCHED_Pos   24U

DWT FUNCTION: MATCHED Position

◆ DWT_FUNCTION_MATCHED_Pos [7/8]

#define DWT_FUNCTION_MATCHED_Pos   24U

DWT FUNCTION: MATCHED Position

◆ DWT_FUNCTION_MATCHED_Pos [8/8]

#define DWT_FUNCTION_MATCHED_Pos   24U

DWT FUNCTION: MATCHED Position

◆ DWT_LSUCNT_LSUCNT_Msk [1/6]

#define DWT_LSUCNT_LSUCNT_Msk   (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)

DWT LSUCNT: LSUCNT Mask

◆ DWT_LSUCNT_LSUCNT_Msk [2/6]

#define DWT_LSUCNT_LSUCNT_Msk   (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)

DWT LSUCNT: LSUCNT Mask

◆ DWT_LSUCNT_LSUCNT_Msk [3/6]

#define DWT_LSUCNT_LSUCNT_Msk   (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)

DWT LSUCNT: LSUCNT Mask

◆ DWT_LSUCNT_LSUCNT_Msk [4/6]

#define DWT_LSUCNT_LSUCNT_Msk   (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)

DWT LSUCNT: LSUCNT Mask

◆ DWT_LSUCNT_LSUCNT_Msk [5/6]

#define DWT_LSUCNT_LSUCNT_Msk   (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)

DWT LSUCNT: LSUCNT Mask

◆ DWT_LSUCNT_LSUCNT_Msk [6/6]

#define DWT_LSUCNT_LSUCNT_Msk   (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)

DWT LSUCNT: LSUCNT Mask

◆ DWT_LSUCNT_LSUCNT_Pos [1/6]

#define DWT_LSUCNT_LSUCNT_Pos   0U

DWT LSUCNT: LSUCNT Position

◆ DWT_LSUCNT_LSUCNT_Pos [2/6]

#define DWT_LSUCNT_LSUCNT_Pos   0U

DWT LSUCNT: LSUCNT Position

◆ DWT_LSUCNT_LSUCNT_Pos [3/6]

#define DWT_LSUCNT_LSUCNT_Pos   0U

DWT LSUCNT: LSUCNT Position

◆ DWT_LSUCNT_LSUCNT_Pos [4/6]

#define DWT_LSUCNT_LSUCNT_Pos   0U

DWT LSUCNT: LSUCNT Position

◆ DWT_LSUCNT_LSUCNT_Pos [5/6]

#define DWT_LSUCNT_LSUCNT_Pos   0U

DWT LSUCNT: LSUCNT Position

◆ DWT_LSUCNT_LSUCNT_Pos [6/6]

#define DWT_LSUCNT_LSUCNT_Pos   0U

DWT LSUCNT: LSUCNT Position

◆ DWT_MASK_MASK_Msk [1/4]

#define DWT_MASK_MASK_Msk   (0x1FUL /*<< DWT_MASK_MASK_Pos*/)

DWT MASK: MASK Mask

◆ DWT_MASK_MASK_Msk [2/4]

#define DWT_MASK_MASK_Msk   (0x1FUL /*<< DWT_MASK_MASK_Pos*/)

DWT MASK: MASK Mask

◆ DWT_MASK_MASK_Msk [3/4]

#define DWT_MASK_MASK_Msk   (0x1FUL /*<< DWT_MASK_MASK_Pos*/)

DWT MASK: MASK Mask

◆ DWT_MASK_MASK_Msk [4/4]

#define DWT_MASK_MASK_Msk   (0x1FUL /*<< DWT_MASK_MASK_Pos*/)

DWT MASK: MASK Mask

◆ DWT_MASK_MASK_Pos [1/4]

#define DWT_MASK_MASK_Pos   0U

DWT MASK: MASK Position

◆ DWT_MASK_MASK_Pos [2/4]

#define DWT_MASK_MASK_Pos   0U

DWT MASK: MASK Position

◆ DWT_MASK_MASK_Pos [3/4]

#define DWT_MASK_MASK_Pos   0U

DWT MASK: MASK Position

◆ DWT_MASK_MASK_Pos [4/4]

#define DWT_MASK_MASK_Pos   0U

DWT MASK: MASK Position

◆ DWT_SLEEPCNT_SLEEPCNT_Msk [1/6]

#define DWT_SLEEPCNT_SLEEPCNT_Msk   (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)

DWT SLEEPCNT: SLEEPCNT Mask

◆ DWT_SLEEPCNT_SLEEPCNT_Msk [2/6]

#define DWT_SLEEPCNT_SLEEPCNT_Msk   (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)

DWT SLEEPCNT: SLEEPCNT Mask

◆ DWT_SLEEPCNT_SLEEPCNT_Msk [3/6]

#define DWT_SLEEPCNT_SLEEPCNT_Msk   (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)

DWT SLEEPCNT: SLEEPCNT Mask

◆ DWT_SLEEPCNT_SLEEPCNT_Msk [4/6]

#define DWT_SLEEPCNT_SLEEPCNT_Msk   (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)

DWT SLEEPCNT: SLEEPCNT Mask

◆ DWT_SLEEPCNT_SLEEPCNT_Msk [5/6]

#define DWT_SLEEPCNT_SLEEPCNT_Msk   (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)

DWT SLEEPCNT: SLEEPCNT Mask

◆ DWT_SLEEPCNT_SLEEPCNT_Msk [6/6]

#define DWT_SLEEPCNT_SLEEPCNT_Msk   (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)

DWT SLEEPCNT: SLEEPCNT Mask

◆ DWT_SLEEPCNT_SLEEPCNT_Pos [1/6]

#define DWT_SLEEPCNT_SLEEPCNT_Pos   0U

DWT SLEEPCNT: SLEEPCNT Position

◆ DWT_SLEEPCNT_SLEEPCNT_Pos [2/6]

#define DWT_SLEEPCNT_SLEEPCNT_Pos   0U

DWT SLEEPCNT: SLEEPCNT Position

◆ DWT_SLEEPCNT_SLEEPCNT_Pos [3/6]

#define DWT_SLEEPCNT_SLEEPCNT_Pos   0U

DWT SLEEPCNT: SLEEPCNT Position

◆ DWT_SLEEPCNT_SLEEPCNT_Pos [4/6]

#define DWT_SLEEPCNT_SLEEPCNT_Pos   0U

DWT SLEEPCNT: SLEEPCNT Position

◆ DWT_SLEEPCNT_SLEEPCNT_Pos [5/6]

#define DWT_SLEEPCNT_SLEEPCNT_Pos   0U

DWT SLEEPCNT: SLEEPCNT Position

◆ DWT_SLEEPCNT_SLEEPCNT_Pos [6/6]

#define DWT_SLEEPCNT_SLEEPCNT_Pos   0U

DWT SLEEPCNT: SLEEPCNT Position

◆ FPU [1/4]

#define FPU   ((FPU_Type *) FPU_BASE )

Floating Point Unit

◆ FPU [2/4]

#define FPU   ((FPU_Type *) FPU_BASE )

Floating Point Unit

◆ FPU [3/4]

#define FPU   ((FPU_Type *) FPU_BASE )

Floating Point Unit

◆ FPU [4/4]

#define FPU   ((FPU_Type *) FPU_BASE )

Floating Point Unit

◆ FPU_BASE [1/4]

#define FPU_BASE   (SCS_BASE + 0x0F30UL)

Floating Point Unit

◆ FPU_BASE [2/4]

#define FPU_BASE   (SCS_BASE + 0x0F30UL)

Floating Point Unit

◆ FPU_BASE [3/4]

#define FPU_BASE   (SCS_BASE + 0x0F30UL)

Floating Point Unit

◆ FPU_BASE [4/4]

#define FPU_BASE   (SCS_BASE + 0x0F30UL)

Floating Point Unit

◆ FPU_FPCAR_ADDRESS_Msk [1/4]

#define FPU_FPCAR_ADDRESS_Msk   (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

FPCAR: ADDRESS bit Mask

◆ FPU_FPCAR_ADDRESS_Msk [2/4]

#define FPU_FPCAR_ADDRESS_Msk   (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

FPCAR: ADDRESS bit Mask

◆ FPU_FPCAR_ADDRESS_Msk [3/4]

#define FPU_FPCAR_ADDRESS_Msk   (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

FPCAR: ADDRESS bit Mask

◆ FPU_FPCAR_ADDRESS_Msk [4/4]

#define FPU_FPCAR_ADDRESS_Msk   (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

FPCAR: ADDRESS bit Mask

◆ FPU_FPCAR_ADDRESS_Pos [1/4]

#define FPU_FPCAR_ADDRESS_Pos   3U

FPCAR: ADDRESS bit Position

◆ FPU_FPCAR_ADDRESS_Pos [2/4]

#define FPU_FPCAR_ADDRESS_Pos   3U

FPCAR: ADDRESS bit Position

◆ FPU_FPCAR_ADDRESS_Pos [3/4]

#define FPU_FPCAR_ADDRESS_Pos   3U

FPCAR: ADDRESS bit Position

◆ FPU_FPCAR_ADDRESS_Pos [4/4]

#define FPU_FPCAR_ADDRESS_Pos   3U

FPCAR: ADDRESS bit Position

◆ FPU_FPCCR_ASPEN_Msk [1/4]

#define FPU_FPCCR_ASPEN_Msk   (1UL << FPU_FPCCR_ASPEN_Pos)

FPCCR: ASPEN bit Mask

◆ FPU_FPCCR_ASPEN_Msk [2/4]

#define FPU_FPCCR_ASPEN_Msk   (1UL << FPU_FPCCR_ASPEN_Pos)

FPCCR: ASPEN bit Mask

◆ FPU_FPCCR_ASPEN_Msk [3/4]

#define FPU_FPCCR_ASPEN_Msk   (1UL << FPU_FPCCR_ASPEN_Pos)

FPCCR: ASPEN bit Mask

◆ FPU_FPCCR_ASPEN_Msk [4/4]

#define FPU_FPCCR_ASPEN_Msk   (1UL << FPU_FPCCR_ASPEN_Pos)

FPCCR: ASPEN bit Mask

◆ FPU_FPCCR_ASPEN_Pos [1/4]

#define FPU_FPCCR_ASPEN_Pos   31U

FPCCR: ASPEN bit Position

◆ FPU_FPCCR_ASPEN_Pos [2/4]

#define FPU_FPCCR_ASPEN_Pos   31U

FPCCR: ASPEN bit Position

◆ FPU_FPCCR_ASPEN_Pos [3/4]

#define FPU_FPCCR_ASPEN_Pos   31U

FPCCR: ASPEN bit Position

◆ FPU_FPCCR_ASPEN_Pos [4/4]

#define FPU_FPCCR_ASPEN_Pos   31U

FPCCR: ASPEN bit Position

◆ FPU_FPCCR_BFRDY_Msk [1/4]

#define FPU_FPCCR_BFRDY_Msk   (1UL << FPU_FPCCR_BFRDY_Pos)

FPCCR: BFRDY bit Mask

◆ FPU_FPCCR_BFRDY_Msk [2/4]

#define FPU_FPCCR_BFRDY_Msk   (1UL << FPU_FPCCR_BFRDY_Pos)

FPCCR: BFRDY bit Mask

◆ FPU_FPCCR_BFRDY_Msk [3/4]

#define FPU_FPCCR_BFRDY_Msk   (1UL << FPU_FPCCR_BFRDY_Pos)

FPCCR: BFRDY bit Mask

◆ FPU_FPCCR_BFRDY_Msk [4/4]

#define FPU_FPCCR_BFRDY_Msk   (1UL << FPU_FPCCR_BFRDY_Pos)

FPCCR: BFRDY bit Mask

◆ FPU_FPCCR_BFRDY_Pos [1/4]

#define FPU_FPCCR_BFRDY_Pos   6U

FPCCR: BFRDY Position

◆ FPU_FPCCR_BFRDY_Pos [2/4]

#define FPU_FPCCR_BFRDY_Pos   6U

FPCCR: BFRDY Position

◆ FPU_FPCCR_BFRDY_Pos [3/4]

#define FPU_FPCCR_BFRDY_Pos   6U

FPCCR: BFRDY Position

◆ FPU_FPCCR_BFRDY_Pos [4/4]

#define FPU_FPCCR_BFRDY_Pos   6U

FPCCR: BFRDY Position

◆ FPU_FPCCR_CLRONRET_Msk [1/2]

#define FPU_FPCCR_CLRONRET_Msk   (1UL << FPU_FPCCR_CLRONRET_Pos)

FPCCR: CLRONRET bit Mask

◆ FPU_FPCCR_CLRONRET_Msk [2/2]

#define FPU_FPCCR_CLRONRET_Msk   (1UL << FPU_FPCCR_CLRONRET_Pos)

FPCCR: CLRONRET bit Mask

◆ FPU_FPCCR_CLRONRET_Pos [1/2]

#define FPU_FPCCR_CLRONRET_Pos   28U

FPCCR: CLRONRET Position

◆ FPU_FPCCR_CLRONRET_Pos [2/2]

#define FPU_FPCCR_CLRONRET_Pos   28U

FPCCR: CLRONRET Position

◆ FPU_FPCCR_CLRONRETS_Msk [1/2]

#define FPU_FPCCR_CLRONRETS_Msk   (1UL << FPU_FPCCR_CLRONRETS_Pos)

FPCCR: CLRONRETS bit Mask

◆ FPU_FPCCR_CLRONRETS_Msk [2/2]

#define FPU_FPCCR_CLRONRETS_Msk   (1UL << FPU_FPCCR_CLRONRETS_Pos)

FPCCR: CLRONRETS bit Mask

◆ FPU_FPCCR_CLRONRETS_Pos [1/2]

#define FPU_FPCCR_CLRONRETS_Pos   27U

FPCCR: CLRONRETS Position

◆ FPU_FPCCR_CLRONRETS_Pos [2/2]

#define FPU_FPCCR_CLRONRETS_Pos   27U

FPCCR: CLRONRETS Position

◆ FPU_FPCCR_HFRDY_Msk [1/4]

#define FPU_FPCCR_HFRDY_Msk   (1UL << FPU_FPCCR_HFRDY_Pos)

FPCCR: HFRDY bit Mask

◆ FPU_FPCCR_HFRDY_Msk [2/4]

#define FPU_FPCCR_HFRDY_Msk   (1UL << FPU_FPCCR_HFRDY_Pos)

FPCCR: HFRDY bit Mask

◆ FPU_FPCCR_HFRDY_Msk [3/4]

#define FPU_FPCCR_HFRDY_Msk   (1UL << FPU_FPCCR_HFRDY_Pos)

FPCCR: HFRDY bit Mask

◆ FPU_FPCCR_HFRDY_Msk [4/4]

#define FPU_FPCCR_HFRDY_Msk   (1UL << FPU_FPCCR_HFRDY_Pos)

FPCCR: HFRDY bit Mask

◆ FPU_FPCCR_HFRDY_Pos [1/4]

#define FPU_FPCCR_HFRDY_Pos   4U

FPCCR: HFRDY Position

◆ FPU_FPCCR_HFRDY_Pos [2/4]

#define FPU_FPCCR_HFRDY_Pos   4U

FPCCR: HFRDY Position

◆ FPU_FPCCR_HFRDY_Pos [3/4]

#define FPU_FPCCR_HFRDY_Pos   4U

FPCCR: HFRDY Position

◆ FPU_FPCCR_HFRDY_Pos [4/4]

#define FPU_FPCCR_HFRDY_Pos   4U

FPCCR: HFRDY Position

◆ FPU_FPCCR_LSPACT_Msk [1/4]

#define FPU_FPCCR_LSPACT_Msk   (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)

FPCCR: Lazy state preservation active bit Mask

◆ FPU_FPCCR_LSPACT_Msk [2/4]

#define FPU_FPCCR_LSPACT_Msk   (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)

FPCCR: Lazy state preservation active bit Mask

◆ FPU_FPCCR_LSPACT_Msk [3/4]

#define FPU_FPCCR_LSPACT_Msk   (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)

FPCCR: Lazy state preservation active bit Mask

◆ FPU_FPCCR_LSPACT_Msk [4/4]

#define FPU_FPCCR_LSPACT_Msk   (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)

FPCCR: Lazy state preservation active bit Mask

◆ FPU_FPCCR_LSPACT_Pos [1/4]

#define FPU_FPCCR_LSPACT_Pos   0U

FPCCR: Lazy state preservation active bit Position

◆ FPU_FPCCR_LSPACT_Pos [2/4]

#define FPU_FPCCR_LSPACT_Pos   0U

FPCCR: Lazy state preservation active bit Position

◆ FPU_FPCCR_LSPACT_Pos [3/4]

#define FPU_FPCCR_LSPACT_Pos   0U

FPCCR: Lazy state preservation active bit Position

◆ FPU_FPCCR_LSPACT_Pos [4/4]

#define FPU_FPCCR_LSPACT_Pos   0U

FPCCR: Lazy state preservation active bit Position

◆ FPU_FPCCR_LSPEN_Msk [1/4]

#define FPU_FPCCR_LSPEN_Msk   (1UL << FPU_FPCCR_LSPEN_Pos)

FPCCR: LSPEN bit Mask

◆ FPU_FPCCR_LSPEN_Msk [2/4]

#define FPU_FPCCR_LSPEN_Msk   (1UL << FPU_FPCCR_LSPEN_Pos)

FPCCR: LSPEN bit Mask

◆ FPU_FPCCR_LSPEN_Msk [3/4]

#define FPU_FPCCR_LSPEN_Msk   (1UL << FPU_FPCCR_LSPEN_Pos)

FPCCR: LSPEN bit Mask

◆ FPU_FPCCR_LSPEN_Msk [4/4]

#define FPU_FPCCR_LSPEN_Msk   (1UL << FPU_FPCCR_LSPEN_Pos)

FPCCR: LSPEN bit Mask

◆ FPU_FPCCR_LSPEN_Pos [1/4]

#define FPU_FPCCR_LSPEN_Pos   30U

FPCCR: LSPEN Position

◆ FPU_FPCCR_LSPEN_Pos [2/4]

#define FPU_FPCCR_LSPEN_Pos   30U

FPCCR: LSPEN Position

◆ FPU_FPCCR_LSPEN_Pos [3/4]

#define FPU_FPCCR_LSPEN_Pos   30U

FPCCR: LSPEN Position

◆ FPU_FPCCR_LSPEN_Pos [4/4]

#define FPU_FPCCR_LSPEN_Pos   30U

FPCCR: LSPEN Position

◆ FPU_FPCCR_LSPENS_Msk [1/2]

#define FPU_FPCCR_LSPENS_Msk   (1UL << FPU_FPCCR_LSPENS_Pos)

FPCCR: LSPENS bit Mask

◆ FPU_FPCCR_LSPENS_Msk [2/2]

#define FPU_FPCCR_LSPENS_Msk   (1UL << FPU_FPCCR_LSPENS_Pos)

FPCCR: LSPENS bit Mask

◆ FPU_FPCCR_LSPENS_Pos [1/2]

#define FPU_FPCCR_LSPENS_Pos   29U

FPCCR: LSPENS Position

◆ FPU_FPCCR_LSPENS_Pos [2/2]

#define FPU_FPCCR_LSPENS_Pos   29U

FPCCR: LSPENS Position

◆ FPU_FPCCR_MMRDY_Msk [1/4]

#define FPU_FPCCR_MMRDY_Msk   (1UL << FPU_FPCCR_MMRDY_Pos)

FPCCR: MMRDY bit Mask

◆ FPU_FPCCR_MMRDY_Msk [2/4]

#define FPU_FPCCR_MMRDY_Msk   (1UL << FPU_FPCCR_MMRDY_Pos)

FPCCR: MMRDY bit Mask

◆ FPU_FPCCR_MMRDY_Msk [3/4]

#define FPU_FPCCR_MMRDY_Msk   (1UL << FPU_FPCCR_MMRDY_Pos)

FPCCR: MMRDY bit Mask

◆ FPU_FPCCR_MMRDY_Msk [4/4]

#define FPU_FPCCR_MMRDY_Msk   (1UL << FPU_FPCCR_MMRDY_Pos)

FPCCR: MMRDY bit Mask

◆ FPU_FPCCR_MMRDY_Pos [1/4]

#define FPU_FPCCR_MMRDY_Pos   5U

FPCCR: MMRDY Position

◆ FPU_FPCCR_MMRDY_Pos [2/4]

#define FPU_FPCCR_MMRDY_Pos   5U

FPCCR: MMRDY Position

◆ FPU_FPCCR_MMRDY_Pos [3/4]

#define FPU_FPCCR_MMRDY_Pos   5U

FPCCR: MMRDY Position

◆ FPU_FPCCR_MMRDY_Pos [4/4]

#define FPU_FPCCR_MMRDY_Pos   5U

FPCCR: MMRDY Position

◆ FPU_FPCCR_MONRDY_Msk [1/4]

#define FPU_FPCCR_MONRDY_Msk   (1UL << FPU_FPCCR_MONRDY_Pos)

FPCCR: MONRDY bit Mask

◆ FPU_FPCCR_MONRDY_Msk [2/4]

#define FPU_FPCCR_MONRDY_Msk   (1UL << FPU_FPCCR_MONRDY_Pos)

FPCCR: MONRDY bit Mask

◆ FPU_FPCCR_MONRDY_Msk [3/4]

#define FPU_FPCCR_MONRDY_Msk   (1UL << FPU_FPCCR_MONRDY_Pos)

FPCCR: MONRDY bit Mask

◆ FPU_FPCCR_MONRDY_Msk [4/4]

#define FPU_FPCCR_MONRDY_Msk   (1UL << FPU_FPCCR_MONRDY_Pos)

FPCCR: MONRDY bit Mask

◆ FPU_FPCCR_MONRDY_Pos [1/4]

#define FPU_FPCCR_MONRDY_Pos   8U

FPCCR: MONRDY Position

◆ FPU_FPCCR_MONRDY_Pos [2/4]

#define FPU_FPCCR_MONRDY_Pos   8U

FPCCR: MONRDY Position

◆ FPU_FPCCR_MONRDY_Pos [3/4]

#define FPU_FPCCR_MONRDY_Pos   8U

FPCCR: MONRDY Position

◆ FPU_FPCCR_MONRDY_Pos [4/4]

#define FPU_FPCCR_MONRDY_Pos   8U

FPCCR: MONRDY Position

◆ FPU_FPCCR_S_Msk [1/2]

#define FPU_FPCCR_S_Msk   (1UL << FPU_FPCCR_S_Pos)

FPCCR: Security status of the FP context bit Mask

◆ FPU_FPCCR_S_Msk [2/2]

#define FPU_FPCCR_S_Msk   (1UL << FPU_FPCCR_S_Pos)

FPCCR: Security status of the FP context bit Mask

◆ FPU_FPCCR_S_Pos [1/2]

#define FPU_FPCCR_S_Pos   2U

FPCCR: Security status of the FP context bit Position

◆ FPU_FPCCR_S_Pos [2/2]

#define FPU_FPCCR_S_Pos   2U

FPCCR: Security status of the FP context bit Position

◆ FPU_FPCCR_SFRDY_Msk [1/2]

#define FPU_FPCCR_SFRDY_Msk   (1UL << FPU_FPCCR_SFRDY_Pos)

FPCCR: SFRDY bit Mask

◆ FPU_FPCCR_SFRDY_Msk [2/2]

#define FPU_FPCCR_SFRDY_Msk   (1UL << FPU_FPCCR_SFRDY_Pos)

FPCCR: SFRDY bit Mask

◆ FPU_FPCCR_SFRDY_Pos [1/2]

#define FPU_FPCCR_SFRDY_Pos   7U

FPCCR: SFRDY Position

◆ FPU_FPCCR_SFRDY_Pos [2/2]

#define FPU_FPCCR_SFRDY_Pos   7U

FPCCR: SFRDY Position

◆ FPU_FPCCR_SPLIMVIOL_Msk [1/2]

#define FPU_FPCCR_SPLIMVIOL_Msk   (1UL << FPU_FPCCR_SPLIMVIOL_Pos)

FPCCR: SPLIMVIOL bit Mask

◆ FPU_FPCCR_SPLIMVIOL_Msk [2/2]

#define FPU_FPCCR_SPLIMVIOL_Msk   (1UL << FPU_FPCCR_SPLIMVIOL_Pos)

FPCCR: SPLIMVIOL bit Mask

◆ FPU_FPCCR_SPLIMVIOL_Pos [1/2]

#define FPU_FPCCR_SPLIMVIOL_Pos   9U

FPCCR: SPLIMVIOL Position

◆ FPU_FPCCR_SPLIMVIOL_Pos [2/2]

#define FPU_FPCCR_SPLIMVIOL_Pos   9U

FPCCR: SPLIMVIOL Position

◆ FPU_FPCCR_THREAD_Msk [1/4]

#define FPU_FPCCR_THREAD_Msk   (1UL << FPU_FPCCR_THREAD_Pos)

FPCCR: processor mode active bit Mask

◆ FPU_FPCCR_THREAD_Msk [2/4]

#define FPU_FPCCR_THREAD_Msk   (1UL << FPU_FPCCR_THREAD_Pos)

FPCCR: processor mode active bit Mask

◆ FPU_FPCCR_THREAD_Msk [3/4]

#define FPU_FPCCR_THREAD_Msk   (1UL << FPU_FPCCR_THREAD_Pos)

FPCCR: processor mode active bit Mask

◆ FPU_FPCCR_THREAD_Msk [4/4]

#define FPU_FPCCR_THREAD_Msk   (1UL << FPU_FPCCR_THREAD_Pos)

FPCCR: processor mode active bit Mask

◆ FPU_FPCCR_THREAD_Pos [1/4]

#define FPU_FPCCR_THREAD_Pos   3U

FPCCR: processor mode bit Position

◆ FPU_FPCCR_THREAD_Pos [2/4]

#define FPU_FPCCR_THREAD_Pos   3U

FPCCR: processor mode bit Position

◆ FPU_FPCCR_THREAD_Pos [3/4]

#define FPU_FPCCR_THREAD_Pos   3U

FPCCR: processor mode bit Position

◆ FPU_FPCCR_THREAD_Pos [4/4]

#define FPU_FPCCR_THREAD_Pos   3U

FPCCR: processor mode bit Position

◆ FPU_FPCCR_TS_Msk [1/2]

#define FPU_FPCCR_TS_Msk   (1UL << FPU_FPCCR_TS_Pos)

FPCCR: TS bit Mask

◆ FPU_FPCCR_TS_Msk [2/2]

#define FPU_FPCCR_TS_Msk   (1UL << FPU_FPCCR_TS_Pos)

FPCCR: TS bit Mask

◆ FPU_FPCCR_TS_Pos [1/2]

#define FPU_FPCCR_TS_Pos   26U

FPCCR: TS Position

◆ FPU_FPCCR_TS_Pos [2/2]

#define FPU_FPCCR_TS_Pos   26U

FPCCR: TS Position

◆ FPU_FPCCR_UFRDY_Msk [1/2]

#define FPU_FPCCR_UFRDY_Msk   (1UL << FPU_FPCCR_UFRDY_Pos)

FPCCR: UFRDY bit Mask

◆ FPU_FPCCR_UFRDY_Msk [2/2]

#define FPU_FPCCR_UFRDY_Msk   (1UL << FPU_FPCCR_UFRDY_Pos)

FPCCR: UFRDY bit Mask

◆ FPU_FPCCR_UFRDY_Pos [1/2]

#define FPU_FPCCR_UFRDY_Pos   10U

FPCCR: UFRDY Position

◆ FPU_FPCCR_UFRDY_Pos [2/2]

#define FPU_FPCCR_UFRDY_Pos   10U

FPCCR: UFRDY Position

◆ FPU_FPCCR_USER_Msk [1/4]

#define FPU_FPCCR_USER_Msk   (1UL << FPU_FPCCR_USER_Pos)

FPCCR: privilege level bit Mask

◆ FPU_FPCCR_USER_Msk [2/4]

#define FPU_FPCCR_USER_Msk   (1UL << FPU_FPCCR_USER_Pos)

FPCCR: privilege level bit Mask

◆ FPU_FPCCR_USER_Msk [3/4]

#define FPU_FPCCR_USER_Msk   (1UL << FPU_FPCCR_USER_Pos)

FPCCR: privilege level bit Mask

◆ FPU_FPCCR_USER_Msk [4/4]

#define FPU_FPCCR_USER_Msk   (1UL << FPU_FPCCR_USER_Pos)

FPCCR: privilege level bit Mask

◆ FPU_FPCCR_USER_Pos [1/4]

#define FPU_FPCCR_USER_Pos   1U

FPCCR: privilege level bit Position

◆ FPU_FPCCR_USER_Pos [2/4]

#define FPU_FPCCR_USER_Pos   1U

FPCCR: privilege level bit Position

◆ FPU_FPCCR_USER_Pos [3/4]

#define FPU_FPCCR_USER_Pos   1U

FPCCR: privilege level bit Position

◆ FPU_FPCCR_USER_Pos [4/4]

#define FPU_FPCCR_USER_Pos   1U

FPCCR: privilege level bit Position

◆ FPU_FPDSCR_AHP_Msk [1/4]

#define FPU_FPDSCR_AHP_Msk   (1UL << FPU_FPDSCR_AHP_Pos)

FPDSCR: AHP bit Mask

◆ FPU_FPDSCR_AHP_Msk [2/4]

#define FPU_FPDSCR_AHP_Msk   (1UL << FPU_FPDSCR_AHP_Pos)

FPDSCR: AHP bit Mask

◆ FPU_FPDSCR_AHP_Msk [3/4]

#define FPU_FPDSCR_AHP_Msk   (1UL << FPU_FPDSCR_AHP_Pos)

FPDSCR: AHP bit Mask

◆ FPU_FPDSCR_AHP_Msk [4/4]

#define FPU_FPDSCR_AHP_Msk   (1UL << FPU_FPDSCR_AHP_Pos)

FPDSCR: AHP bit Mask

◆ FPU_FPDSCR_AHP_Pos [1/4]

#define FPU_FPDSCR_AHP_Pos   26U

FPDSCR: AHP bit Position

◆ FPU_FPDSCR_AHP_Pos [2/4]

#define FPU_FPDSCR_AHP_Pos   26U

FPDSCR: AHP bit Position

◆ FPU_FPDSCR_AHP_Pos [3/4]

#define FPU_FPDSCR_AHP_Pos   26U

FPDSCR: AHP bit Position

◆ FPU_FPDSCR_AHP_Pos [4/4]

#define FPU_FPDSCR_AHP_Pos   26U

FPDSCR: AHP bit Position

◆ FPU_FPDSCR_DN_Msk [1/4]

#define FPU_FPDSCR_DN_Msk   (1UL << FPU_FPDSCR_DN_Pos)

FPDSCR: DN bit Mask

◆ FPU_FPDSCR_DN_Msk [2/4]

#define FPU_FPDSCR_DN_Msk   (1UL << FPU_FPDSCR_DN_Pos)

FPDSCR: DN bit Mask

◆ FPU_FPDSCR_DN_Msk [3/4]

#define FPU_FPDSCR_DN_Msk   (1UL << FPU_FPDSCR_DN_Pos)

FPDSCR: DN bit Mask

◆ FPU_FPDSCR_DN_Msk [4/4]

#define FPU_FPDSCR_DN_Msk   (1UL << FPU_FPDSCR_DN_Pos)

FPDSCR: DN bit Mask

◆ FPU_FPDSCR_DN_Pos [1/4]

#define FPU_FPDSCR_DN_Pos   25U

FPDSCR: DN bit Position

◆ FPU_FPDSCR_DN_Pos [2/4]

#define FPU_FPDSCR_DN_Pos   25U

FPDSCR: DN bit Position

◆ FPU_FPDSCR_DN_Pos [3/4]

#define FPU_FPDSCR_DN_Pos   25U

FPDSCR: DN bit Position

◆ FPU_FPDSCR_DN_Pos [4/4]

#define FPU_FPDSCR_DN_Pos   25U

FPDSCR: DN bit Position

◆ FPU_FPDSCR_FZ_Msk [1/4]

#define FPU_FPDSCR_FZ_Msk   (1UL << FPU_FPDSCR_FZ_Pos)

FPDSCR: FZ bit Mask

◆ FPU_FPDSCR_FZ_Msk [2/4]

#define FPU_FPDSCR_FZ_Msk   (1UL << FPU_FPDSCR_FZ_Pos)

FPDSCR: FZ bit Mask

◆ FPU_FPDSCR_FZ_Msk [3/4]

#define FPU_FPDSCR_FZ_Msk   (1UL << FPU_FPDSCR_FZ_Pos)

FPDSCR: FZ bit Mask

◆ FPU_FPDSCR_FZ_Msk [4/4]

#define FPU_FPDSCR_FZ_Msk   (1UL << FPU_FPDSCR_FZ_Pos)

FPDSCR: FZ bit Mask

◆ FPU_FPDSCR_FZ_Pos [1/4]

#define FPU_FPDSCR_FZ_Pos   24U

FPDSCR: FZ bit Position

◆ FPU_FPDSCR_FZ_Pos [2/4]

#define FPU_FPDSCR_FZ_Pos   24U

FPDSCR: FZ bit Position

◆ FPU_FPDSCR_FZ_Pos [3/4]

#define FPU_FPDSCR_FZ_Pos   24U

FPDSCR: FZ bit Position

◆ FPU_FPDSCR_FZ_Pos [4/4]

#define FPU_FPDSCR_FZ_Pos   24U

FPDSCR: FZ bit Position

◆ FPU_FPDSCR_RMode_Msk [1/4]

#define FPU_FPDSCR_RMode_Msk   (3UL << FPU_FPDSCR_RMode_Pos)

FPDSCR: RMode bit Mask

◆ FPU_FPDSCR_RMode_Msk [2/4]

#define FPU_FPDSCR_RMode_Msk   (3UL << FPU_FPDSCR_RMode_Pos)

FPDSCR: RMode bit Mask

◆ FPU_FPDSCR_RMode_Msk [3/4]

#define FPU_FPDSCR_RMode_Msk   (3UL << FPU_FPDSCR_RMode_Pos)

FPDSCR: RMode bit Mask

◆ FPU_FPDSCR_RMode_Msk [4/4]

#define FPU_FPDSCR_RMode_Msk   (3UL << FPU_FPDSCR_RMode_Pos)

FPDSCR: RMode bit Mask

◆ FPU_FPDSCR_RMode_Pos [1/4]

#define FPU_FPDSCR_RMode_Pos   22U

FPDSCR: RMode bit Position

◆ FPU_FPDSCR_RMode_Pos [2/4]

#define FPU_FPDSCR_RMode_Pos   22U

FPDSCR: RMode bit Position

◆ FPU_FPDSCR_RMode_Pos [3/4]

#define FPU_FPDSCR_RMode_Pos   22U

FPDSCR: RMode bit Position

◆ FPU_FPDSCR_RMode_Pos [4/4]

#define FPU_FPDSCR_RMode_Pos   22U

FPDSCR: RMode bit Position

◆ FPU_MVFR0_A_SIMD_registers_Msk [1/4]

#define FPU_MVFR0_A_SIMD_registers_Msk   (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)

MVFR0: A_SIMD registers bits Mask

◆ FPU_MVFR0_A_SIMD_registers_Msk [2/4]

#define FPU_MVFR0_A_SIMD_registers_Msk   (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)

MVFR0: A_SIMD registers bits Mask

◆ FPU_MVFR0_A_SIMD_registers_Msk [3/4]

#define FPU_MVFR0_A_SIMD_registers_Msk   (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)

MVFR0: A_SIMD registers bits Mask

◆ FPU_MVFR0_A_SIMD_registers_Msk [4/4]

#define FPU_MVFR0_A_SIMD_registers_Msk   (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)

MVFR0: A_SIMD registers bits Mask

◆ FPU_MVFR0_A_SIMD_registers_Pos [1/4]

#define FPU_MVFR0_A_SIMD_registers_Pos   0U

MVFR0: A_SIMD registers bits Position

◆ FPU_MVFR0_A_SIMD_registers_Pos [2/4]

#define FPU_MVFR0_A_SIMD_registers_Pos   0U

MVFR0: A_SIMD registers bits Position

◆ FPU_MVFR0_A_SIMD_registers_Pos [3/4]

#define FPU_MVFR0_A_SIMD_registers_Pos   0U

MVFR0: A_SIMD registers bits Position

◆ FPU_MVFR0_A_SIMD_registers_Pos [4/4]

#define FPU_MVFR0_A_SIMD_registers_Pos   0U

MVFR0: A_SIMD registers bits Position

◆ FPU_MVFR0_Divide_Msk [1/4]

#define FPU_MVFR0_Divide_Msk   (0xFUL << FPU_MVFR0_Divide_Pos)

MVFR0: Divide bits Mask

◆ FPU_MVFR0_Divide_Msk [2/4]

#define FPU_MVFR0_Divide_Msk   (0xFUL << FPU_MVFR0_Divide_Pos)

MVFR0: Divide bits Mask

◆ FPU_MVFR0_Divide_Msk [3/4]

#define FPU_MVFR0_Divide_Msk   (0xFUL << FPU_MVFR0_Divide_Pos)

MVFR0: Divide bits Mask

◆ FPU_MVFR0_Divide_Msk [4/4]

#define FPU_MVFR0_Divide_Msk   (0xFUL << FPU_MVFR0_Divide_Pos)

MVFR0: Divide bits Mask

◆ FPU_MVFR0_Divide_Pos [1/4]

#define FPU_MVFR0_Divide_Pos   16U

MVFR0: Divide bits Position

◆ FPU_MVFR0_Divide_Pos [2/4]

#define FPU_MVFR0_Divide_Pos   16U

MVFR0: Divide bits Position

◆ FPU_MVFR0_Divide_Pos [3/4]

#define FPU_MVFR0_Divide_Pos   16U

MVFR0: Divide bits Position

◆ FPU_MVFR0_Divide_Pos [4/4]

#define FPU_MVFR0_Divide_Pos   16U

MVFR0: Divide bits Position

◆ FPU_MVFR0_Double_precision_Msk [1/4]

#define FPU_MVFR0_Double_precision_Msk   (0xFUL << FPU_MVFR0_Double_precision_Pos)

MVFR0: Double-precision bits Mask

◆ FPU_MVFR0_Double_precision_Msk [2/4]

#define FPU_MVFR0_Double_precision_Msk   (0xFUL << FPU_MVFR0_Double_precision_Pos)

MVFR0: Double-precision bits Mask

◆ FPU_MVFR0_Double_precision_Msk [3/4]

#define FPU_MVFR0_Double_precision_Msk   (0xFUL << FPU_MVFR0_Double_precision_Pos)

MVFR0: Double-precision bits Mask

◆ FPU_MVFR0_Double_precision_Msk [4/4]

#define FPU_MVFR0_Double_precision_Msk   (0xFUL << FPU_MVFR0_Double_precision_Pos)

MVFR0: Double-precision bits Mask

◆ FPU_MVFR0_Double_precision_Pos [1/4]

#define FPU_MVFR0_Double_precision_Pos   8U

MVFR0: Double-precision bits Position

◆ FPU_MVFR0_Double_precision_Pos [2/4]

#define FPU_MVFR0_Double_precision_Pos   8U

MVFR0: Double-precision bits Position

◆ FPU_MVFR0_Double_precision_Pos [3/4]

#define FPU_MVFR0_Double_precision_Pos   8U

MVFR0: Double-precision bits Position

◆ FPU_MVFR0_Double_precision_Pos [4/4]

#define FPU_MVFR0_Double_precision_Pos   8U

MVFR0: Double-precision bits Position

◆ FPU_MVFR0_FP_excep_trapping_Msk [1/4]

#define FPU_MVFR0_FP_excep_trapping_Msk   (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

MVFR0: FP exception trapping bits Mask

◆ FPU_MVFR0_FP_excep_trapping_Msk [2/4]

#define FPU_MVFR0_FP_excep_trapping_Msk   (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

MVFR0: FP exception trapping bits Mask

◆ FPU_MVFR0_FP_excep_trapping_Msk [3/4]

#define FPU_MVFR0_FP_excep_trapping_Msk   (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

MVFR0: FP exception trapping bits Mask

◆ FPU_MVFR0_FP_excep_trapping_Msk [4/4]

#define FPU_MVFR0_FP_excep_trapping_Msk   (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

MVFR0: FP exception trapping bits Mask

◆ FPU_MVFR0_FP_excep_trapping_Pos [1/4]

#define FPU_MVFR0_FP_excep_trapping_Pos   12U

MVFR0: FP exception trapping bits Position

◆ FPU_MVFR0_FP_excep_trapping_Pos [2/4]

#define FPU_MVFR0_FP_excep_trapping_Pos   12U

MVFR0: FP exception trapping bits Position

◆ FPU_MVFR0_FP_excep_trapping_Pos [3/4]

#define FPU_MVFR0_FP_excep_trapping_Pos   12U

MVFR0: FP exception trapping bits Position

◆ FPU_MVFR0_FP_excep_trapping_Pos [4/4]

#define FPU_MVFR0_FP_excep_trapping_Pos   12U

MVFR0: FP exception trapping bits Position

◆ FPU_MVFR0_FP_rounding_modes_Msk [1/4]

#define FPU_MVFR0_FP_rounding_modes_Msk   (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

MVFR0: FP rounding modes bits Mask

◆ FPU_MVFR0_FP_rounding_modes_Msk [2/4]

#define FPU_MVFR0_FP_rounding_modes_Msk   (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

MVFR0: FP rounding modes bits Mask

◆ FPU_MVFR0_FP_rounding_modes_Msk [3/4]

#define FPU_MVFR0_FP_rounding_modes_Msk   (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

MVFR0: FP rounding modes bits Mask

◆ FPU_MVFR0_FP_rounding_modes_Msk [4/4]

#define FPU_MVFR0_FP_rounding_modes_Msk   (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

MVFR0: FP rounding modes bits Mask

◆ FPU_MVFR0_FP_rounding_modes_Pos [1/4]

#define FPU_MVFR0_FP_rounding_modes_Pos   28U

MVFR0: FP rounding modes bits Position

◆ FPU_MVFR0_FP_rounding_modes_Pos [2/4]

#define FPU_MVFR0_FP_rounding_modes_Pos   28U

MVFR0: FP rounding modes bits Position

◆ FPU_MVFR0_FP_rounding_modes_Pos [3/4]

#define FPU_MVFR0_FP_rounding_modes_Pos   28U

MVFR0: FP rounding modes bits Position

◆ FPU_MVFR0_FP_rounding_modes_Pos [4/4]

#define FPU_MVFR0_FP_rounding_modes_Pos   28U

MVFR0: FP rounding modes bits Position

◆ FPU_MVFR0_Short_vectors_Msk [1/4]

#define FPU_MVFR0_Short_vectors_Msk   (0xFUL << FPU_MVFR0_Short_vectors_Pos)

MVFR0: Short vectors bits Mask

◆ FPU_MVFR0_Short_vectors_Msk [2/4]

#define FPU_MVFR0_Short_vectors_Msk   (0xFUL << FPU_MVFR0_Short_vectors_Pos)

MVFR0: Short vectors bits Mask

◆ FPU_MVFR0_Short_vectors_Msk [3/4]

#define FPU_MVFR0_Short_vectors_Msk   (0xFUL << FPU_MVFR0_Short_vectors_Pos)

MVFR0: Short vectors bits Mask

◆ FPU_MVFR0_Short_vectors_Msk [4/4]

#define FPU_MVFR0_Short_vectors_Msk   (0xFUL << FPU_MVFR0_Short_vectors_Pos)

MVFR0: Short vectors bits Mask

◆ FPU_MVFR0_Short_vectors_Pos [1/4]

#define FPU_MVFR0_Short_vectors_Pos   24U

MVFR0: Short vectors bits Position

◆ FPU_MVFR0_Short_vectors_Pos [2/4]

#define FPU_MVFR0_Short_vectors_Pos   24U

MVFR0: Short vectors bits Position

◆ FPU_MVFR0_Short_vectors_Pos [3/4]

#define FPU_MVFR0_Short_vectors_Pos   24U

MVFR0: Short vectors bits Position

◆ FPU_MVFR0_Short_vectors_Pos [4/4]

#define FPU_MVFR0_Short_vectors_Pos   24U

MVFR0: Short vectors bits Position

◆ FPU_MVFR0_Single_precision_Msk [1/4]

#define FPU_MVFR0_Single_precision_Msk   (0xFUL << FPU_MVFR0_Single_precision_Pos)

MVFR0: Single-precision bits Mask

◆ FPU_MVFR0_Single_precision_Msk [2/4]

#define FPU_MVFR0_Single_precision_Msk   (0xFUL << FPU_MVFR0_Single_precision_Pos)

MVFR0: Single-precision bits Mask

◆ FPU_MVFR0_Single_precision_Msk [3/4]

#define FPU_MVFR0_Single_precision_Msk   (0xFUL << FPU_MVFR0_Single_precision_Pos)

MVFR0: Single-precision bits Mask

◆ FPU_MVFR0_Single_precision_Msk [4/4]

#define FPU_MVFR0_Single_precision_Msk   (0xFUL << FPU_MVFR0_Single_precision_Pos)

MVFR0: Single-precision bits Mask

◆ FPU_MVFR0_Single_precision_Pos [1/4]

#define FPU_MVFR0_Single_precision_Pos   4U

MVFR0: Single-precision bits Position

◆ FPU_MVFR0_Single_precision_Pos [2/4]

#define FPU_MVFR0_Single_precision_Pos   4U

MVFR0: Single-precision bits Position

◆ FPU_MVFR0_Single_precision_Pos [3/4]

#define FPU_MVFR0_Single_precision_Pos   4U

MVFR0: Single-precision bits Position

◆ FPU_MVFR0_Single_precision_Pos [4/4]

#define FPU_MVFR0_Single_precision_Pos   4U

MVFR0: Single-precision bits Position

◆ FPU_MVFR0_Square_root_Msk [1/4]

#define FPU_MVFR0_Square_root_Msk   (0xFUL << FPU_MVFR0_Square_root_Pos)

MVFR0: Square root bits Mask

◆ FPU_MVFR0_Square_root_Msk [2/4]

#define FPU_MVFR0_Square_root_Msk   (0xFUL << FPU_MVFR0_Square_root_Pos)

MVFR0: Square root bits Mask

◆ FPU_MVFR0_Square_root_Msk [3/4]

#define FPU_MVFR0_Square_root_Msk   (0xFUL << FPU_MVFR0_Square_root_Pos)

MVFR0: Square root bits Mask

◆ FPU_MVFR0_Square_root_Msk [4/4]

#define FPU_MVFR0_Square_root_Msk   (0xFUL << FPU_MVFR0_Square_root_Pos)

MVFR0: Square root bits Mask

◆ FPU_MVFR0_Square_root_Pos [1/4]

#define FPU_MVFR0_Square_root_Pos   20U

MVFR0: Square root bits Position

◆ FPU_MVFR0_Square_root_Pos [2/4]

#define FPU_MVFR0_Square_root_Pos   20U

MVFR0: Square root bits Position

◆ FPU_MVFR0_Square_root_Pos [3/4]

#define FPU_MVFR0_Square_root_Pos   20U

MVFR0: Square root bits Position

◆ FPU_MVFR0_Square_root_Pos [4/4]

#define FPU_MVFR0_Square_root_Pos   20U

MVFR0: Square root bits Position

◆ FPU_MVFR1_D_NaN_mode_Msk [1/4]

#define FPU_MVFR1_D_NaN_mode_Msk   (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)

MVFR1: D_NaN mode bits Mask

◆ FPU_MVFR1_D_NaN_mode_Msk [2/4]

#define FPU_MVFR1_D_NaN_mode_Msk   (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)

MVFR1: D_NaN mode bits Mask

◆ FPU_MVFR1_D_NaN_mode_Msk [3/4]

#define FPU_MVFR1_D_NaN_mode_Msk   (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)

MVFR1: D_NaN mode bits Mask

◆ FPU_MVFR1_D_NaN_mode_Msk [4/4]

#define FPU_MVFR1_D_NaN_mode_Msk   (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)

MVFR1: D_NaN mode bits Mask

◆ FPU_MVFR1_D_NaN_mode_Pos [1/4]

#define FPU_MVFR1_D_NaN_mode_Pos   4U

MVFR1: D_NaN mode bits Position

◆ FPU_MVFR1_D_NaN_mode_Pos [2/4]

#define FPU_MVFR1_D_NaN_mode_Pos   4U

MVFR1: D_NaN mode bits Position

◆ FPU_MVFR1_D_NaN_mode_Pos [3/4]

#define FPU_MVFR1_D_NaN_mode_Pos   4U

MVFR1: D_NaN mode bits Position

◆ FPU_MVFR1_D_NaN_mode_Pos [4/4]

#define FPU_MVFR1_D_NaN_mode_Pos   4U

MVFR1: D_NaN mode bits Position

◆ FPU_MVFR1_FP_fused_MAC_Msk [1/4]

#define FPU_MVFR1_FP_fused_MAC_Msk   (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)

MVFR1: FP fused MAC bits Mask

◆ FPU_MVFR1_FP_fused_MAC_Msk [2/4]

#define FPU_MVFR1_FP_fused_MAC_Msk   (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)

MVFR1: FP fused MAC bits Mask

◆ FPU_MVFR1_FP_fused_MAC_Msk [3/4]

#define FPU_MVFR1_FP_fused_MAC_Msk   (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)

MVFR1: FP fused MAC bits Mask

◆ FPU_MVFR1_FP_fused_MAC_Msk [4/4]

#define FPU_MVFR1_FP_fused_MAC_Msk   (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)

MVFR1: FP fused MAC bits Mask

◆ FPU_MVFR1_FP_fused_MAC_Pos [1/4]

#define FPU_MVFR1_FP_fused_MAC_Pos   28U

MVFR1: FP fused MAC bits Position

◆ FPU_MVFR1_FP_fused_MAC_Pos [2/4]

#define FPU_MVFR1_FP_fused_MAC_Pos   28U

MVFR1: FP fused MAC bits Position

◆ FPU_MVFR1_FP_fused_MAC_Pos [3/4]

#define FPU_MVFR1_FP_fused_MAC_Pos   28U

MVFR1: FP fused MAC bits Position

◆ FPU_MVFR1_FP_fused_MAC_Pos [4/4]

#define FPU_MVFR1_FP_fused_MAC_Pos   28U

MVFR1: FP fused MAC bits Position

◆ FPU_MVFR1_FP_HPFP_Msk [1/4]

#define FPU_MVFR1_FP_HPFP_Msk   (0xFUL << FPU_MVFR1_FP_HPFP_Pos)

MVFR1: FP HPFP bits Mask

◆ FPU_MVFR1_FP_HPFP_Msk [2/4]

#define FPU_MVFR1_FP_HPFP_Msk   (0xFUL << FPU_MVFR1_FP_HPFP_Pos)

MVFR1: FP HPFP bits Mask

◆ FPU_MVFR1_FP_HPFP_Msk [3/4]

#define FPU_MVFR1_FP_HPFP_Msk   (0xFUL << FPU_MVFR1_FP_HPFP_Pos)

MVFR1: FP HPFP bits Mask

◆ FPU_MVFR1_FP_HPFP_Msk [4/4]

#define FPU_MVFR1_FP_HPFP_Msk   (0xFUL << FPU_MVFR1_FP_HPFP_Pos)

MVFR1: FP HPFP bits Mask

◆ FPU_MVFR1_FP_HPFP_Pos [1/4]

#define FPU_MVFR1_FP_HPFP_Pos   24U

MVFR1: FP HPFP bits Position

◆ FPU_MVFR1_FP_HPFP_Pos [2/4]

#define FPU_MVFR1_FP_HPFP_Pos   24U

MVFR1: FP HPFP bits Position

◆ FPU_MVFR1_FP_HPFP_Pos [3/4]

#define FPU_MVFR1_FP_HPFP_Pos   24U

MVFR1: FP HPFP bits Position

◆ FPU_MVFR1_FP_HPFP_Pos [4/4]

#define FPU_MVFR1_FP_HPFP_Pos   24U

MVFR1: FP HPFP bits Position

◆ FPU_MVFR1_FtZ_mode_Msk [1/4]

#define FPU_MVFR1_FtZ_mode_Msk   (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)

MVFR1: FtZ mode bits Mask

◆ FPU_MVFR1_FtZ_mode_Msk [2/4]

#define FPU_MVFR1_FtZ_mode_Msk   (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)

MVFR1: FtZ mode bits Mask

◆ FPU_MVFR1_FtZ_mode_Msk [3/4]

#define FPU_MVFR1_FtZ_mode_Msk   (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)

MVFR1: FtZ mode bits Mask

◆ FPU_MVFR1_FtZ_mode_Msk [4/4]

#define FPU_MVFR1_FtZ_mode_Msk   (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)

MVFR1: FtZ mode bits Mask

◆ FPU_MVFR1_FtZ_mode_Pos [1/4]

#define FPU_MVFR1_FtZ_mode_Pos   0U

MVFR1: FtZ mode bits Position

◆ FPU_MVFR1_FtZ_mode_Pos [2/4]

#define FPU_MVFR1_FtZ_mode_Pos   0U

MVFR1: FtZ mode bits Position

◆ FPU_MVFR1_FtZ_mode_Pos [3/4]

#define FPU_MVFR1_FtZ_mode_Pos   0U

MVFR1: FtZ mode bits Position

◆ FPU_MVFR1_FtZ_mode_Pos [4/4]

#define FPU_MVFR1_FtZ_mode_Pos   0U

MVFR1: FtZ mode bits Position

◆ IPSR_ISR_Msk [1/12]

#define IPSR_ISR_Msk   (0x1FFUL /*<< IPSR_ISR_Pos*/)

IPSR: ISR Mask

◆ IPSR_ISR_Msk [2/12]

#define IPSR_ISR_Msk   (0x1FFUL /*<< IPSR_ISR_Pos*/)

IPSR: ISR Mask

◆ IPSR_ISR_Msk [3/12]

#define IPSR_ISR_Msk   (0x1FFUL /*<< IPSR_ISR_Pos*/)

IPSR: ISR Mask

◆ IPSR_ISR_Msk [4/12]

#define IPSR_ISR_Msk   (0x1FFUL /*<< IPSR_ISR_Pos*/)

IPSR: ISR Mask

◆ IPSR_ISR_Msk [5/12]

#define IPSR_ISR_Msk   (0x1FFUL /*<< IPSR_ISR_Pos*/)

IPSR: ISR Mask

◆ IPSR_ISR_Msk [6/12]

#define IPSR_ISR_Msk   (0x1FFUL /*<< IPSR_ISR_Pos*/)

IPSR: ISR Mask

◆ IPSR_ISR_Msk [7/12]

#define IPSR_ISR_Msk   (0x1FFUL /*<< IPSR_ISR_Pos*/)

IPSR: ISR Mask

◆ IPSR_ISR_Msk [8/12]

#define IPSR_ISR_Msk   (0x1FFUL /*<< IPSR_ISR_Pos*/)

IPSR: ISR Mask

◆ IPSR_ISR_Msk [9/12]

#define IPSR_ISR_Msk   (0x1FFUL /*<< IPSR_ISR_Pos*/)

IPSR: ISR Mask

◆ IPSR_ISR_Msk [10/12]

#define IPSR_ISR_Msk   (0x1FFUL /*<< IPSR_ISR_Pos*/)

IPSR: ISR Mask

◆ IPSR_ISR_Msk [11/12]

#define IPSR_ISR_Msk   (0x1FFUL /*<< IPSR_ISR_Pos*/)

IPSR: ISR Mask

◆ IPSR_ISR_Msk [12/12]

#define IPSR_ISR_Msk   (0x1FFUL /*<< IPSR_ISR_Pos*/)

IPSR: ISR Mask

◆ IPSR_ISR_Pos [1/12]

#define IPSR_ISR_Pos   0U

IPSR: ISR Position

◆ IPSR_ISR_Pos [2/12]

#define IPSR_ISR_Pos   0U

IPSR: ISR Position

◆ IPSR_ISR_Pos [3/12]

#define IPSR_ISR_Pos   0U

IPSR: ISR Position

◆ IPSR_ISR_Pos [4/12]

#define IPSR_ISR_Pos   0U

IPSR: ISR Position

◆ IPSR_ISR_Pos [5/12]

#define IPSR_ISR_Pos   0U

IPSR: ISR Position

◆ IPSR_ISR_Pos [6/12]

#define IPSR_ISR_Pos   0U

IPSR: ISR Position

◆ IPSR_ISR_Pos [7/12]

#define IPSR_ISR_Pos   0U

IPSR: ISR Position

◆ IPSR_ISR_Pos [8/12]

#define IPSR_ISR_Pos   0U

IPSR: ISR Position

◆ IPSR_ISR_Pos [9/12]

#define IPSR_ISR_Pos   0U

IPSR: ISR Position

◆ IPSR_ISR_Pos [10/12]

#define IPSR_ISR_Pos   0U

IPSR: ISR Position

◆ IPSR_ISR_Pos [11/12]

#define IPSR_ISR_Pos   0U

IPSR: ISR Position

◆ IPSR_ISR_Pos [12/12]

#define IPSR_ISR_Pos   0U

IPSR: ISR Position

◆ ITM [1/6]

#define ITM   ((ITM_Type *) ITM_BASE )

ITM configuration struct

◆ ITM [2/6]

#define ITM   ((ITM_Type *) ITM_BASE )

ITM configuration struct

◆ ITM [3/6]

#define ITM   ((ITM_Type *) ITM_BASE )

ITM configuration struct

◆ ITM [4/6]

#define ITM   ((ITM_Type *) ITM_BASE )

ITM configuration struct

◆ ITM [5/6]

#define ITM   ((ITM_Type *) ITM_BASE )

ITM configuration struct

◆ ITM [6/6]

#define ITM   ((ITM_Type *) ITM_BASE )

ITM configuration struct

◆ ITM_BASE [1/6]

#define ITM_BASE   (0xE0000000UL)

ITM Base Address

◆ ITM_BASE [2/6]

#define ITM_BASE   (0xE0000000UL)

ITM Base Address

◆ ITM_BASE [3/6]

#define ITM_BASE   (0xE0000000UL)

ITM Base Address

◆ ITM_BASE [4/6]

#define ITM_BASE   (0xE0000000UL)

ITM Base Address

◆ ITM_BASE [5/6]

#define ITM_BASE   (0xE0000000UL)

ITM Base Address

◆ ITM_BASE [6/6]

#define ITM_BASE   (0xE0000000UL)

ITM Base Address

◆ ITM_IMCR_INTEGRATION_Msk [1/6]

#define ITM_IMCR_INTEGRATION_Msk   (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)

ITM IMCR: INTEGRATION Mask

◆ ITM_IMCR_INTEGRATION_Msk [2/6]

#define ITM_IMCR_INTEGRATION_Msk   (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)

ITM IMCR: INTEGRATION Mask

◆ ITM_IMCR_INTEGRATION_Msk [3/6]

#define ITM_IMCR_INTEGRATION_Msk   (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)

ITM IMCR: INTEGRATION Mask

◆ ITM_IMCR_INTEGRATION_Msk [4/6]

#define ITM_IMCR_INTEGRATION_Msk   (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)

ITM IMCR: INTEGRATION Mask

◆ ITM_IMCR_INTEGRATION_Msk [5/6]

#define ITM_IMCR_INTEGRATION_Msk   (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)

ITM IMCR: INTEGRATION Mask

◆ ITM_IMCR_INTEGRATION_Msk [6/6]

#define ITM_IMCR_INTEGRATION_Msk   (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)

ITM IMCR: INTEGRATION Mask

◆ ITM_IMCR_INTEGRATION_Pos [1/6]

#define ITM_IMCR_INTEGRATION_Pos   0U

ITM IMCR: INTEGRATION Position

◆ ITM_IMCR_INTEGRATION_Pos [2/6]

#define ITM_IMCR_INTEGRATION_Pos   0U

ITM IMCR: INTEGRATION Position

◆ ITM_IMCR_INTEGRATION_Pos [3/6]

#define ITM_IMCR_INTEGRATION_Pos   0U

ITM IMCR: INTEGRATION Position

◆ ITM_IMCR_INTEGRATION_Pos [4/6]

#define ITM_IMCR_INTEGRATION_Pos   0U

ITM IMCR: INTEGRATION Position

◆ ITM_IMCR_INTEGRATION_Pos [5/6]

#define ITM_IMCR_INTEGRATION_Pos   0U

ITM IMCR: INTEGRATION Position

◆ ITM_IMCR_INTEGRATION_Pos [6/6]

#define ITM_IMCR_INTEGRATION_Pos   0U

ITM IMCR: INTEGRATION Position

◆ ITM_IRR_ATREADYM_Msk [1/6]

#define ITM_IRR_ATREADYM_Msk   (1UL /*<< ITM_IRR_ATREADYM_Pos*/)

ITM IRR: ATREADYM Mask

◆ ITM_IRR_ATREADYM_Msk [2/6]

#define ITM_IRR_ATREADYM_Msk   (1UL /*<< ITM_IRR_ATREADYM_Pos*/)

ITM IRR: ATREADYM Mask

◆ ITM_IRR_ATREADYM_Msk [3/6]

#define ITM_IRR_ATREADYM_Msk   (1UL /*<< ITM_IRR_ATREADYM_Pos*/)

ITM IRR: ATREADYM Mask

◆ ITM_IRR_ATREADYM_Msk [4/6]

#define ITM_IRR_ATREADYM_Msk   (1UL /*<< ITM_IRR_ATREADYM_Pos*/)

ITM IRR: ATREADYM Mask

◆ ITM_IRR_ATREADYM_Msk [5/6]

#define ITM_IRR_ATREADYM_Msk   (1UL /*<< ITM_IRR_ATREADYM_Pos*/)

ITM IRR: ATREADYM Mask

◆ ITM_IRR_ATREADYM_Msk [6/6]

#define ITM_IRR_ATREADYM_Msk   (1UL /*<< ITM_IRR_ATREADYM_Pos*/)

ITM IRR: ATREADYM Mask

◆ ITM_IRR_ATREADYM_Pos [1/6]

#define ITM_IRR_ATREADYM_Pos   0U

ITM IRR: ATREADYM Position

◆ ITM_IRR_ATREADYM_Pos [2/6]

#define ITM_IRR_ATREADYM_Pos   0U

ITM IRR: ATREADYM Position

◆ ITM_IRR_ATREADYM_Pos [3/6]

#define ITM_IRR_ATREADYM_Pos   0U

ITM IRR: ATREADYM Position

◆ ITM_IRR_ATREADYM_Pos [4/6]

#define ITM_IRR_ATREADYM_Pos   0U

ITM IRR: ATREADYM Position

◆ ITM_IRR_ATREADYM_Pos [5/6]

#define ITM_IRR_ATREADYM_Pos   0U

ITM IRR: ATREADYM Position

◆ ITM_IRR_ATREADYM_Pos [6/6]

#define ITM_IRR_ATREADYM_Pos   0U

ITM IRR: ATREADYM Position

◆ ITM_IWR_ATVALIDM_Msk [1/6]

#define ITM_IWR_ATVALIDM_Msk   (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)

ITM IWR: ATVALIDM Mask

◆ ITM_IWR_ATVALIDM_Msk [2/6]

#define ITM_IWR_ATVALIDM_Msk   (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)

ITM IWR: ATVALIDM Mask

◆ ITM_IWR_ATVALIDM_Msk [3/6]

#define ITM_IWR_ATVALIDM_Msk   (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)

ITM IWR: ATVALIDM Mask

◆ ITM_IWR_ATVALIDM_Msk [4/6]

#define ITM_IWR_ATVALIDM_Msk   (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)

ITM IWR: ATVALIDM Mask

◆ ITM_IWR_ATVALIDM_Msk [5/6]

#define ITM_IWR_ATVALIDM_Msk   (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)

ITM IWR: ATVALIDM Mask

◆ ITM_IWR_ATVALIDM_Msk [6/6]

#define ITM_IWR_ATVALIDM_Msk   (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)

ITM IWR: ATVALIDM Mask

◆ ITM_IWR_ATVALIDM_Pos [1/6]

#define ITM_IWR_ATVALIDM_Pos   0U

ITM IWR: ATVALIDM Position

◆ ITM_IWR_ATVALIDM_Pos [2/6]

#define ITM_IWR_ATVALIDM_Pos   0U

ITM IWR: ATVALIDM Position

◆ ITM_IWR_ATVALIDM_Pos [3/6]

#define ITM_IWR_ATVALIDM_Pos   0U

ITM IWR: ATVALIDM Position

◆ ITM_IWR_ATVALIDM_Pos [4/6]

#define ITM_IWR_ATVALIDM_Pos   0U

ITM IWR: ATVALIDM Position

◆ ITM_IWR_ATVALIDM_Pos [5/6]

#define ITM_IWR_ATVALIDM_Pos   0U

ITM IWR: ATVALIDM Position

◆ ITM_IWR_ATVALIDM_Pos [6/6]

#define ITM_IWR_ATVALIDM_Pos   0U

ITM IWR: ATVALIDM Position

◆ ITM_LSR_Access_Msk [1/6]

#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

◆ ITM_LSR_Access_Msk [2/6]

#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

◆ ITM_LSR_Access_Msk [3/6]

#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

◆ ITM_LSR_Access_Msk [4/6]

#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

◆ ITM_LSR_Access_Msk [5/6]

#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

◆ ITM_LSR_Access_Msk [6/6]

#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

◆ ITM_LSR_Access_Pos [1/6]

#define ITM_LSR_Access_Pos   1U

ITM LSR: Access Position

◆ ITM_LSR_Access_Pos [2/6]

#define ITM_LSR_Access_Pos   1U

ITM LSR: Access Position

◆ ITM_LSR_Access_Pos [3/6]

#define ITM_LSR_Access_Pos   1U

ITM LSR: Access Position

◆ ITM_LSR_Access_Pos [4/6]

#define ITM_LSR_Access_Pos   1U

ITM LSR: Access Position

◆ ITM_LSR_Access_Pos [5/6]

#define ITM_LSR_Access_Pos   1U

ITM LSR: Access Position

◆ ITM_LSR_Access_Pos [6/6]

#define ITM_LSR_Access_Pos   1U

ITM LSR: Access Position

◆ ITM_LSR_ByteAcc_Msk [1/6]

#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

◆ ITM_LSR_ByteAcc_Msk [2/6]

#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

◆ ITM_LSR_ByteAcc_Msk [3/6]

#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

◆ ITM_LSR_ByteAcc_Msk [4/6]

#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

◆ ITM_LSR_ByteAcc_Msk [5/6]

#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

◆ ITM_LSR_ByteAcc_Msk [6/6]

#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

◆ ITM_LSR_ByteAcc_Pos [1/6]

#define ITM_LSR_ByteAcc_Pos   2U

ITM LSR: ByteAcc Position

◆ ITM_LSR_ByteAcc_Pos [2/6]

#define ITM_LSR_ByteAcc_Pos   2U

ITM LSR: ByteAcc Position

◆ ITM_LSR_ByteAcc_Pos [3/6]

#define ITM_LSR_ByteAcc_Pos   2U

ITM LSR: ByteAcc Position

◆ ITM_LSR_ByteAcc_Pos [4/6]

#define ITM_LSR_ByteAcc_Pos   2U

ITM LSR: ByteAcc Position

◆ ITM_LSR_ByteAcc_Pos [5/6]

#define ITM_LSR_ByteAcc_Pos   2U

ITM LSR: ByteAcc Position

◆ ITM_LSR_ByteAcc_Pos [6/6]

#define ITM_LSR_ByteAcc_Pos   2U

ITM LSR: ByteAcc Position

◆ ITM_LSR_Present_Msk [1/6]

#define ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

◆ ITM_LSR_Present_Msk [2/6]

#define ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

◆ ITM_LSR_Present_Msk [3/6]

#define ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

◆ ITM_LSR_Present_Msk [4/6]

#define ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

◆ ITM_LSR_Present_Msk [5/6]

#define ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

◆ ITM_LSR_Present_Msk [6/6]

#define ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

◆ ITM_LSR_Present_Pos [1/6]

#define ITM_LSR_Present_Pos   0U

ITM LSR: Present Position

◆ ITM_LSR_Present_Pos [2/6]

#define ITM_LSR_Present_Pos   0U

ITM LSR: Present Position

◆ ITM_LSR_Present_Pos [3/6]

#define ITM_LSR_Present_Pos   0U

ITM LSR: Present Position

◆ ITM_LSR_Present_Pos [4/6]

#define ITM_LSR_Present_Pos   0U

ITM LSR: Present Position

◆ ITM_LSR_Present_Pos [5/6]

#define ITM_LSR_Present_Pos   0U

ITM LSR: Present Position

◆ ITM_LSR_Present_Pos [6/6]

#define ITM_LSR_Present_Pos   0U

ITM LSR: Present Position

◆ ITM_RXBUFFER_EMPTY [1/5]

#define ITM_RXBUFFER_EMPTY   ((int32_t)0x5AA55AA5U)

Value identifying ITM_RxBuffer is ready for next character.

◆ ITM_RXBUFFER_EMPTY [2/5]

#define ITM_RXBUFFER_EMPTY   ((int32_t)0x5AA55AA5U)

Value identifying ITM_RxBuffer is ready for next character.

◆ ITM_RXBUFFER_EMPTY [3/5]

#define ITM_RXBUFFER_EMPTY   ((int32_t)0x5AA55AA5U)

Value identifying ITM_RxBuffer is ready for next character.

◆ ITM_RXBUFFER_EMPTY [4/5]

#define ITM_RXBUFFER_EMPTY   ((int32_t)0x5AA55AA5U)

Value identifying ITM_RxBuffer is ready for next character.

◆ ITM_RXBUFFER_EMPTY [5/5]

#define ITM_RXBUFFER_EMPTY   ((int32_t)0x5AA55AA5U)

Value identifying ITM_RxBuffer is ready for next character.

◆ ITM_STIM_DISABLED_Msk [1/2]

#define ITM_STIM_DISABLED_Msk   (0x1UL << ITM_STIM_DISABLED_Pos)

ITM STIM: DISABLED Mask

◆ ITM_STIM_DISABLED_Msk [2/2]

#define ITM_STIM_DISABLED_Msk   (0x1UL << ITM_STIM_DISABLED_Pos)

ITM STIM: DISABLED Mask

◆ ITM_STIM_DISABLED_Pos [1/2]

#define ITM_STIM_DISABLED_Pos   1U

ITM STIM: DISABLED Position

◆ ITM_STIM_DISABLED_Pos [2/2]

#define ITM_STIM_DISABLED_Pos   1U

ITM STIM: DISABLED Position

◆ ITM_STIM_FIFOREADY_Msk [1/2]

#define ITM_STIM_FIFOREADY_Msk   (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)

ITM STIM: FIFOREADY Mask

◆ ITM_STIM_FIFOREADY_Msk [2/2]

#define ITM_STIM_FIFOREADY_Msk   (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)

ITM STIM: FIFOREADY Mask

◆ ITM_STIM_FIFOREADY_Pos [1/2]

#define ITM_STIM_FIFOREADY_Pos   0U

ITM STIM: FIFOREADY Position

◆ ITM_STIM_FIFOREADY_Pos [2/2]

#define ITM_STIM_FIFOREADY_Pos   0U

ITM STIM: FIFOREADY Position

◆ ITM_TCR_BUSY_Msk [1/6]

#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

◆ ITM_TCR_BUSY_Msk [2/6]

#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

◆ ITM_TCR_BUSY_Msk [3/6]

#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

◆ ITM_TCR_BUSY_Msk [4/6]

#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

◆ ITM_TCR_BUSY_Msk [5/6]

#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

◆ ITM_TCR_BUSY_Msk [6/6]

#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

◆ ITM_TCR_BUSY_Pos [1/6]

#define ITM_TCR_BUSY_Pos   23U

ITM TCR: BUSY Position

◆ ITM_TCR_BUSY_Pos [2/6]

#define ITM_TCR_BUSY_Pos   23U

ITM TCR: BUSY Position

◆ ITM_TCR_BUSY_Pos [3/6]

#define ITM_TCR_BUSY_Pos   23U

ITM TCR: BUSY Position

◆ ITM_TCR_BUSY_Pos [4/6]

#define ITM_TCR_BUSY_Pos   23U

ITM TCR: BUSY Position

◆ ITM_TCR_BUSY_Pos [5/6]

#define ITM_TCR_BUSY_Pos   23U

ITM TCR: BUSY Position

◆ ITM_TCR_BUSY_Pos [6/6]

#define ITM_TCR_BUSY_Pos   23U

ITM TCR: BUSY Position

◆ ITM_TCR_DWTENA_Msk [1/6]

#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

◆ ITM_TCR_DWTENA_Msk [2/6]

#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

◆ ITM_TCR_DWTENA_Msk [3/6]

#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

◆ ITM_TCR_DWTENA_Msk [4/6]

#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

◆ ITM_TCR_DWTENA_Msk [5/6]

#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

◆ ITM_TCR_DWTENA_Msk [6/6]

#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

◆ ITM_TCR_DWTENA_Pos [1/6]

#define ITM_TCR_DWTENA_Pos   3U

ITM TCR: DWTENA Position

◆ ITM_TCR_DWTENA_Pos [2/6]

#define ITM_TCR_DWTENA_Pos   3U

ITM TCR: DWTENA Position

◆ ITM_TCR_DWTENA_Pos [3/6]

#define ITM_TCR_DWTENA_Pos   3U

ITM TCR: DWTENA Position

◆ ITM_TCR_DWTENA_Pos [4/6]

#define ITM_TCR_DWTENA_Pos   3U

ITM TCR: DWTENA Position

◆ ITM_TCR_DWTENA_Pos [5/6]

#define ITM_TCR_DWTENA_Pos   3U

ITM TCR: DWTENA Position

◆ ITM_TCR_DWTENA_Pos [6/6]

#define ITM_TCR_DWTENA_Pos   3U

ITM TCR: DWTENA Position

◆ ITM_TCR_GTSFREQ_Msk [1/6]

#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

◆ ITM_TCR_GTSFREQ_Msk [2/6]

#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

◆ ITM_TCR_GTSFREQ_Msk [3/6]

#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

◆ ITM_TCR_GTSFREQ_Msk [4/6]

#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

◆ ITM_TCR_GTSFREQ_Msk [5/6]

#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

◆ ITM_TCR_GTSFREQ_Msk [6/6]

#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

◆ ITM_TCR_GTSFREQ_Pos [1/6]

#define ITM_TCR_GTSFREQ_Pos   10U

ITM TCR: Global timestamp frequency Position

◆ ITM_TCR_GTSFREQ_Pos [2/6]

#define ITM_TCR_GTSFREQ_Pos   10U

ITM TCR: Global timestamp frequency Position

◆ ITM_TCR_GTSFREQ_Pos [3/6]

#define ITM_TCR_GTSFREQ_Pos   10U

ITM TCR: Global timestamp frequency Position

◆ ITM_TCR_GTSFREQ_Pos [4/6]

#define ITM_TCR_GTSFREQ_Pos   10U

ITM TCR: Global timestamp frequency Position

◆ ITM_TCR_GTSFREQ_Pos [5/6]

#define ITM_TCR_GTSFREQ_Pos   10U

ITM TCR: Global timestamp frequency Position

◆ ITM_TCR_GTSFREQ_Pos [6/6]

#define ITM_TCR_GTSFREQ_Pos   10U

ITM TCR: Global timestamp frequency Position

◆ ITM_TCR_ITMENA_Msk [1/6]

#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

◆ ITM_TCR_ITMENA_Msk [2/6]

#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

◆ ITM_TCR_ITMENA_Msk [3/6]

#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

◆ ITM_TCR_ITMENA_Msk [4/6]

#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

◆ ITM_TCR_ITMENA_Msk [5/6]

#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

◆ ITM_TCR_ITMENA_Msk [6/6]

#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

◆ ITM_TCR_ITMENA_Pos [1/6]

#define ITM_TCR_ITMENA_Pos   0U

ITM TCR: ITM Enable bit Position

◆ ITM_TCR_ITMENA_Pos [2/6]

#define ITM_TCR_ITMENA_Pos   0U

ITM TCR: ITM Enable bit Position

◆ ITM_TCR_ITMENA_Pos [3/6]

#define ITM_TCR_ITMENA_Pos   0U

ITM TCR: ITM Enable bit Position

◆ ITM_TCR_ITMENA_Pos [4/6]

#define ITM_TCR_ITMENA_Pos   0U

ITM TCR: ITM Enable bit Position

◆ ITM_TCR_ITMENA_Pos [5/6]

#define ITM_TCR_ITMENA_Pos   0U

ITM TCR: ITM Enable bit Position

◆ ITM_TCR_ITMENA_Pos [6/6]

#define ITM_TCR_ITMENA_Pos   0U

ITM TCR: ITM Enable bit Position

◆ ITM_TCR_STALLENA_Msk [1/2]

#define ITM_TCR_STALLENA_Msk   (1UL << ITM_TCR_STALLENA_Pos)

ITM TCR: STALLENA Mask

◆ ITM_TCR_STALLENA_Msk [2/2]

#define ITM_TCR_STALLENA_Msk   (1UL << ITM_TCR_STALLENA_Pos)

ITM TCR: STALLENA Mask

◆ ITM_TCR_STALLENA_Pos [1/2]

#define ITM_TCR_STALLENA_Pos   5U

ITM TCR: STALLENA Position

◆ ITM_TCR_STALLENA_Pos [2/2]

#define ITM_TCR_STALLENA_Pos   5U

ITM TCR: STALLENA Position

◆ ITM_TCR_SWOENA_Msk [1/6]

#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

◆ ITM_TCR_SWOENA_Msk [2/6]

#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

◆ ITM_TCR_SWOENA_Msk [3/6]

#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

◆ ITM_TCR_SWOENA_Msk [4/6]

#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

◆ ITM_TCR_SWOENA_Msk [5/6]

#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

◆ ITM_TCR_SWOENA_Msk [6/6]

#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

◆ ITM_TCR_SWOENA_Pos [1/6]

#define ITM_TCR_SWOENA_Pos   4U

ITM TCR: SWOENA Position

◆ ITM_TCR_SWOENA_Pos [2/6]

#define ITM_TCR_SWOENA_Pos   4U

ITM TCR: SWOENA Position

◆ ITM_TCR_SWOENA_Pos [3/6]

#define ITM_TCR_SWOENA_Pos   4U

ITM TCR: SWOENA Position

◆ ITM_TCR_SWOENA_Pos [4/6]

#define ITM_TCR_SWOENA_Pos   4U

ITM TCR: SWOENA Position

◆ ITM_TCR_SWOENA_Pos [5/6]

#define ITM_TCR_SWOENA_Pos   4U

ITM TCR: SWOENA Position

◆ ITM_TCR_SWOENA_Pos [6/6]

#define ITM_TCR_SWOENA_Pos   4U

ITM TCR: SWOENA Position

◆ ITM_TCR_SYNCENA_Msk [1/6]

#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

◆ ITM_TCR_SYNCENA_Msk [2/6]

#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

◆ ITM_TCR_SYNCENA_Msk [3/6]

#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

◆ ITM_TCR_SYNCENA_Msk [4/6]

#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

◆ ITM_TCR_SYNCENA_Msk [5/6]

#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

◆ ITM_TCR_SYNCENA_Msk [6/6]

#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

◆ ITM_TCR_SYNCENA_Pos [1/6]

#define ITM_TCR_SYNCENA_Pos   2U

ITM TCR: SYNCENA Position

◆ ITM_TCR_SYNCENA_Pos [2/6]

#define ITM_TCR_SYNCENA_Pos   2U

ITM TCR: SYNCENA Position

◆ ITM_TCR_SYNCENA_Pos [3/6]

#define ITM_TCR_SYNCENA_Pos   2U

ITM TCR: SYNCENA Position

◆ ITM_TCR_SYNCENA_Pos [4/6]

#define ITM_TCR_SYNCENA_Pos   2U

ITM TCR: SYNCENA Position

◆ ITM_TCR_SYNCENA_Pos [5/6]

#define ITM_TCR_SYNCENA_Pos   2U

ITM TCR: SYNCENA Position

◆ ITM_TCR_SYNCENA_Pos [6/6]

#define ITM_TCR_SYNCENA_Pos   2U

ITM TCR: SYNCENA Position

◆ ITM_TCR_TRACEBUSID_Msk [1/2]

#define ITM_TCR_TRACEBUSID_Msk   (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

ITM TCR: ATBID Mask

◆ ITM_TCR_TRACEBUSID_Msk [2/2]

#define ITM_TCR_TRACEBUSID_Msk   (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

ITM TCR: ATBID Mask

◆ ITM_TCR_TraceBusID_Msk [1/4]

#define ITM_TCR_TraceBusID_Msk   (0x7FUL << ITM_TCR_TraceBusID_Pos)

ITM TCR: ATBID Mask

◆ ITM_TCR_TraceBusID_Msk [2/4]

#define ITM_TCR_TraceBusID_Msk   (0x7FUL << ITM_TCR_TraceBusID_Pos)

ITM TCR: ATBID Mask

◆ ITM_TCR_TraceBusID_Msk [3/4]

#define ITM_TCR_TraceBusID_Msk   (0x7FUL << ITM_TCR_TraceBusID_Pos)

ITM TCR: ATBID Mask

◆ ITM_TCR_TraceBusID_Msk [4/4]

#define ITM_TCR_TraceBusID_Msk   (0x7FUL << ITM_TCR_TraceBusID_Pos)

ITM TCR: ATBID Mask

◆ ITM_TCR_TRACEBUSID_Pos [1/2]

#define ITM_TCR_TRACEBUSID_Pos   16U

ITM TCR: ATBID Position

◆ ITM_TCR_TRACEBUSID_Pos [2/2]

#define ITM_TCR_TRACEBUSID_Pos   16U

ITM TCR: ATBID Position

◆ ITM_TCR_TraceBusID_Pos [1/4]

#define ITM_TCR_TraceBusID_Pos   16U

ITM TCR: ATBID Position

◆ ITM_TCR_TraceBusID_Pos [2/4]

#define ITM_TCR_TraceBusID_Pos   16U

ITM TCR: ATBID Position

◆ ITM_TCR_TraceBusID_Pos [3/4]

#define ITM_TCR_TraceBusID_Pos   16U

ITM TCR: ATBID Position

◆ ITM_TCR_TraceBusID_Pos [4/4]

#define ITM_TCR_TraceBusID_Pos   16U

ITM TCR: ATBID Position

◆ ITM_TCR_TSENA_Msk [1/6]

#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

◆ ITM_TCR_TSENA_Msk [2/6]

#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

◆ ITM_TCR_TSENA_Msk [3/6]

#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

◆ ITM_TCR_TSENA_Msk [4/6]

#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

◆ ITM_TCR_TSENA_Msk [5/6]

#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

◆ ITM_TCR_TSENA_Msk [6/6]

#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

◆ ITM_TCR_TSENA_Pos [1/6]

#define ITM_TCR_TSENA_Pos   1U

ITM TCR: TSENA Position

◆ ITM_TCR_TSENA_Pos [2/6]

#define ITM_TCR_TSENA_Pos   1U

ITM TCR: TSENA Position

◆ ITM_TCR_TSENA_Pos [3/6]

#define ITM_TCR_TSENA_Pos   1U

ITM TCR: TSENA Position

◆ ITM_TCR_TSENA_Pos [4/6]

#define ITM_TCR_TSENA_Pos   1U

ITM TCR: TSENA Position

◆ ITM_TCR_TSENA_Pos [5/6]

#define ITM_TCR_TSENA_Pos   1U

ITM TCR: TSENA Position

◆ ITM_TCR_TSENA_Pos [6/6]

#define ITM_TCR_TSENA_Pos   1U

ITM TCR: TSENA Position

◆ ITM_TCR_TSPRESCALE_Msk [1/2]

#define ITM_TCR_TSPRESCALE_Msk   (3UL << ITM_TCR_TSPRESCALE_Pos)

ITM TCR: TSPRESCALE Mask

◆ ITM_TCR_TSPRESCALE_Msk [2/2]

#define ITM_TCR_TSPRESCALE_Msk   (3UL << ITM_TCR_TSPRESCALE_Pos)

ITM TCR: TSPRESCALE Mask

◆ ITM_TCR_TSPrescale_Msk [1/4]

#define ITM_TCR_TSPrescale_Msk   (3UL << ITM_TCR_TSPrescale_Pos)

ITM TCR: TSPrescale Mask

◆ ITM_TCR_TSPrescale_Msk [2/4]

#define ITM_TCR_TSPrescale_Msk   (3UL << ITM_TCR_TSPrescale_Pos)

ITM TCR: TSPrescale Mask

◆ ITM_TCR_TSPrescale_Msk [3/4]

#define ITM_TCR_TSPrescale_Msk   (3UL << ITM_TCR_TSPrescale_Pos)

ITM TCR: TSPrescale Mask

◆ ITM_TCR_TSPrescale_Msk [4/4]

#define ITM_TCR_TSPrescale_Msk   (3UL << ITM_TCR_TSPrescale_Pos)

ITM TCR: TSPrescale Mask

◆ ITM_TCR_TSPRESCALE_Pos [1/2]

#define ITM_TCR_TSPRESCALE_Pos   8U

ITM TCR: TSPRESCALE Position

◆ ITM_TCR_TSPRESCALE_Pos [2/2]

#define ITM_TCR_TSPRESCALE_Pos   8U

ITM TCR: TSPRESCALE Position

◆ ITM_TCR_TSPrescale_Pos [1/4]

#define ITM_TCR_TSPrescale_Pos   8U

ITM TCR: TSPrescale Position

◆ ITM_TCR_TSPrescale_Pos [2/4]

#define ITM_TCR_TSPrescale_Pos   8U

ITM TCR: TSPrescale Position

◆ ITM_TCR_TSPrescale_Pos [3/4]

#define ITM_TCR_TSPrescale_Pos   8U

ITM TCR: TSPrescale Position

◆ ITM_TCR_TSPrescale_Pos [4/4]

#define ITM_TCR_TSPrescale_Pos   8U

ITM TCR: TSPrescale Position

◆ ITM_TPR_PRIVMASK_Msk [1/6]

#define ITM_TPR_PRIVMASK_Msk   (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

◆ ITM_TPR_PRIVMASK_Msk [2/6]

#define ITM_TPR_PRIVMASK_Msk   (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

◆ ITM_TPR_PRIVMASK_Msk [3/6]

#define ITM_TPR_PRIVMASK_Msk   (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

◆ ITM_TPR_PRIVMASK_Msk [4/6]

#define ITM_TPR_PRIVMASK_Msk   (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

◆ ITM_TPR_PRIVMASK_Msk [5/6]

#define ITM_TPR_PRIVMASK_Msk   (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

◆ ITM_TPR_PRIVMASK_Msk [6/6]

#define ITM_TPR_PRIVMASK_Msk   (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

◆ ITM_TPR_PRIVMASK_Pos [1/6]

#define ITM_TPR_PRIVMASK_Pos   0U

ITM TPR: PRIVMASK Position

◆ ITM_TPR_PRIVMASK_Pos [2/6]

#define ITM_TPR_PRIVMASK_Pos   0U

ITM TPR: PRIVMASK Position

◆ ITM_TPR_PRIVMASK_Pos [3/6]

#define ITM_TPR_PRIVMASK_Pos   0U

ITM TPR: PRIVMASK Position

◆ ITM_TPR_PRIVMASK_Pos [4/6]

#define ITM_TPR_PRIVMASK_Pos   0U

ITM TPR: PRIVMASK Position

◆ ITM_TPR_PRIVMASK_Pos [5/6]

#define ITM_TPR_PRIVMASK_Pos   0U

ITM TPR: PRIVMASK Position

◆ ITM_TPR_PRIVMASK_Pos [6/6]

#define ITM_TPR_PRIVMASK_Pos   0U

ITM TPR: PRIVMASK Position

◆ MPU [1/10]

#define MPU   ((MPU_Type *) MPU_BASE )

Memory Protection Unit

◆ MPU [2/10]

#define MPU   ((MPU_Type *) MPU_BASE )

Memory Protection Unit

◆ MPU [3/10]

#define MPU   ((MPU_Type *) MPU_BASE )

Memory Protection Unit

◆ MPU [4/10]

#define MPU   ((MPU_Type *) MPU_BASE )

Memory Protection Unit

◆ MPU [5/10]

#define MPU   ((MPU_Type *) MPU_BASE )

Memory Protection Unit

◆ MPU [6/10]

#define MPU   ((MPU_Type *) MPU_BASE )

Memory Protection Unit

◆ MPU [7/10]

#define MPU   ((MPU_Type *) MPU_BASE )

Memory Protection Unit

◆ MPU [8/10]

#define MPU   ((MPU_Type *) MPU_BASE )

Memory Protection Unit

◆ MPU [9/10]

#define MPU   ((MPU_Type *) MPU_BASE )

Memory Protection Unit

◆ MPU [10/10]

#define MPU   ((MPU_Type *) MPU_BASE )

Memory Protection Unit

◆ MPU_BASE [1/10]

#define MPU_BASE   (SCS_BASE + 0x0D90UL)

Memory Protection Unit

◆ MPU_BASE [2/10]

#define MPU_BASE   (SCS_BASE + 0x0D90UL)

Memory Protection Unit

◆ MPU_BASE [3/10]

#define MPU_BASE   (SCS_BASE + 0x0D90UL)

Memory Protection Unit

◆ MPU_BASE [4/10]

#define MPU_BASE   (SCS_BASE + 0x0D90UL)

Memory Protection Unit

◆ MPU_BASE [5/10]

#define MPU_BASE   (SCS_BASE + 0x0D90UL)

Memory Protection Unit

◆ MPU_BASE [6/10]

#define MPU_BASE   (SCS_BASE + 0x0D90UL)

Memory Protection Unit

◆ MPU_BASE [7/10]

#define MPU_BASE   (SCS_BASE + 0x0D90UL)

Memory Protection Unit

◆ MPU_BASE [8/10]

#define MPU_BASE   (SCS_BASE + 0x0D90UL)

Memory Protection Unit

◆ MPU_BASE [9/10]

#define MPU_BASE   (SCS_BASE + 0x0D90UL)

Memory Protection Unit

◆ MPU_BASE [10/10]

#define MPU_BASE   (SCS_BASE + 0x0D90UL)

Memory Protection Unit

◆ MPU_CTRL_ENABLE_Msk [1/10]

#define MPU_CTRL_ENABLE_Msk   (1UL /*<< MPU_CTRL_ENABLE_Pos*/)

MPU CTRL: ENABLE Mask

◆ MPU_CTRL_ENABLE_Msk [2/10]

#define MPU_CTRL_ENABLE_Msk   (1UL /*<< MPU_CTRL_ENABLE_Pos*/)

MPU CTRL: ENABLE Mask

◆ MPU_CTRL_ENABLE_Msk [3/10]

#define MPU_CTRL_ENABLE_Msk   (1UL /*<< MPU_CTRL_ENABLE_Pos*/)

MPU CTRL: ENABLE Mask

◆ MPU_CTRL_ENABLE_Msk [4/10]

#define MPU_CTRL_ENABLE_Msk   (1UL /*<< MPU_CTRL_ENABLE_Pos*/)

MPU CTRL: ENABLE Mask

◆ MPU_CTRL_ENABLE_Msk [5/10]

#define MPU_CTRL_ENABLE_Msk   (1UL /*<< MPU_CTRL_ENABLE_Pos*/)

MPU CTRL: ENABLE Mask

◆ MPU_CTRL_ENABLE_Msk [6/10]

#define MPU_CTRL_ENABLE_Msk   (1UL /*<< MPU_CTRL_ENABLE_Pos*/)

MPU CTRL: ENABLE Mask

◆ MPU_CTRL_ENABLE_Msk [7/10]

#define MPU_CTRL_ENABLE_Msk   (1UL /*<< MPU_CTRL_ENABLE_Pos*/)

MPU CTRL: ENABLE Mask

◆ MPU_CTRL_ENABLE_Msk [8/10]

#define MPU_CTRL_ENABLE_Msk   (1UL /*<< MPU_CTRL_ENABLE_Pos*/)

MPU CTRL: ENABLE Mask

◆ MPU_CTRL_ENABLE_Msk [9/10]

#define MPU_CTRL_ENABLE_Msk   (1UL /*<< MPU_CTRL_ENABLE_Pos*/)

MPU CTRL: ENABLE Mask

◆ MPU_CTRL_ENABLE_Msk [10/10]

#define MPU_CTRL_ENABLE_Msk   (1UL /*<< MPU_CTRL_ENABLE_Pos*/)

MPU CTRL: ENABLE Mask

◆ MPU_CTRL_ENABLE_Pos [1/10]

#define MPU_CTRL_ENABLE_Pos   0U

MPU CTRL: ENABLE Position

◆ MPU_CTRL_ENABLE_Pos [2/10]

#define MPU_CTRL_ENABLE_Pos   0U

MPU CTRL: ENABLE Position

◆ MPU_CTRL_ENABLE_Pos [3/10]

#define MPU_CTRL_ENABLE_Pos   0U

MPU CTRL: ENABLE Position

◆ MPU_CTRL_ENABLE_Pos [4/10]

#define MPU_CTRL_ENABLE_Pos   0U

MPU CTRL: ENABLE Position

◆ MPU_CTRL_ENABLE_Pos [5/10]

#define MPU_CTRL_ENABLE_Pos   0U

MPU CTRL: ENABLE Position

◆ MPU_CTRL_ENABLE_Pos [6/10]

#define MPU_CTRL_ENABLE_Pos   0U

MPU CTRL: ENABLE Position

◆ MPU_CTRL_ENABLE_Pos [7/10]

#define MPU_CTRL_ENABLE_Pos   0U

MPU CTRL: ENABLE Position

◆ MPU_CTRL_ENABLE_Pos [8/10]

#define MPU_CTRL_ENABLE_Pos   0U

MPU CTRL: ENABLE Position

◆ MPU_CTRL_ENABLE_Pos [9/10]

#define MPU_CTRL_ENABLE_Pos   0U

MPU CTRL: ENABLE Position

◆ MPU_CTRL_ENABLE_Pos [10/10]

#define MPU_CTRL_ENABLE_Pos   0U

MPU CTRL: ENABLE Position

◆ MPU_CTRL_HFNMIENA_Msk [1/10]

#define MPU_CTRL_HFNMIENA_Msk   (1UL << MPU_CTRL_HFNMIENA_Pos)

MPU CTRL: HFNMIENA Mask

◆ MPU_CTRL_HFNMIENA_Msk [2/10]

#define MPU_CTRL_HFNMIENA_Msk   (1UL << MPU_CTRL_HFNMIENA_Pos)

MPU CTRL: HFNMIENA Mask

◆ MPU_CTRL_HFNMIENA_Msk [3/10]

#define MPU_CTRL_HFNMIENA_Msk   (1UL << MPU_CTRL_HFNMIENA_Pos)

MPU CTRL: HFNMIENA Mask

◆ MPU_CTRL_HFNMIENA_Msk [4/10]

#define MPU_CTRL_HFNMIENA_Msk   (1UL << MPU_CTRL_HFNMIENA_Pos)

MPU CTRL: HFNMIENA Mask

◆ MPU_CTRL_HFNMIENA_Msk [5/10]

#define MPU_CTRL_HFNMIENA_Msk   (1UL << MPU_CTRL_HFNMIENA_Pos)

MPU CTRL: HFNMIENA Mask

◆ MPU_CTRL_HFNMIENA_Msk [6/10]

#define MPU_CTRL_HFNMIENA_Msk   (1UL << MPU_CTRL_HFNMIENA_Pos)

MPU CTRL: HFNMIENA Mask

◆ MPU_CTRL_HFNMIENA_Msk [7/10]

#define MPU_CTRL_HFNMIENA_Msk   (1UL << MPU_CTRL_HFNMIENA_Pos)

MPU CTRL: HFNMIENA Mask

◆ MPU_CTRL_HFNMIENA_Msk [8/10]

#define MPU_CTRL_HFNMIENA_Msk   (1UL << MPU_CTRL_HFNMIENA_Pos)

MPU CTRL: HFNMIENA Mask

◆ MPU_CTRL_HFNMIENA_Msk [9/10]

#define MPU_CTRL_HFNMIENA_Msk   (1UL << MPU_CTRL_HFNMIENA_Pos)

MPU CTRL: HFNMIENA Mask

◆ MPU_CTRL_HFNMIENA_Msk [10/10]

#define MPU_CTRL_HFNMIENA_Msk   (1UL << MPU_CTRL_HFNMIENA_Pos)

MPU CTRL: HFNMIENA Mask

◆ MPU_CTRL_HFNMIENA_Pos [1/10]

#define MPU_CTRL_HFNMIENA_Pos   1U

MPU CTRL: HFNMIENA Position

◆ MPU_CTRL_HFNMIENA_Pos [2/10]

#define MPU_CTRL_HFNMIENA_Pos   1U

MPU CTRL: HFNMIENA Position

◆ MPU_CTRL_HFNMIENA_Pos [3/10]

#define MPU_CTRL_HFNMIENA_Pos   1U

MPU CTRL: HFNMIENA Position

◆ MPU_CTRL_HFNMIENA_Pos [4/10]

#define MPU_CTRL_HFNMIENA_Pos   1U

MPU CTRL: HFNMIENA Position

◆ MPU_CTRL_HFNMIENA_Pos [5/10]

#define MPU_CTRL_HFNMIENA_Pos   1U

MPU CTRL: HFNMIENA Position

◆ MPU_CTRL_HFNMIENA_Pos [6/10]

#define MPU_CTRL_HFNMIENA_Pos   1U

MPU CTRL: HFNMIENA Position

◆ MPU_CTRL_HFNMIENA_Pos [7/10]

#define MPU_CTRL_HFNMIENA_Pos   1U

MPU CTRL: HFNMIENA Position

◆ MPU_CTRL_HFNMIENA_Pos [8/10]

#define MPU_CTRL_HFNMIENA_Pos   1U

MPU CTRL: HFNMIENA Position

◆ MPU_CTRL_HFNMIENA_Pos [9/10]

#define MPU_CTRL_HFNMIENA_Pos   1U

MPU CTRL: HFNMIENA Position

◆ MPU_CTRL_HFNMIENA_Pos [10/10]

#define MPU_CTRL_HFNMIENA_Pos   1U

MPU CTRL: HFNMIENA Position

◆ MPU_CTRL_PRIVDEFENA_Msk [1/10]

#define MPU_CTRL_PRIVDEFENA_Msk   (1UL << MPU_CTRL_PRIVDEFENA_Pos)

MPU CTRL: PRIVDEFENA Mask

◆ MPU_CTRL_PRIVDEFENA_Msk [2/10]

#define MPU_CTRL_PRIVDEFENA_Msk   (1UL << MPU_CTRL_PRIVDEFENA_Pos)

MPU CTRL: PRIVDEFENA Mask

◆ MPU_CTRL_PRIVDEFENA_Msk [3/10]

#define MPU_CTRL_PRIVDEFENA_Msk   (1UL << MPU_CTRL_PRIVDEFENA_Pos)

MPU CTRL: PRIVDEFENA Mask

◆ MPU_CTRL_PRIVDEFENA_Msk [4/10]

#define MPU_CTRL_PRIVDEFENA_Msk   (1UL << MPU_CTRL_PRIVDEFENA_Pos)

MPU CTRL: PRIVDEFENA Mask

◆ MPU_CTRL_PRIVDEFENA_Msk [5/10]

#define MPU_CTRL_PRIVDEFENA_Msk   (1UL << MPU_CTRL_PRIVDEFENA_Pos)

MPU CTRL: PRIVDEFENA Mask

◆ MPU_CTRL_PRIVDEFENA_Msk [6/10]

#define MPU_CTRL_PRIVDEFENA_Msk   (1UL << MPU_CTRL_PRIVDEFENA_Pos)

MPU CTRL: PRIVDEFENA Mask

◆ MPU_CTRL_PRIVDEFENA_Msk [7/10]

#define MPU_CTRL_PRIVDEFENA_Msk   (1UL << MPU_CTRL_PRIVDEFENA_Pos)

MPU CTRL: PRIVDEFENA Mask

◆ MPU_CTRL_PRIVDEFENA_Msk [8/10]

#define MPU_CTRL_PRIVDEFENA_Msk   (1UL << MPU_CTRL_PRIVDEFENA_Pos)

MPU CTRL: PRIVDEFENA Mask

◆ MPU_CTRL_PRIVDEFENA_Msk [9/10]

#define MPU_CTRL_PRIVDEFENA_Msk   (1UL << MPU_CTRL_PRIVDEFENA_Pos)

MPU CTRL: PRIVDEFENA Mask

◆ MPU_CTRL_PRIVDEFENA_Msk [10/10]

#define MPU_CTRL_PRIVDEFENA_Msk   (1UL << MPU_CTRL_PRIVDEFENA_Pos)

MPU CTRL: PRIVDEFENA Mask

◆ MPU_CTRL_PRIVDEFENA_Pos [1/10]

#define MPU_CTRL_PRIVDEFENA_Pos   2U

MPU CTRL: PRIVDEFENA Position

◆ MPU_CTRL_PRIVDEFENA_Pos [2/10]

#define MPU_CTRL_PRIVDEFENA_Pos   2U

MPU CTRL: PRIVDEFENA Position

◆ MPU_CTRL_PRIVDEFENA_Pos [3/10]

#define MPU_CTRL_PRIVDEFENA_Pos   2U

MPU CTRL: PRIVDEFENA Position

◆ MPU_CTRL_PRIVDEFENA_Pos [4/10]

#define MPU_CTRL_PRIVDEFENA_Pos   2U

MPU CTRL: PRIVDEFENA Position

◆ MPU_CTRL_PRIVDEFENA_Pos [5/10]

#define MPU_CTRL_PRIVDEFENA_Pos   2U

MPU CTRL: PRIVDEFENA Position

◆ MPU_CTRL_PRIVDEFENA_Pos [6/10]

#define MPU_CTRL_PRIVDEFENA_Pos   2U

MPU CTRL: PRIVDEFENA Position

◆ MPU_CTRL_PRIVDEFENA_Pos [7/10]

#define MPU_CTRL_PRIVDEFENA_Pos   2U

MPU CTRL: PRIVDEFENA Position

◆ MPU_CTRL_PRIVDEFENA_Pos [8/10]

#define MPU_CTRL_PRIVDEFENA_Pos   2U

MPU CTRL: PRIVDEFENA Position

◆ MPU_CTRL_PRIVDEFENA_Pos [9/10]

#define MPU_CTRL_PRIVDEFENA_Pos   2U

MPU CTRL: PRIVDEFENA Position

◆ MPU_CTRL_PRIVDEFENA_Pos [10/10]

#define MPU_CTRL_PRIVDEFENA_Pos   2U

MPU CTRL: PRIVDEFENA Position

◆ MPU_MAIR0_Attr0_Msk

#define MPU_MAIR0_Attr0_Msk   (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)

MPU MAIR0: Attr0 Mask

◆ MPU_MAIR0_Attr0_Pos

#define MPU_MAIR0_Attr0_Pos   0U

MPU MAIR0: Attr0 Position

◆ MPU_MAIR0_Attr1_Msk

#define MPU_MAIR0_Attr1_Msk   (0xFFUL << MPU_MAIR0_Attr1_Pos)

MPU MAIR0: Attr1 Mask

◆ MPU_MAIR0_Attr1_Pos

#define MPU_MAIR0_Attr1_Pos   8U

MPU MAIR0: Attr1 Position

◆ MPU_MAIR0_Attr2_Msk

#define MPU_MAIR0_Attr2_Msk   (0xFFUL << MPU_MAIR0_Attr2_Pos)

MPU MAIR0: Attr2 Mask

◆ MPU_MAIR0_Attr2_Pos

#define MPU_MAIR0_Attr2_Pos   16U

MPU MAIR0: Attr2 Position

◆ MPU_MAIR0_Attr3_Msk

#define MPU_MAIR0_Attr3_Msk   (0xFFUL << MPU_MAIR0_Attr3_Pos)

MPU MAIR0: Attr3 Mask

◆ MPU_MAIR0_Attr3_Pos

#define MPU_MAIR0_Attr3_Pos   24U

MPU MAIR0: Attr3 Position

◆ MPU_MAIR1_Attr4_Msk

#define MPU_MAIR1_Attr4_Msk   (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)

MPU MAIR1: Attr4 Mask

◆ MPU_MAIR1_Attr4_Pos

#define MPU_MAIR1_Attr4_Pos   0U

MPU MAIR1: Attr4 Position

◆ MPU_MAIR1_Attr5_Msk

#define MPU_MAIR1_Attr5_Msk   (0xFFUL << MPU_MAIR1_Attr5_Pos)

MPU MAIR1: Attr5 Mask

◆ MPU_MAIR1_Attr5_Pos

#define MPU_MAIR1_Attr5_Pos   8U

MPU MAIR1: Attr5 Position

◆ MPU_MAIR1_Attr6_Msk

#define MPU_MAIR1_Attr6_Msk   (0xFFUL << MPU_MAIR1_Attr6_Pos)

MPU MAIR1: Attr6 Mask

◆ MPU_MAIR1_Attr6_Pos

#define MPU_MAIR1_Attr6_Pos   16U

MPU MAIR1: Attr6 Position

◆ MPU_MAIR1_Attr7_Msk

#define MPU_MAIR1_Attr7_Msk   (0xFFUL << MPU_MAIR1_Attr7_Pos)

MPU MAIR1: Attr7 Mask

◆ MPU_MAIR1_Attr7_Pos

#define MPU_MAIR1_Attr7_Pos   24U

MPU MAIR1: Attr7 Position

◆ MPU_RASR_AP_Msk [1/6]

#define MPU_RASR_AP_Msk   (0x7UL << MPU_RASR_AP_Pos)

MPU RASR: ATTRS.AP Mask

◆ MPU_RASR_AP_Msk [2/6]

#define MPU_RASR_AP_Msk   (0x7UL << MPU_RASR_AP_Pos)

MPU RASR: ATTRS.AP Mask

◆ MPU_RASR_AP_Msk [3/6]

#define MPU_RASR_AP_Msk   (0x7UL << MPU_RASR_AP_Pos)

MPU RASR: ATTRS.AP Mask

◆ MPU_RASR_AP_Msk [4/6]

#define MPU_RASR_AP_Msk   (0x7UL << MPU_RASR_AP_Pos)

MPU RASR: ATTRS.AP Mask

◆ MPU_RASR_AP_Msk [5/6]

#define MPU_RASR_AP_Msk   (0x7UL << MPU_RASR_AP_Pos)

MPU RASR: ATTRS.AP Mask

◆ MPU_RASR_AP_Msk [6/6]

#define MPU_RASR_AP_Msk   (0x7UL << MPU_RASR_AP_Pos)

MPU RASR: ATTRS.AP Mask

◆ MPU_RASR_AP_Pos [1/6]

#define MPU_RASR_AP_Pos   24U

MPU RASR: ATTRS.AP Position

◆ MPU_RASR_AP_Pos [2/6]

#define MPU_RASR_AP_Pos   24U

MPU RASR: ATTRS.AP Position

◆ MPU_RASR_AP_Pos [3/6]

#define MPU_RASR_AP_Pos   24U

MPU RASR: ATTRS.AP Position

◆ MPU_RASR_AP_Pos [4/6]

#define MPU_RASR_AP_Pos   24U

MPU RASR: ATTRS.AP Position

◆ MPU_RASR_AP_Pos [5/6]

#define MPU_RASR_AP_Pos   24U

MPU RASR: ATTRS.AP Position

◆ MPU_RASR_AP_Pos [6/6]

#define MPU_RASR_AP_Pos   24U

MPU RASR: ATTRS.AP Position

◆ MPU_RASR_ATTRS_Msk [1/6]

#define MPU_RASR_ATTRS_Msk   (0xFFFFUL << MPU_RASR_ATTRS_Pos)

MPU RASR: MPU Region Attribute field Mask

◆ MPU_RASR_ATTRS_Msk [2/6]

#define MPU_RASR_ATTRS_Msk   (0xFFFFUL << MPU_RASR_ATTRS_Pos)

MPU RASR: MPU Region Attribute field Mask

◆ MPU_RASR_ATTRS_Msk [3/6]

#define MPU_RASR_ATTRS_Msk   (0xFFFFUL << MPU_RASR_ATTRS_Pos)

MPU RASR: MPU Region Attribute field Mask

◆ MPU_RASR_ATTRS_Msk [4/6]

#define MPU_RASR_ATTRS_Msk   (0xFFFFUL << MPU_RASR_ATTRS_Pos)

MPU RASR: MPU Region Attribute field Mask

◆ MPU_RASR_ATTRS_Msk [5/6]

#define MPU_RASR_ATTRS_Msk   (0xFFFFUL << MPU_RASR_ATTRS_Pos)

MPU RASR: MPU Region Attribute field Mask

◆ MPU_RASR_ATTRS_Msk [6/6]

#define MPU_RASR_ATTRS_Msk   (0xFFFFUL << MPU_RASR_ATTRS_Pos)

MPU RASR: MPU Region Attribute field Mask

◆ MPU_RASR_ATTRS_Pos [1/6]

#define MPU_RASR_ATTRS_Pos   16U

MPU RASR: MPU Region Attribute field Position

◆ MPU_RASR_ATTRS_Pos [2/6]

#define MPU_RASR_ATTRS_Pos   16U

MPU RASR: MPU Region Attribute field Position

◆ MPU_RASR_ATTRS_Pos [3/6]

#define MPU_RASR_ATTRS_Pos   16U

MPU RASR: MPU Region Attribute field Position

◆ MPU_RASR_ATTRS_Pos [4/6]

#define MPU_RASR_ATTRS_Pos   16U

MPU RASR: MPU Region Attribute field Position

◆ MPU_RASR_ATTRS_Pos [5/6]

#define MPU_RASR_ATTRS_Pos   16U

MPU RASR: MPU Region Attribute field Position

◆ MPU_RASR_ATTRS_Pos [6/6]

#define MPU_RASR_ATTRS_Pos   16U

MPU RASR: MPU Region Attribute field Position

◆ MPU_RASR_B_Msk [1/6]

#define MPU_RASR_B_Msk   (1UL << MPU_RASR_B_Pos)

MPU RASR: ATTRS.B Mask

◆ MPU_RASR_B_Msk [2/6]

#define MPU_RASR_B_Msk   (1UL << MPU_RASR_B_Pos)

MPU RASR: ATTRS.B Mask

◆ MPU_RASR_B_Msk [3/6]

#define MPU_RASR_B_Msk   (1UL << MPU_RASR_B_Pos)

MPU RASR: ATTRS.B Mask

◆ MPU_RASR_B_Msk [4/6]

#define MPU_RASR_B_Msk   (1UL << MPU_RASR_B_Pos)

MPU RASR: ATTRS.B Mask

◆ MPU_RASR_B_Msk [5/6]

#define MPU_RASR_B_Msk   (1UL << MPU_RASR_B_Pos)

MPU RASR: ATTRS.B Mask

◆ MPU_RASR_B_Msk [6/6]

#define MPU_RASR_B_Msk   (1UL << MPU_RASR_B_Pos)

MPU RASR: ATTRS.B Mask

◆ MPU_RASR_B_Pos [1/6]

#define MPU_RASR_B_Pos   16U

MPU RASR: ATTRS.B Position

◆ MPU_RASR_B_Pos [2/6]

#define MPU_RASR_B_Pos   16U

MPU RASR: ATTRS.B Position

◆ MPU_RASR_B_Pos [3/6]

#define MPU_RASR_B_Pos   16U

MPU RASR: ATTRS.B Position

◆ MPU_RASR_B_Pos [4/6]

#define MPU_RASR_B_Pos   16U

MPU RASR: ATTRS.B Position

◆ MPU_RASR_B_Pos [5/6]

#define MPU_RASR_B_Pos   16U

MPU RASR: ATTRS.B Position

◆ MPU_RASR_B_Pos [6/6]

#define MPU_RASR_B_Pos   16U

MPU RASR: ATTRS.B Position

◆ MPU_RASR_C_Msk [1/6]

#define MPU_RASR_C_Msk   (1UL << MPU_RASR_C_Pos)

MPU RASR: ATTRS.C Mask

◆ MPU_RASR_C_Msk [2/6]

#define MPU_RASR_C_Msk   (1UL << MPU_RASR_C_Pos)

MPU RASR: ATTRS.C Mask

◆ MPU_RASR_C_Msk [3/6]

#define MPU_RASR_C_Msk   (1UL << MPU_RASR_C_Pos)

MPU RASR: ATTRS.C Mask

◆ MPU_RASR_C_Msk [4/6]

#define MPU_RASR_C_Msk   (1UL << MPU_RASR_C_Pos)

MPU RASR: ATTRS.C Mask

◆ MPU_RASR_C_Msk [5/6]

#define MPU_RASR_C_Msk   (1UL << MPU_RASR_C_Pos)

MPU RASR: ATTRS.C Mask

◆ MPU_RASR_C_Msk [6/6]

#define MPU_RASR_C_Msk   (1UL << MPU_RASR_C_Pos)

MPU RASR: ATTRS.C Mask

◆ MPU_RASR_C_Pos [1/6]

#define MPU_RASR_C_Pos   17U

MPU RASR: ATTRS.C Position

◆ MPU_RASR_C_Pos [2/6]

#define MPU_RASR_C_Pos   17U

MPU RASR: ATTRS.C Position

◆ MPU_RASR_C_Pos [3/6]

#define MPU_RASR_C_Pos   17U

MPU RASR: ATTRS.C Position

◆ MPU_RASR_C_Pos [4/6]

#define MPU_RASR_C_Pos   17U

MPU RASR: ATTRS.C Position

◆ MPU_RASR_C_Pos [5/6]

#define MPU_RASR_C_Pos   17U

MPU RASR: ATTRS.C Position

◆ MPU_RASR_C_Pos [6/6]

#define MPU_RASR_C_Pos   17U

MPU RASR: ATTRS.C Position

◆ MPU_RASR_ENABLE_Msk [1/6]

#define MPU_RASR_ENABLE_Msk   (1UL /*<< MPU_RASR_ENABLE_Pos*/)

MPU RASR: Region enable bit Disable Mask

◆ MPU_RASR_ENABLE_Msk [2/6]

#define MPU_RASR_ENABLE_Msk   (1UL /*<< MPU_RASR_ENABLE_Pos*/)

MPU RASR: Region enable bit Disable Mask

◆ MPU_RASR_ENABLE_Msk [3/6]

#define MPU_RASR_ENABLE_Msk   (1UL /*<< MPU_RASR_ENABLE_Pos*/)

MPU RASR: Region enable bit Disable Mask

◆ MPU_RASR_ENABLE_Msk [4/6]

#define MPU_RASR_ENABLE_Msk   (1UL /*<< MPU_RASR_ENABLE_Pos*/)

MPU RASR: Region enable bit Disable Mask

◆ MPU_RASR_ENABLE_Msk [5/6]

#define MPU_RASR_ENABLE_Msk   (1UL /*<< MPU_RASR_ENABLE_Pos*/)

MPU RASR: Region enable bit Disable Mask

◆ MPU_RASR_ENABLE_Msk [6/6]

#define MPU_RASR_ENABLE_Msk   (1UL /*<< MPU_RASR_ENABLE_Pos*/)

MPU RASR: Region enable bit Disable Mask

◆ MPU_RASR_ENABLE_Pos [1/6]

#define MPU_RASR_ENABLE_Pos   0U

MPU RASR: Region enable bit Position

◆ MPU_RASR_ENABLE_Pos [2/6]

#define MPU_RASR_ENABLE_Pos   0U

MPU RASR: Region enable bit Position

◆ MPU_RASR_ENABLE_Pos [3/6]

#define MPU_RASR_ENABLE_Pos   0U

MPU RASR: Region enable bit Position

◆ MPU_RASR_ENABLE_Pos [4/6]

#define MPU_RASR_ENABLE_Pos   0U

MPU RASR: Region enable bit Position

◆ MPU_RASR_ENABLE_Pos [5/6]

#define MPU_RASR_ENABLE_Pos   0U

MPU RASR: Region enable bit Position

◆ MPU_RASR_ENABLE_Pos [6/6]

#define MPU_RASR_ENABLE_Pos   0U

MPU RASR: Region enable bit Position

◆ MPU_RASR_S_Msk [1/6]

#define MPU_RASR_S_Msk   (1UL << MPU_RASR_S_Pos)

MPU RASR: ATTRS.S Mask

◆ MPU_RASR_S_Msk [2/6]

#define MPU_RASR_S_Msk   (1UL << MPU_RASR_S_Pos)

MPU RASR: ATTRS.S Mask

◆ MPU_RASR_S_Msk [3/6]

#define MPU_RASR_S_Msk   (1UL << MPU_RASR_S_Pos)

MPU RASR: ATTRS.S Mask

◆ MPU_RASR_S_Msk [4/6]

#define MPU_RASR_S_Msk   (1UL << MPU_RASR_S_Pos)

MPU RASR: ATTRS.S Mask

◆ MPU_RASR_S_Msk [5/6]

#define MPU_RASR_S_Msk   (1UL << MPU_RASR_S_Pos)

MPU RASR: ATTRS.S Mask

◆ MPU_RASR_S_Msk [6/6]

#define MPU_RASR_S_Msk   (1UL << MPU_RASR_S_Pos)

MPU RASR: ATTRS.S Mask

◆ MPU_RASR_S_Pos [1/6]

#define MPU_RASR_S_Pos   18U

MPU RASR: ATTRS.S Position

◆ MPU_RASR_S_Pos [2/6]

#define MPU_RASR_S_Pos   18U

MPU RASR: ATTRS.S Position

◆ MPU_RASR_S_Pos [3/6]

#define MPU_RASR_S_Pos   18U

MPU RASR: ATTRS.S Position

◆ MPU_RASR_S_Pos [4/6]

#define MPU_RASR_S_Pos   18U

MPU RASR: ATTRS.S Position

◆ MPU_RASR_S_Pos [5/6]

#define MPU_RASR_S_Pos   18U

MPU RASR: ATTRS.S Position

◆ MPU_RASR_S_Pos [6/6]

#define MPU_RASR_S_Pos   18U

MPU RASR: ATTRS.S Position

◆ MPU_RASR_SIZE_Msk [1/6]

#define MPU_RASR_SIZE_Msk   (0x1FUL << MPU_RASR_SIZE_Pos)

MPU RASR: Region Size Field Mask

◆ MPU_RASR_SIZE_Msk [2/6]

#define MPU_RASR_SIZE_Msk   (0x1FUL << MPU_RASR_SIZE_Pos)

MPU RASR: Region Size Field Mask

◆ MPU_RASR_SIZE_Msk [3/6]

#define MPU_RASR_SIZE_Msk   (0x1FUL << MPU_RASR_SIZE_Pos)

MPU RASR: Region Size Field Mask

◆ MPU_RASR_SIZE_Msk [4/6]

#define MPU_RASR_SIZE_Msk   (0x1FUL << MPU_RASR_SIZE_Pos)

MPU RASR: Region Size Field Mask

◆ MPU_RASR_SIZE_Msk [5/6]

#define MPU_RASR_SIZE_Msk   (0x1FUL << MPU_RASR_SIZE_Pos)

MPU RASR: Region Size Field Mask

◆ MPU_RASR_SIZE_Msk [6/6]

#define MPU_RASR_SIZE_Msk   (0x1FUL << MPU_RASR_SIZE_Pos)

MPU RASR: Region Size Field Mask

◆ MPU_RASR_SIZE_Pos [1/6]

#define MPU_RASR_SIZE_Pos   1U

MPU RASR: Region Size Field Position

◆ MPU_RASR_SIZE_Pos [2/6]

#define MPU_RASR_SIZE_Pos   1U

MPU RASR: Region Size Field Position

◆ MPU_RASR_SIZE_Pos [3/6]

#define MPU_RASR_SIZE_Pos   1U

MPU RASR: Region Size Field Position

◆ MPU_RASR_SIZE_Pos [4/6]

#define MPU_RASR_SIZE_Pos   1U

MPU RASR: Region Size Field Position

◆ MPU_RASR_SIZE_Pos [5/6]

#define MPU_RASR_SIZE_Pos   1U

MPU RASR: Region Size Field Position

◆ MPU_RASR_SIZE_Pos [6/6]

#define MPU_RASR_SIZE_Pos   1U

MPU RASR: Region Size Field Position

◆ MPU_RASR_SRD_Msk [1/6]

#define MPU_RASR_SRD_Msk   (0xFFUL << MPU_RASR_SRD_Pos)

MPU RASR: Sub-Region Disable Mask

◆ MPU_RASR_SRD_Msk [2/6]

#define MPU_RASR_SRD_Msk   (0xFFUL << MPU_RASR_SRD_Pos)

MPU RASR: Sub-Region Disable Mask

◆ MPU_RASR_SRD_Msk [3/6]

#define MPU_RASR_SRD_Msk   (0xFFUL << MPU_RASR_SRD_Pos)

MPU RASR: Sub-Region Disable Mask

◆ MPU_RASR_SRD_Msk [4/6]

#define MPU_RASR_SRD_Msk   (0xFFUL << MPU_RASR_SRD_Pos)

MPU RASR: Sub-Region Disable Mask

◆ MPU_RASR_SRD_Msk [5/6]

#define MPU_RASR_SRD_Msk   (0xFFUL << MPU_RASR_SRD_Pos)

MPU RASR: Sub-Region Disable Mask

◆ MPU_RASR_SRD_Msk [6/6]

#define MPU_RASR_SRD_Msk   (0xFFUL << MPU_RASR_SRD_Pos)

MPU RASR: Sub-Region Disable Mask

◆ MPU_RASR_SRD_Pos [1/6]

#define MPU_RASR_SRD_Pos   8U

MPU RASR: Sub-Region Disable Position

◆ MPU_RASR_SRD_Pos [2/6]

#define MPU_RASR_SRD_Pos   8U

MPU RASR: Sub-Region Disable Position

◆ MPU_RASR_SRD_Pos [3/6]

#define MPU_RASR_SRD_Pos   8U

MPU RASR: Sub-Region Disable Position

◆ MPU_RASR_SRD_Pos [4/6]

#define MPU_RASR_SRD_Pos   8U

MPU RASR: Sub-Region Disable Position

◆ MPU_RASR_SRD_Pos [5/6]

#define MPU_RASR_SRD_Pos   8U

MPU RASR: Sub-Region Disable Position

◆ MPU_RASR_SRD_Pos [6/6]

#define MPU_RASR_SRD_Pos   8U

MPU RASR: Sub-Region Disable Position

◆ MPU_RASR_TEX_Msk [1/6]

#define MPU_RASR_TEX_Msk   (0x7UL << MPU_RASR_TEX_Pos)

MPU RASR: ATTRS.TEX Mask

◆ MPU_RASR_TEX_Msk [2/6]

#define MPU_RASR_TEX_Msk   (0x7UL << MPU_RASR_TEX_Pos)

MPU RASR: ATTRS.TEX Mask

◆ MPU_RASR_TEX_Msk [3/6]

#define MPU_RASR_TEX_Msk   (0x7UL << MPU_RASR_TEX_Pos)

MPU RASR: ATTRS.TEX Mask

◆ MPU_RASR_TEX_Msk [4/6]

#define MPU_RASR_TEX_Msk   (0x7UL << MPU_RASR_TEX_Pos)

MPU RASR: ATTRS.TEX Mask

◆ MPU_RASR_TEX_Msk [5/6]

#define MPU_RASR_TEX_Msk   (0x7UL << MPU_RASR_TEX_Pos)

MPU RASR: ATTRS.TEX Mask

◆ MPU_RASR_TEX_Msk [6/6]

#define MPU_RASR_TEX_Msk   (0x7UL << MPU_RASR_TEX_Pos)

MPU RASR: ATTRS.TEX Mask

◆ MPU_RASR_TEX_Pos [1/6]

#define MPU_RASR_TEX_Pos   19U

MPU RASR: ATTRS.TEX Position

◆ MPU_RASR_TEX_Pos [2/6]

#define MPU_RASR_TEX_Pos   19U

MPU RASR: ATTRS.TEX Position

◆ MPU_RASR_TEX_Pos [3/6]

#define MPU_RASR_TEX_Pos   19U

MPU RASR: ATTRS.TEX Position

◆ MPU_RASR_TEX_Pos [4/6]

#define MPU_RASR_TEX_Pos   19U

MPU RASR: ATTRS.TEX Position

◆ MPU_RASR_TEX_Pos [5/6]

#define MPU_RASR_TEX_Pos   19U

MPU RASR: ATTRS.TEX Position

◆ MPU_RASR_TEX_Pos [6/6]

#define MPU_RASR_TEX_Pos   19U

MPU RASR: ATTRS.TEX Position

◆ MPU_RASR_XN_Msk [1/6]

#define MPU_RASR_XN_Msk   (1UL << MPU_RASR_XN_Pos)

MPU RASR: ATTRS.XN Mask

◆ MPU_RASR_XN_Msk [2/6]

#define MPU_RASR_XN_Msk   (1UL << MPU_RASR_XN_Pos)

MPU RASR: ATTRS.XN Mask

◆ MPU_RASR_XN_Msk [3/6]

#define MPU_RASR_XN_Msk   (1UL << MPU_RASR_XN_Pos)

MPU RASR: ATTRS.XN Mask

◆ MPU_RASR_XN_Msk [4/6]

#define MPU_RASR_XN_Msk   (1UL << MPU_RASR_XN_Pos)

MPU RASR: ATTRS.XN Mask

◆ MPU_RASR_XN_Msk [5/6]

#define MPU_RASR_XN_Msk   (1UL << MPU_RASR_XN_Pos)

MPU RASR: ATTRS.XN Mask

◆ MPU_RASR_XN_Msk [6/6]

#define MPU_RASR_XN_Msk   (1UL << MPU_RASR_XN_Pos)

MPU RASR: ATTRS.XN Mask

◆ MPU_RASR_XN_Pos [1/6]

#define MPU_RASR_XN_Pos   28U

MPU RASR: ATTRS.XN Position

◆ MPU_RASR_XN_Pos [2/6]

#define MPU_RASR_XN_Pos   28U

MPU RASR: ATTRS.XN Position

◆ MPU_RASR_XN_Pos [3/6]

#define MPU_RASR_XN_Pos   28U

MPU RASR: ATTRS.XN Position

◆ MPU_RASR_XN_Pos [4/6]

#define MPU_RASR_XN_Pos   28U

MPU RASR: ATTRS.XN Position

◆ MPU_RASR_XN_Pos [5/6]

#define MPU_RASR_XN_Pos   28U

MPU RASR: ATTRS.XN Position

◆ MPU_RASR_XN_Pos [6/6]

#define MPU_RASR_XN_Pos   28U

MPU RASR: ATTRS.XN Position

◆ MPU_RBAR_ADDR_Msk [1/6]

#define MPU_RBAR_ADDR_Msk   (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)

MPU RBAR: ADDR Mask

◆ MPU_RBAR_ADDR_Msk [2/6]

#define MPU_RBAR_ADDR_Msk   (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)

MPU RBAR: ADDR Mask

◆ MPU_RBAR_ADDR_Msk [3/6]

#define MPU_RBAR_ADDR_Msk   (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)

MPU RBAR: ADDR Mask

◆ MPU_RBAR_ADDR_Msk [4/6]

#define MPU_RBAR_ADDR_Msk   (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)

MPU RBAR: ADDR Mask

◆ MPU_RBAR_ADDR_Msk [5/6]

#define MPU_RBAR_ADDR_Msk   (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)

MPU RBAR: ADDR Mask

◆ MPU_RBAR_ADDR_Msk [6/6]

#define MPU_RBAR_ADDR_Msk   (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)

MPU RBAR: ADDR Mask

◆ MPU_RBAR_ADDR_Pos [1/6]

#define MPU_RBAR_ADDR_Pos   8U

MPU RBAR: ADDR Position

◆ MPU_RBAR_ADDR_Pos [2/6]

#define MPU_RBAR_ADDR_Pos   5U

MPU RBAR: ADDR Position

◆ MPU_RBAR_ADDR_Pos [3/6]

#define MPU_RBAR_ADDR_Pos   5U

MPU RBAR: ADDR Position

◆ MPU_RBAR_ADDR_Pos [4/6]

#define MPU_RBAR_ADDR_Pos   5U

MPU RBAR: ADDR Position

◆ MPU_RBAR_ADDR_Pos [5/6]

#define MPU_RBAR_ADDR_Pos   8U

MPU RBAR: ADDR Position

◆ MPU_RBAR_ADDR_Pos [6/6]

#define MPU_RBAR_ADDR_Pos   5U

MPU RBAR: ADDR Position

◆ MPU_RBAR_AP_Msk

#define MPU_RBAR_AP_Msk   (0x3UL << MPU_RBAR_AP_Pos)

MPU RBAR: AP Mask

◆ MPU_RBAR_AP_Pos

#define MPU_RBAR_AP_Pos   1U

MPU RBAR: AP Position

◆ MPU_RBAR_BASE_Msk

#define MPU_RBAR_BASE_Msk   (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)

MPU RBAR: BASE Mask

◆ MPU_RBAR_BASE_Pos

#define MPU_RBAR_BASE_Pos   5U

MPU RBAR: BASE Position

◆ MPU_RBAR_REGION_Msk [1/6]

#define MPU_RBAR_REGION_Msk   (0xFUL /*<< MPU_RBAR_REGION_Pos*/)

MPU RBAR: REGION Mask

◆ MPU_RBAR_REGION_Msk [2/6]

#define MPU_RBAR_REGION_Msk   (0xFUL /*<< MPU_RBAR_REGION_Pos*/)

MPU RBAR: REGION Mask

◆ MPU_RBAR_REGION_Msk [3/6]

#define MPU_RBAR_REGION_Msk   (0xFUL /*<< MPU_RBAR_REGION_Pos*/)

MPU RBAR: REGION Mask

◆ MPU_RBAR_REGION_Msk [4/6]

#define MPU_RBAR_REGION_Msk   (0xFUL /*<< MPU_RBAR_REGION_Pos*/)

MPU RBAR: REGION Mask

◆ MPU_RBAR_REGION_Msk [5/6]

#define MPU_RBAR_REGION_Msk   (0xFUL /*<< MPU_RBAR_REGION_Pos*/)

MPU RBAR: REGION Mask

◆ MPU_RBAR_REGION_Msk [6/6]

#define MPU_RBAR_REGION_Msk   (0xFUL /*<< MPU_RBAR_REGION_Pos*/)

MPU RBAR: REGION Mask

◆ MPU_RBAR_REGION_Pos [1/6]

#define MPU_RBAR_REGION_Pos   0U

MPU RBAR: REGION Position

◆ MPU_RBAR_REGION_Pos [2/6]

#define MPU_RBAR_REGION_Pos   0U

MPU RBAR: REGION Position

◆ MPU_RBAR_REGION_Pos [3/6]

#define MPU_RBAR_REGION_Pos   0U

MPU RBAR: REGION Position

◆ MPU_RBAR_REGION_Pos [4/6]

#define MPU_RBAR_REGION_Pos   0U

MPU RBAR: REGION Position

◆ MPU_RBAR_REGION_Pos [5/6]

#define MPU_RBAR_REGION_Pos   0U

MPU RBAR: REGION Position

◆ MPU_RBAR_REGION_Pos [6/6]

#define MPU_RBAR_REGION_Pos   0U

MPU RBAR: REGION Position

◆ MPU_RBAR_SH_Msk

#define MPU_RBAR_SH_Msk   (0x3UL << MPU_RBAR_SH_Pos)

MPU RBAR: SH Mask

◆ MPU_RBAR_SH_Pos

#define MPU_RBAR_SH_Pos   3U

MPU RBAR: SH Position

◆ MPU_RBAR_VALID_Msk [1/6]

#define MPU_RBAR_VALID_Msk   (1UL << MPU_RBAR_VALID_Pos)

MPU RBAR: VALID Mask

◆ MPU_RBAR_VALID_Msk [2/6]

#define MPU_RBAR_VALID_Msk   (1UL << MPU_RBAR_VALID_Pos)

MPU RBAR: VALID Mask

◆ MPU_RBAR_VALID_Msk [3/6]

#define MPU_RBAR_VALID_Msk   (1UL << MPU_RBAR_VALID_Pos)

MPU RBAR: VALID Mask

◆ MPU_RBAR_VALID_Msk [4/6]

#define MPU_RBAR_VALID_Msk   (1UL << MPU_RBAR_VALID_Pos)

MPU RBAR: VALID Mask

◆ MPU_RBAR_VALID_Msk [5/6]

#define MPU_RBAR_VALID_Msk   (1UL << MPU_RBAR_VALID_Pos)

MPU RBAR: VALID Mask

◆ MPU_RBAR_VALID_Msk [6/6]

#define MPU_RBAR_VALID_Msk   (1UL << MPU_RBAR_VALID_Pos)

MPU RBAR: VALID Mask

◆ MPU_RBAR_VALID_Pos [1/6]

#define MPU_RBAR_VALID_Pos   4U

MPU RBAR: VALID Position

◆ MPU_RBAR_VALID_Pos [2/6]

#define MPU_RBAR_VALID_Pos   4U

MPU RBAR: VALID Position

◆ MPU_RBAR_VALID_Pos [3/6]

#define MPU_RBAR_VALID_Pos   4U

MPU RBAR: VALID Position

◆ MPU_RBAR_VALID_Pos [4/6]

#define MPU_RBAR_VALID_Pos   4U

MPU RBAR: VALID Position

◆ MPU_RBAR_VALID_Pos [5/6]

#define MPU_RBAR_VALID_Pos   4U

MPU RBAR: VALID Position

◆ MPU_RBAR_VALID_Pos [6/6]

#define MPU_RBAR_VALID_Pos   4U

MPU RBAR: VALID Position

◆ MPU_RBAR_XN_Msk

#define MPU_RBAR_XN_Msk   (01UL /*<< MPU_RBAR_XN_Pos*/)

MPU RBAR: XN Mask

◆ MPU_RBAR_XN_Pos

#define MPU_RBAR_XN_Pos   0U

MPU RBAR: XN Position

◆ MPU_RLAR_AttrIndx_Msk

#define MPU_RLAR_AttrIndx_Msk   (0x7UL << MPU_RLAR_AttrIndx_Pos)

MPU RLAR: AttrIndx Mask

◆ MPU_RLAR_AttrIndx_Pos

#define MPU_RLAR_AttrIndx_Pos   1U

MPU RLAR: AttrIndx Position

◆ MPU_RLAR_EN_Msk

#define MPU_RLAR_EN_Msk   (1UL /*<< MPU_RLAR_EN_Pos*/)

MPU RLAR: Region enable bit Disable Mask

MPU RLAR: EN Mask

◆ MPU_RLAR_EN_Pos

#define MPU_RLAR_EN_Pos   0U

MPU RLAR: Region enable bit Position

MPU RLAR: EN Position

◆ MPU_RLAR_LIMIT_Msk

#define MPU_RLAR_LIMIT_Msk   (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)

MPU RLAR: LIMIT Mask

◆ MPU_RLAR_LIMIT_Pos

#define MPU_RLAR_LIMIT_Pos   5U

MPU RLAR: LIMIT Position

◆ MPU_RNR_REGION_Msk [1/10]

#define MPU_RNR_REGION_Msk   (0xFFUL /*<< MPU_RNR_REGION_Pos*/)

MPU RNR: REGION Mask

◆ MPU_RNR_REGION_Msk [2/10]

#define MPU_RNR_REGION_Msk   (0xFFUL /*<< MPU_RNR_REGION_Pos*/)

MPU RNR: REGION Mask

◆ MPU_RNR_REGION_Msk [3/10]

#define MPU_RNR_REGION_Msk   (0xFFUL /*<< MPU_RNR_REGION_Pos*/)

MPU RNR: REGION Mask

◆ MPU_RNR_REGION_Msk [4/10]

#define MPU_RNR_REGION_Msk   (0xFFUL /*<< MPU_RNR_REGION_Pos*/)

MPU RNR: REGION Mask

◆ MPU_RNR_REGION_Msk [5/10]

#define MPU_RNR_REGION_Msk   (0xFFUL /*<< MPU_RNR_REGION_Pos*/)

MPU RNR: REGION Mask

◆ MPU_RNR_REGION_Msk [6/10]

#define MPU_RNR_REGION_Msk   (0xFFUL /*<< MPU_RNR_REGION_Pos*/)

MPU RNR: REGION Mask

◆ MPU_RNR_REGION_Msk [7/10]

#define MPU_RNR_REGION_Msk   (0xFFUL /*<< MPU_RNR_REGION_Pos*/)

MPU RNR: REGION Mask

◆ MPU_RNR_REGION_Msk [8/10]

#define MPU_RNR_REGION_Msk   (0xFFUL /*<< MPU_RNR_REGION_Pos*/)

MPU RNR: REGION Mask

◆ MPU_RNR_REGION_Msk [9/10]

#define MPU_RNR_REGION_Msk   (0xFFUL /*<< MPU_RNR_REGION_Pos*/)

MPU RNR: REGION Mask

◆ MPU_RNR_REGION_Msk [10/10]

#define MPU_RNR_REGION_Msk   (0xFFUL /*<< MPU_RNR_REGION_Pos*/)

MPU RNR: REGION Mask

◆ MPU_RNR_REGION_Pos [1/10]

#define MPU_RNR_REGION_Pos   0U

MPU RNR: REGION Position

◆ MPU_RNR_REGION_Pos [2/10]

#define MPU_RNR_REGION_Pos   0U

MPU RNR: REGION Position

◆ MPU_RNR_REGION_Pos [3/10]

#define MPU_RNR_REGION_Pos   0U

MPU RNR: REGION Position

◆ MPU_RNR_REGION_Pos [4/10]

#define MPU_RNR_REGION_Pos   0U

MPU RNR: REGION Position

◆ MPU_RNR_REGION_Pos [5/10]

#define MPU_RNR_REGION_Pos   0U

MPU RNR: REGION Position

◆ MPU_RNR_REGION_Pos [6/10]

#define MPU_RNR_REGION_Pos   0U

MPU RNR: REGION Position

◆ MPU_RNR_REGION_Pos [7/10]

#define MPU_RNR_REGION_Pos   0U

MPU RNR: REGION Position

◆ MPU_RNR_REGION_Pos [8/10]

#define MPU_RNR_REGION_Pos   0U

MPU RNR: REGION Position

◆ MPU_RNR_REGION_Pos [9/10]

#define MPU_RNR_REGION_Pos   0U

MPU RNR: REGION Position

◆ MPU_RNR_REGION_Pos [10/10]

#define MPU_RNR_REGION_Pos   0U

MPU RNR: REGION Position

◆ MPU_TYPE_DREGION_Msk [1/10]

#define MPU_TYPE_DREGION_Msk   (0xFFUL << MPU_TYPE_DREGION_Pos)

MPU TYPE: DREGION Mask

◆ MPU_TYPE_DREGION_Msk [2/10]

#define MPU_TYPE_DREGION_Msk   (0xFFUL << MPU_TYPE_DREGION_Pos)

MPU TYPE: DREGION Mask

◆ MPU_TYPE_DREGION_Msk [3/10]

#define MPU_TYPE_DREGION_Msk   (0xFFUL << MPU_TYPE_DREGION_Pos)

MPU TYPE: DREGION Mask

◆ MPU_TYPE_DREGION_Msk [4/10]

#define MPU_TYPE_DREGION_Msk   (0xFFUL << MPU_TYPE_DREGION_Pos)

MPU TYPE: DREGION Mask

◆ MPU_TYPE_DREGION_Msk [5/10]

#define MPU_TYPE_DREGION_Msk   (0xFFUL << MPU_TYPE_DREGION_Pos)

MPU TYPE: DREGION Mask

◆ MPU_TYPE_DREGION_Msk [6/10]

#define MPU_TYPE_DREGION_Msk   (0xFFUL << MPU_TYPE_DREGION_Pos)

MPU TYPE: DREGION Mask

◆ MPU_TYPE_DREGION_Msk [7/10]

#define MPU_TYPE_DREGION_Msk   (0xFFUL << MPU_TYPE_DREGION_Pos)

MPU TYPE: DREGION Mask

◆ MPU_TYPE_DREGION_Msk [8/10]

#define MPU_TYPE_DREGION_Msk   (0xFFUL << MPU_TYPE_DREGION_Pos)

MPU TYPE: DREGION Mask

◆ MPU_TYPE_DREGION_Msk [9/10]

#define MPU_TYPE_DREGION_Msk   (0xFFUL << MPU_TYPE_DREGION_Pos)

MPU TYPE: DREGION Mask

◆ MPU_TYPE_DREGION_Msk [10/10]

#define MPU_TYPE_DREGION_Msk   (0xFFUL << MPU_TYPE_DREGION_Pos)

MPU TYPE: DREGION Mask

◆ MPU_TYPE_DREGION_Pos [1/10]

#define MPU_TYPE_DREGION_Pos   8U

MPU TYPE: DREGION Position

◆ MPU_TYPE_DREGION_Pos [2/10]

#define MPU_TYPE_DREGION_Pos   8U

MPU TYPE: DREGION Position

◆ MPU_TYPE_DREGION_Pos [3/10]

#define MPU_TYPE_DREGION_Pos   8U

MPU TYPE: DREGION Position

◆ MPU_TYPE_DREGION_Pos [4/10]

#define MPU_TYPE_DREGION_Pos   8U

MPU TYPE: DREGION Position

◆ MPU_TYPE_DREGION_Pos [5/10]

#define MPU_TYPE_DREGION_Pos   8U

MPU TYPE: DREGION Position

◆ MPU_TYPE_DREGION_Pos [6/10]

#define MPU_TYPE_DREGION_Pos   8U

MPU TYPE: DREGION Position

◆ MPU_TYPE_DREGION_Pos [7/10]

#define MPU_TYPE_DREGION_Pos   8U

MPU TYPE: DREGION Position

◆ MPU_TYPE_DREGION_Pos [8/10]

#define MPU_TYPE_DREGION_Pos   8U

MPU TYPE: DREGION Position

◆ MPU_TYPE_DREGION_Pos [9/10]

#define MPU_TYPE_DREGION_Pos   8U

MPU TYPE: DREGION Position

◆ MPU_TYPE_DREGION_Pos [10/10]

#define MPU_TYPE_DREGION_Pos   8U

MPU TYPE: DREGION Position

◆ MPU_TYPE_IREGION_Msk [1/10]

#define MPU_TYPE_IREGION_Msk   (0xFFUL << MPU_TYPE_IREGION_Pos)

MPU TYPE: IREGION Mask

◆ MPU_TYPE_IREGION_Msk [2/10]

#define MPU_TYPE_IREGION_Msk   (0xFFUL << MPU_TYPE_IREGION_Pos)

MPU TYPE: IREGION Mask

◆ MPU_TYPE_IREGION_Msk [3/10]

#define MPU_TYPE_IREGION_Msk   (0xFFUL << MPU_TYPE_IREGION_Pos)

MPU TYPE: IREGION Mask

◆ MPU_TYPE_IREGION_Msk [4/10]

#define MPU_TYPE_IREGION_Msk   (0xFFUL << MPU_TYPE_IREGION_Pos)

MPU TYPE: IREGION Mask

◆ MPU_TYPE_IREGION_Msk [5/10]

#define MPU_TYPE_IREGION_Msk   (0xFFUL << MPU_TYPE_IREGION_Pos)

MPU TYPE: IREGION Mask

◆ MPU_TYPE_IREGION_Msk [6/10]

#define MPU_TYPE_IREGION_Msk   (0xFFUL << MPU_TYPE_IREGION_Pos)

MPU TYPE: IREGION Mask

◆ MPU_TYPE_IREGION_Msk [7/10]

#define MPU_TYPE_IREGION_Msk   (0xFFUL << MPU_TYPE_IREGION_Pos)

MPU TYPE: IREGION Mask

◆ MPU_TYPE_IREGION_Msk [8/10]

#define MPU_TYPE_IREGION_Msk   (0xFFUL << MPU_TYPE_IREGION_Pos)

MPU TYPE: IREGION Mask

◆ MPU_TYPE_IREGION_Msk [9/10]

#define MPU_TYPE_IREGION_Msk   (0xFFUL << MPU_TYPE_IREGION_Pos)

MPU TYPE: IREGION Mask

◆ MPU_TYPE_IREGION_Msk [10/10]

#define MPU_TYPE_IREGION_Msk   (0xFFUL << MPU_TYPE_IREGION_Pos)

MPU TYPE: IREGION Mask

◆ MPU_TYPE_IREGION_Pos [1/10]

#define MPU_TYPE_IREGION_Pos   16U

MPU TYPE: IREGION Position

◆ MPU_TYPE_IREGION_Pos [2/10]

#define MPU_TYPE_IREGION_Pos   16U

MPU TYPE: IREGION Position

◆ MPU_TYPE_IREGION_Pos [3/10]

#define MPU_TYPE_IREGION_Pos   16U

MPU TYPE: IREGION Position

◆ MPU_TYPE_IREGION_Pos [4/10]

#define MPU_TYPE_IREGION_Pos   16U

MPU TYPE: IREGION Position

◆ MPU_TYPE_IREGION_Pos [5/10]

#define MPU_TYPE_IREGION_Pos   16U

MPU TYPE: IREGION Position

◆ MPU_TYPE_IREGION_Pos [6/10]

#define MPU_TYPE_IREGION_Pos   16U

MPU TYPE: IREGION Position

◆ MPU_TYPE_IREGION_Pos [7/10]

#define MPU_TYPE_IREGION_Pos   16U

MPU TYPE: IREGION Position

◆ MPU_TYPE_IREGION_Pos [8/10]

#define MPU_TYPE_IREGION_Pos   16U

MPU TYPE: IREGION Position

◆ MPU_TYPE_IREGION_Pos [9/10]

#define MPU_TYPE_IREGION_Pos   16U

MPU TYPE: IREGION Position

◆ MPU_TYPE_IREGION_Pos [10/10]

#define MPU_TYPE_IREGION_Pos   16U

MPU TYPE: IREGION Position

◆ MPU_TYPE_SEPARATE_Msk [1/10]

#define MPU_TYPE_SEPARATE_Msk   (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)

MPU TYPE: SEPARATE Mask

◆ MPU_TYPE_SEPARATE_Msk [2/10]

#define MPU_TYPE_SEPARATE_Msk   (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)

MPU TYPE: SEPARATE Mask

◆ MPU_TYPE_SEPARATE_Msk [3/10]

#define MPU_TYPE_SEPARATE_Msk   (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)

MPU TYPE: SEPARATE Mask

◆ MPU_TYPE_SEPARATE_Msk [4/10]

#define MPU_TYPE_SEPARATE_Msk   (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)

MPU TYPE: SEPARATE Mask

◆ MPU_TYPE_SEPARATE_Msk [5/10]

#define MPU_TYPE_SEPARATE_Msk   (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)

MPU TYPE: SEPARATE Mask

◆ MPU_TYPE_SEPARATE_Msk [6/10]

#define MPU_TYPE_SEPARATE_Msk   (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)

MPU TYPE: SEPARATE Mask

◆ MPU_TYPE_SEPARATE_Msk [7/10]

#define MPU_TYPE_SEPARATE_Msk   (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)

MPU TYPE: SEPARATE Mask

◆ MPU_TYPE_SEPARATE_Msk [8/10]

#define MPU_TYPE_SEPARATE_Msk   (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)

MPU TYPE: SEPARATE Mask

◆ MPU_TYPE_SEPARATE_Msk [9/10]

#define MPU_TYPE_SEPARATE_Msk   (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)

MPU TYPE: SEPARATE Mask

◆ MPU_TYPE_SEPARATE_Msk [10/10]

#define MPU_TYPE_SEPARATE_Msk   (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)

MPU TYPE: SEPARATE Mask

◆ MPU_TYPE_SEPARATE_Pos [1/10]

#define MPU_TYPE_SEPARATE_Pos   0U

MPU TYPE: SEPARATE Position

◆ MPU_TYPE_SEPARATE_Pos [2/10]

#define MPU_TYPE_SEPARATE_Pos   0U

MPU TYPE: SEPARATE Position

◆ MPU_TYPE_SEPARATE_Pos [3/10]

#define MPU_TYPE_SEPARATE_Pos   0U

MPU TYPE: SEPARATE Position

◆ MPU_TYPE_SEPARATE_Pos [4/10]

#define MPU_TYPE_SEPARATE_Pos   0U

MPU TYPE: SEPARATE Position

◆ MPU_TYPE_SEPARATE_Pos [5/10]

#define MPU_TYPE_SEPARATE_Pos   0U

MPU TYPE: SEPARATE Position

◆ MPU_TYPE_SEPARATE_Pos [6/10]

#define MPU_TYPE_SEPARATE_Pos   0U

MPU TYPE: SEPARATE Position

◆ MPU_TYPE_SEPARATE_Pos [7/10]

#define MPU_TYPE_SEPARATE_Pos   0U

MPU TYPE: SEPARATE Position

◆ MPU_TYPE_SEPARATE_Pos [8/10]

#define MPU_TYPE_SEPARATE_Pos   0U

MPU TYPE: SEPARATE Position

◆ MPU_TYPE_SEPARATE_Pos [9/10]

#define MPU_TYPE_SEPARATE_Pos   0U

MPU TYPE: SEPARATE Position

◆ MPU_TYPE_SEPARATE_Pos [10/10]

#define MPU_TYPE_SEPARATE_Pos   0U

MPU TYPE: SEPARATE Position

◆ NVIC [1/12]

#define NVIC   ((NVIC_Type *) NVIC_BASE )

NVIC configuration struct

◆ NVIC [2/12]

#define NVIC   ((NVIC_Type *) NVIC_BASE )

NVIC configuration struct

◆ NVIC [3/12]

#define NVIC   ((NVIC_Type *) NVIC_BASE )

NVIC configuration struct

◆ NVIC [4/12]

#define NVIC   ((NVIC_Type *) NVIC_BASE )

NVIC configuration struct

◆ NVIC [5/12]

#define NVIC   ((NVIC_Type *) NVIC_BASE )

NVIC configuration struct

◆ NVIC [6/12]

#define NVIC   ((NVIC_Type *) NVIC_BASE )

NVIC configuration struct

◆ NVIC [7/12]

#define NVIC   ((NVIC_Type *) NVIC_BASE )

NVIC configuration struct

◆ NVIC [8/12]

#define NVIC   ((NVIC_Type *) NVIC_BASE )

NVIC configuration struct

◆ NVIC [9/12]

#define NVIC   ((NVIC_Type *) NVIC_BASE )

NVIC configuration struct

◆ NVIC [10/12]

#define NVIC   ((NVIC_Type *) NVIC_BASE )

NVIC configuration struct

◆ NVIC [11/12]

#define NVIC   ((NVIC_Type *) NVIC_BASE )

NVIC configuration struct

◆ NVIC [12/12]

#define NVIC   ((NVIC_Type *) NVIC_BASE )

NVIC configuration struct

◆ NVIC_BASE [1/12]

#define NVIC_BASE   (SCS_BASE + 0x0100UL)

NVIC Base Address

◆ NVIC_BASE [2/12]

#define NVIC_BASE   (SCS_BASE + 0x0100UL)

NVIC Base Address

◆ NVIC_BASE [3/12]

#define NVIC_BASE   (SCS_BASE + 0x0100UL)

NVIC Base Address

◆ NVIC_BASE [4/12]

#define NVIC_BASE   (SCS_BASE + 0x0100UL)

NVIC Base Address

◆ NVIC_BASE [5/12]

#define NVIC_BASE   (SCS_BASE + 0x0100UL)

NVIC Base Address

◆ NVIC_BASE [6/12]

#define NVIC_BASE   (SCS_BASE + 0x0100UL)

NVIC Base Address

◆ NVIC_BASE [7/12]

#define NVIC_BASE   (SCS_BASE + 0x0100UL)

NVIC Base Address

◆ NVIC_BASE [8/12]

#define NVIC_BASE   (SCS_BASE + 0x0100UL)

NVIC Base Address

◆ NVIC_BASE [9/12]

#define NVIC_BASE   (SCS_BASE + 0x0100UL)

NVIC Base Address

◆ NVIC_BASE [10/12]

#define NVIC_BASE   (SCS_BASE + 0x0100UL)

NVIC Base Address

◆ NVIC_BASE [11/12]

#define NVIC_BASE   (SCS_BASE + 0x0100UL)

NVIC Base Address

◆ NVIC_BASE [12/12]

#define NVIC_BASE   (SCS_BASE + 0x0100UL)

NVIC Base Address

◆ NVIC_STIR_INTID_Msk [1/6]

#define NVIC_STIR_INTID_Msk   (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)

STIR: INTLINESNUM Mask

◆ NVIC_STIR_INTID_Msk [2/6]

#define NVIC_STIR_INTID_Msk   (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)

STIR: INTLINESNUM Mask

◆ NVIC_STIR_INTID_Msk [3/6]

#define NVIC_STIR_INTID_Msk   (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)

STIR: INTLINESNUM Mask

◆ NVIC_STIR_INTID_Msk [4/6]

#define NVIC_STIR_INTID_Msk   (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)

STIR: INTLINESNUM Mask

◆ NVIC_STIR_INTID_Msk [5/6]

#define NVIC_STIR_INTID_Msk   (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)

STIR: INTLINESNUM Mask

◆ NVIC_STIR_INTID_Msk [6/6]

#define NVIC_STIR_INTID_Msk   (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)

STIR: INTLINESNUM Mask

◆ NVIC_STIR_INTID_Pos [1/6]

#define NVIC_STIR_INTID_Pos   0U

STIR: INTLINESNUM Position

◆ NVIC_STIR_INTID_Pos [2/6]

#define NVIC_STIR_INTID_Pos   0U

STIR: INTLINESNUM Position

◆ NVIC_STIR_INTID_Pos [3/6]

#define NVIC_STIR_INTID_Pos   0U

STIR: INTLINESNUM Position

◆ NVIC_STIR_INTID_Pos [4/6]

#define NVIC_STIR_INTID_Pos   0U

STIR: INTLINESNUM Position

◆ NVIC_STIR_INTID_Pos [5/6]

#define NVIC_STIR_INTID_Pos   0U

STIR: INTLINESNUM Position

◆ NVIC_STIR_INTID_Pos [6/6]

#define NVIC_STIR_INTID_Pos   0U

STIR: INTLINESNUM Position

◆ SCB [1/12]

#define SCB   ((SCB_Type *) SCB_BASE )

SCB configuration struct

◆ SCB [2/12]

#define SCB   ((SCB_Type *) SCB_BASE )

SCB configuration struct

◆ SCB [3/12]

#define SCB   ((SCB_Type *) SCB_BASE )

SCB configuration struct

◆ SCB [4/12]

#define SCB   ((SCB_Type *) SCB_BASE )

SCB configuration struct

◆ SCB [5/12]

#define SCB   ((SCB_Type *) SCB_BASE )

SCB configuration struct

◆ SCB [6/12]

#define SCB   ((SCB_Type *) SCB_BASE )

SCB configuration struct

◆ SCB [7/12]

#define SCB   ((SCB_Type *) SCB_BASE )

SCB configuration struct

◆ SCB [8/12]

#define SCB   ((SCB_Type *) SCB_BASE )

SCB configuration struct

◆ SCB [9/12]

#define SCB   ((SCB_Type *) SCB_BASE )

SCB configuration struct

◆ SCB [10/12]

#define SCB   ((SCB_Type *) SCB_BASE )

SCB configuration struct

◆ SCB [11/12]

#define SCB   ((SCB_Type *) SCB_BASE )

SCB configuration struct

◆ SCB [12/12]

#define SCB   ((SCB_Type *) SCB_BASE )

SCB configuration struct

◆ SCB_ABFSR_AHBP_Msk [1/2]

#define SCB_ABFSR_AHBP_Msk   (1UL << SCB_ABFSR_AHBP_Pos)

SCB ABFSR: AHBP Mask

◆ SCB_ABFSR_AHBP_Msk [2/2]

#define SCB_ABFSR_AHBP_Msk   (1UL << SCB_ABFSR_AHBP_Pos)

SCB ABFSR: AHBP Mask

◆ SCB_ABFSR_AHBP_Pos [1/2]

#define SCB_ABFSR_AHBP_Pos   2U

SCB ABFSR: AHBP Position

◆ SCB_ABFSR_AHBP_Pos [2/2]

#define SCB_ABFSR_AHBP_Pos   2U

SCB ABFSR: AHBP Position

◆ SCB_ABFSR_AXIM_Msk [1/2]

#define SCB_ABFSR_AXIM_Msk   (1UL << SCB_ABFSR_AXIM_Pos)

SCB ABFSR: AXIM Mask

◆ SCB_ABFSR_AXIM_Msk [2/2]

#define SCB_ABFSR_AXIM_Msk   (1UL << SCB_ABFSR_AXIM_Pos)

SCB ABFSR: AXIM Mask

◆ SCB_ABFSR_AXIM_Pos [1/2]

#define SCB_ABFSR_AXIM_Pos   3U

SCB ABFSR: AXIM Position

◆ SCB_ABFSR_AXIM_Pos [2/2]

#define SCB_ABFSR_AXIM_Pos   3U

SCB ABFSR: AXIM Position

◆ SCB_ABFSR_AXIMTYPE_Msk [1/2]

#define SCB_ABFSR_AXIMTYPE_Msk   (3UL << SCB_ABFSR_AXIMTYPE_Pos)

SCB ABFSR: AXIMTYPE Mask

◆ SCB_ABFSR_AXIMTYPE_Msk [2/2]

#define SCB_ABFSR_AXIMTYPE_Msk   (3UL << SCB_ABFSR_AXIMTYPE_Pos)

SCB ABFSR: AXIMTYPE Mask

◆ SCB_ABFSR_AXIMTYPE_Pos [1/2]

#define SCB_ABFSR_AXIMTYPE_Pos   8U

SCB ABFSR: AXIMTYPE Position

◆ SCB_ABFSR_AXIMTYPE_Pos [2/2]

#define SCB_ABFSR_AXIMTYPE_Pos   8U

SCB ABFSR: AXIMTYPE Position

◆ SCB_ABFSR_DTCM_Msk [1/2]

#define SCB_ABFSR_DTCM_Msk   (1UL << SCB_ABFSR_DTCM_Pos)

SCB ABFSR: DTCM Mask

◆ SCB_ABFSR_DTCM_Msk [2/2]

#define SCB_ABFSR_DTCM_Msk   (1UL << SCB_ABFSR_DTCM_Pos)

SCB ABFSR: DTCM Mask

◆ SCB_ABFSR_DTCM_Pos [1/2]

#define SCB_ABFSR_DTCM_Pos   1U

SCB ABFSR: DTCM Position

◆ SCB_ABFSR_DTCM_Pos [2/2]

#define SCB_ABFSR_DTCM_Pos   1U

SCB ABFSR: DTCM Position

◆ SCB_ABFSR_EPPB_Msk [1/2]

#define SCB_ABFSR_EPPB_Msk   (1UL << SCB_ABFSR_EPPB_Pos)

SCB ABFSR: EPPB Mask

◆ SCB_ABFSR_EPPB_Msk [2/2]

#define SCB_ABFSR_EPPB_Msk   (1UL << SCB_ABFSR_EPPB_Pos)

SCB ABFSR: EPPB Mask

◆ SCB_ABFSR_EPPB_Pos [1/2]

#define SCB_ABFSR_EPPB_Pos   4U

SCB ABFSR: EPPB Position

◆ SCB_ABFSR_EPPB_Pos [2/2]

#define SCB_ABFSR_EPPB_Pos   4U

SCB ABFSR: EPPB Position

◆ SCB_ABFSR_ITCM_Msk [1/2]

#define SCB_ABFSR_ITCM_Msk   (1UL /*<< SCB_ABFSR_ITCM_Pos*/)

SCB ABFSR: ITCM Mask

◆ SCB_ABFSR_ITCM_Msk [2/2]

#define SCB_ABFSR_ITCM_Msk   (1UL /*<< SCB_ABFSR_ITCM_Pos*/)

SCB ABFSR: ITCM Mask

◆ SCB_ABFSR_ITCM_Pos [1/2]

#define SCB_ABFSR_ITCM_Pos   0U

SCB ABFSR: ITCM Position

◆ SCB_ABFSR_ITCM_Pos [2/2]

#define SCB_ABFSR_ITCM_Pos   0U

SCB ABFSR: ITCM Position

◆ SCB_AHBPCR_EN_Msk [1/2]

#define SCB_AHBPCR_EN_Msk   (1UL /*<< SCB_AHBPCR_EN_Pos*/)

SCB AHBPCR: EN Mask

◆ SCB_AHBPCR_EN_Msk [2/2]

#define SCB_AHBPCR_EN_Msk   (1UL /*<< SCB_AHBPCR_EN_Pos*/)

SCB AHBPCR: EN Mask

◆ SCB_AHBPCR_EN_Pos [1/2]

#define SCB_AHBPCR_EN_Pos   0U

SCB AHBPCR: EN Position

◆ SCB_AHBPCR_EN_Pos [2/2]

#define SCB_AHBPCR_EN_Pos   0U

SCB AHBPCR: EN Position

◆ SCB_AHBPCR_SZ_Msk [1/2]

#define SCB_AHBPCR_SZ_Msk   (7UL << SCB_AHBPCR_SZ_Pos)

SCB AHBPCR: SZ Mask

◆ SCB_AHBPCR_SZ_Msk [2/2]

#define SCB_AHBPCR_SZ_Msk   (7UL << SCB_AHBPCR_SZ_Pos)

SCB AHBPCR: SZ Mask

◆ SCB_AHBPCR_SZ_Pos [1/2]

#define SCB_AHBPCR_SZ_Pos   1U

SCB AHBPCR: SZ Position

◆ SCB_AHBPCR_SZ_Pos [2/2]

#define SCB_AHBPCR_SZ_Pos   1U

SCB AHBPCR: SZ Position

◆ SCB_AHBSCR_CTL_Msk [1/2]

#define SCB_AHBSCR_CTL_Msk   (3UL /*<< SCB_AHBPCR_CTL_Pos*/)

SCB AHBSCR: CTL Mask

◆ SCB_AHBSCR_CTL_Msk [2/2]

#define SCB_AHBSCR_CTL_Msk   (3UL /*<< SCB_AHBPCR_CTL_Pos*/)

SCB AHBSCR: CTL Mask

◆ SCB_AHBSCR_CTL_Pos [1/2]

#define SCB_AHBSCR_CTL_Pos   0U

SCB AHBSCR: CTL Position

◆ SCB_AHBSCR_CTL_Pos [2/2]

#define SCB_AHBSCR_CTL_Pos   0U

SCB AHBSCR: CTL Position

◆ SCB_AHBSCR_INITCOUNT_Msk [1/2]

#define SCB_AHBSCR_INITCOUNT_Msk   (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)

SCB AHBSCR: INITCOUNT Mask

◆ SCB_AHBSCR_INITCOUNT_Msk [2/2]

#define SCB_AHBSCR_INITCOUNT_Msk   (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)

SCB AHBSCR: INITCOUNT Mask

◆ SCB_AHBSCR_INITCOUNT_Pos [1/2]

#define SCB_AHBSCR_INITCOUNT_Pos   11U

SCB AHBSCR: INITCOUNT Position

◆ SCB_AHBSCR_INITCOUNT_Pos [2/2]

#define SCB_AHBSCR_INITCOUNT_Pos   11U

SCB AHBSCR: INITCOUNT Position

◆ SCB_AHBSCR_TPRI_Msk [1/2]

#define SCB_AHBSCR_TPRI_Msk   (0x1FFUL << SCB_AHBPCR_TPRI_Pos)

SCB AHBSCR: TPRI Mask

◆ SCB_AHBSCR_TPRI_Msk [2/2]

#define SCB_AHBSCR_TPRI_Msk   (0x1FFUL << SCB_AHBPCR_TPRI_Pos)

SCB AHBSCR: TPRI Mask

◆ SCB_AHBSCR_TPRI_Pos [1/2]

#define SCB_AHBSCR_TPRI_Pos   2U

SCB AHBSCR: TPRI Position

◆ SCB_AHBSCR_TPRI_Pos [2/2]

#define SCB_AHBSCR_TPRI_Pos   2U

SCB AHBSCR: TPRI Position

◆ SCB_AIRCR_BFHFNMINS_Msk

#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)

SCB AIRCR: BFHFNMINS Mask

◆ SCB_AIRCR_BFHFNMINS_Pos

#define SCB_AIRCR_BFHFNMINS_Pos   13U

SCB AIRCR: BFHFNMINS Position

◆ SCB_AIRCR_ENDIANESS_Msk [1/12]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

◆ SCB_AIRCR_ENDIANESS_Msk [2/12]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

◆ SCB_AIRCR_ENDIANESS_Msk [3/12]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

◆ SCB_AIRCR_ENDIANESS_Msk [4/12]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

◆ SCB_AIRCR_ENDIANESS_Msk [5/12]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

◆ SCB_AIRCR_ENDIANESS_Msk [6/12]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

◆ SCB_AIRCR_ENDIANESS_Msk [7/12]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

◆ SCB_AIRCR_ENDIANESS_Msk [8/12]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

◆ SCB_AIRCR_ENDIANESS_Msk [9/12]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

◆ SCB_AIRCR_ENDIANESS_Msk [10/12]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

◆ SCB_AIRCR_ENDIANESS_Msk [11/12]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

◆ SCB_AIRCR_ENDIANESS_Msk [12/12]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

◆ SCB_AIRCR_ENDIANESS_Pos [1/12]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

◆ SCB_AIRCR_ENDIANESS_Pos [2/12]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

◆ SCB_AIRCR_ENDIANESS_Pos [3/12]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

◆ SCB_AIRCR_ENDIANESS_Pos [4/12]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

◆ SCB_AIRCR_ENDIANESS_Pos [5/12]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

◆ SCB_AIRCR_ENDIANESS_Pos [6/12]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

◆ SCB_AIRCR_ENDIANESS_Pos [7/12]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

◆ SCB_AIRCR_ENDIANESS_Pos [8/12]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

◆ SCB_AIRCR_ENDIANESS_Pos [9/12]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

◆ SCB_AIRCR_ENDIANESS_Pos [10/12]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

◆ SCB_AIRCR_ENDIANESS_Pos [11/12]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

◆ SCB_AIRCR_ENDIANESS_Pos [12/12]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

◆ SCB_AIRCR_PRIGROUP_Msk [1/6]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

◆ SCB_AIRCR_PRIGROUP_Msk [2/6]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

◆ SCB_AIRCR_PRIGROUP_Msk [3/6]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

◆ SCB_AIRCR_PRIGROUP_Msk [4/6]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

◆ SCB_AIRCR_PRIGROUP_Msk [5/6]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

◆ SCB_AIRCR_PRIGROUP_Msk [6/6]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

◆ SCB_AIRCR_PRIGROUP_Pos [1/6]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

◆ SCB_AIRCR_PRIGROUP_Pos [2/6]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

◆ SCB_AIRCR_PRIGROUP_Pos [3/6]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

◆ SCB_AIRCR_PRIGROUP_Pos [4/6]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

◆ SCB_AIRCR_PRIGROUP_Pos [5/6]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

◆ SCB_AIRCR_PRIGROUP_Pos [6/6]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

◆ SCB_AIRCR_PRIS_Msk

#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)

SCB AIRCR: PRIS Mask

◆ SCB_AIRCR_PRIS_Pos

#define SCB_AIRCR_PRIS_Pos   14U

SCB AIRCR: PRIS Position

◆ SCB_AIRCR_SYSRESETREQ_Msk [1/12]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

◆ SCB_AIRCR_SYSRESETREQ_Msk [2/12]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

◆ SCB_AIRCR_SYSRESETREQ_Msk [3/12]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

◆ SCB_AIRCR_SYSRESETREQ_Msk [4/12]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

◆ SCB_AIRCR_SYSRESETREQ_Msk [5/12]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

◆ SCB_AIRCR_SYSRESETREQ_Msk [6/12]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

◆ SCB_AIRCR_SYSRESETREQ_Msk [7/12]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

◆ SCB_AIRCR_SYSRESETREQ_Msk [8/12]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

◆ SCB_AIRCR_SYSRESETREQ_Msk [9/12]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

◆ SCB_AIRCR_SYSRESETREQ_Msk [10/12]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

◆ SCB_AIRCR_SYSRESETREQ_Msk [11/12]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

◆ SCB_AIRCR_SYSRESETREQ_Msk [12/12]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

◆ SCB_AIRCR_SYSRESETREQ_Pos [1/12]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

◆ SCB_AIRCR_SYSRESETREQ_Pos [2/12]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

◆ SCB_AIRCR_SYSRESETREQ_Pos [3/12]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

◆ SCB_AIRCR_SYSRESETREQ_Pos [4/12]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

◆ SCB_AIRCR_SYSRESETREQ_Pos [5/12]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

◆ SCB_AIRCR_SYSRESETREQ_Pos [6/12]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

◆ SCB_AIRCR_SYSRESETREQ_Pos [7/12]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

◆ SCB_AIRCR_SYSRESETREQ_Pos [8/12]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

◆ SCB_AIRCR_SYSRESETREQ_Pos [9/12]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

◆ SCB_AIRCR_SYSRESETREQ_Pos [10/12]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

◆ SCB_AIRCR_SYSRESETREQ_Pos [11/12]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

◆ SCB_AIRCR_SYSRESETREQ_Pos [12/12]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

◆ SCB_AIRCR_SYSRESETREQS_Msk

#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

SCB AIRCR: SYSRESETREQS Mask

◆ SCB_AIRCR_SYSRESETREQS_Pos

#define SCB_AIRCR_SYSRESETREQS_Pos   3U

SCB AIRCR: SYSRESETREQS Position

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [1/12]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [2/12]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [3/12]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [4/12]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [5/12]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [6/12]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [7/12]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [8/12]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [9/12]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [10/12]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [11/12]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [12/12]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [1/12]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [2/12]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [3/12]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [4/12]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [5/12]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [6/12]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [7/12]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [8/12]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [9/12]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [10/12]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [11/12]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [12/12]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

◆ SCB_AIRCR_VECTKEY_Msk [1/12]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

◆ SCB_AIRCR_VECTKEY_Msk [2/12]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

◆ SCB_AIRCR_VECTKEY_Msk [3/12]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

◆ SCB_AIRCR_VECTKEY_Msk [4/12]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

◆ SCB_AIRCR_VECTKEY_Msk [5/12]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

◆ SCB_AIRCR_VECTKEY_Msk [6/12]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

◆ SCB_AIRCR_VECTKEY_Msk [7/12]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

◆ SCB_AIRCR_VECTKEY_Msk [8/12]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

◆ SCB_AIRCR_VECTKEY_Msk [9/12]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

◆ SCB_AIRCR_VECTKEY_Msk [10/12]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

◆ SCB_AIRCR_VECTKEY_Msk [11/12]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

◆ SCB_AIRCR_VECTKEY_Msk [12/12]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

◆ SCB_AIRCR_VECTKEY_Pos [1/12]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

◆ SCB_AIRCR_VECTKEY_Pos [2/12]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

◆ SCB_AIRCR_VECTKEY_Pos [3/12]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

◆ SCB_AIRCR_VECTKEY_Pos [4/12]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

◆ SCB_AIRCR_VECTKEY_Pos [5/12]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

◆ SCB_AIRCR_VECTKEY_Pos [6/12]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

◆ SCB_AIRCR_VECTKEY_Pos [7/12]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

◆ SCB_AIRCR_VECTKEY_Pos [8/12]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

◆ SCB_AIRCR_VECTKEY_Pos [9/12]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

◆ SCB_AIRCR_VECTKEY_Pos [10/12]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

◆ SCB_AIRCR_VECTKEY_Pos [11/12]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

◆ SCB_AIRCR_VECTKEY_Pos [12/12]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

◆ SCB_AIRCR_VECTKEYSTAT_Msk [1/12]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

◆ SCB_AIRCR_VECTKEYSTAT_Msk [2/12]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

◆ SCB_AIRCR_VECTKEYSTAT_Msk [3/12]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

◆ SCB_AIRCR_VECTKEYSTAT_Msk [4/12]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

◆ SCB_AIRCR_VECTKEYSTAT_Msk [5/12]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

◆ SCB_AIRCR_VECTKEYSTAT_Msk [6/12]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

◆ SCB_AIRCR_VECTKEYSTAT_Msk [7/12]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

◆ SCB_AIRCR_VECTKEYSTAT_Msk [8/12]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

◆ SCB_AIRCR_VECTKEYSTAT_Msk [9/12]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

◆ SCB_AIRCR_VECTKEYSTAT_Msk [10/12]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

◆ SCB_AIRCR_VECTKEYSTAT_Msk [11/12]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

◆ SCB_AIRCR_VECTKEYSTAT_Msk [12/12]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

◆ SCB_AIRCR_VECTKEYSTAT_Pos [1/12]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

◆ SCB_AIRCR_VECTKEYSTAT_Pos [2/12]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

◆ SCB_AIRCR_VECTKEYSTAT_Pos [3/12]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

◆ SCB_AIRCR_VECTKEYSTAT_Pos [4/12]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

◆ SCB_AIRCR_VECTKEYSTAT_Pos [5/12]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

◆ SCB_AIRCR_VECTKEYSTAT_Pos [6/12]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

◆ SCB_AIRCR_VECTKEYSTAT_Pos [7/12]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

◆ SCB_AIRCR_VECTKEYSTAT_Pos [8/12]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

◆ SCB_AIRCR_VECTKEYSTAT_Pos [9/12]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

◆ SCB_AIRCR_VECTKEYSTAT_Pos [10/12]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

◆ SCB_AIRCR_VECTKEYSTAT_Pos [11/12]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

◆ SCB_AIRCR_VECTKEYSTAT_Pos [12/12]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

◆ SCB_AIRCR_VECTRESET_Msk [1/4]

#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)

SCB AIRCR: VECTRESET Mask

◆ SCB_AIRCR_VECTRESET_Msk [2/4]

#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)

SCB AIRCR: VECTRESET Mask

◆ SCB_AIRCR_VECTRESET_Msk [3/4]

#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)

SCB AIRCR: VECTRESET Mask

◆ SCB_AIRCR_VECTRESET_Msk [4/4]

#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)

SCB AIRCR: VECTRESET Mask

◆ SCB_AIRCR_VECTRESET_Pos [1/4]

#define SCB_AIRCR_VECTRESET_Pos   0U

SCB AIRCR: VECTRESET Position

◆ SCB_AIRCR_VECTRESET_Pos [2/4]

#define SCB_AIRCR_VECTRESET_Pos   0U

SCB AIRCR: VECTRESET Position

◆ SCB_AIRCR_VECTRESET_Pos [3/4]

#define SCB_AIRCR_VECTRESET_Pos   0U

SCB AIRCR: VECTRESET Position

◆ SCB_AIRCR_VECTRESET_Pos [4/4]

#define SCB_AIRCR_VECTRESET_Pos   0U

SCB AIRCR: VECTRESET Position

◆ SCB_BASE [1/12]

#define SCB_BASE   (SCS_BASE + 0x0D00UL)

System Control Block Base Address

◆ SCB_BASE [2/12]

#define SCB_BASE   (SCS_BASE + 0x0D00UL)

System Control Block Base Address

◆ SCB_BASE [3/12]

#define SCB_BASE   (SCS_BASE + 0x0D00UL)

System Control Block Base Address

◆ SCB_BASE [4/12]

#define SCB_BASE   (SCS_BASE + 0x0D00UL)

System Control Block Base Address

◆ SCB_BASE [5/12]

#define SCB_BASE   (SCS_BASE + 0x0D00UL)

System Control Block Base Address

◆ SCB_BASE [6/12]

#define SCB_BASE   (SCS_BASE + 0x0D00UL)

System Control Block Base Address

◆ SCB_BASE [7/12]

#define SCB_BASE   (SCS_BASE + 0x0D00UL)

System Control Block Base Address

◆ SCB_BASE [8/12]

#define SCB_BASE   (SCS_BASE + 0x0D00UL)

System Control Block Base Address

◆ SCB_BASE [9/12]

#define SCB_BASE   (SCS_BASE + 0x0D00UL)

System Control Block Base Address

◆ SCB_BASE [10/12]

#define SCB_BASE   (SCS_BASE + 0x0D00UL)

System Control Block Base Address

◆ SCB_BASE [11/12]

#define SCB_BASE   (SCS_BASE + 0x0D00UL)

System Control Block Base Address

◆ SCB_BASE [12/12]

#define SCB_BASE   (SCS_BASE + 0x0D00UL)

System Control Block Base Address

◆ SCB_CACR_ECCEN_Msk [1/2]

#define SCB_CACR_ECCEN_Msk   (1UL << SCB_CACR_ECCEN_Pos)

SCB CACR: ECCEN Mask

◆ SCB_CACR_ECCEN_Msk [2/2]

#define SCB_CACR_ECCEN_Msk   (1UL << SCB_CACR_ECCEN_Pos)

SCB CACR: ECCEN Mask

◆ SCB_CACR_ECCEN_Pos [1/2]

#define SCB_CACR_ECCEN_Pos   1U

SCB CACR: ECCEN Position

◆ SCB_CACR_ECCEN_Pos [2/2]

#define SCB_CACR_ECCEN_Pos   1U

SCB CACR: ECCEN Position

◆ SCB_CACR_FORCEWT_Msk [1/2]

#define SCB_CACR_FORCEWT_Msk   (1UL << SCB_CACR_FORCEWT_Pos)

SCB CACR: FORCEWT Mask

◆ SCB_CACR_FORCEWT_Msk [2/2]

#define SCB_CACR_FORCEWT_Msk   (1UL << SCB_CACR_FORCEWT_Pos)

SCB CACR: FORCEWT Mask

◆ SCB_CACR_FORCEWT_Pos [1/2]

#define SCB_CACR_FORCEWT_Pos   2U

SCB CACR: FORCEWT Position

◆ SCB_CACR_FORCEWT_Pos [2/2]

#define SCB_CACR_FORCEWT_Pos   2U

SCB CACR: FORCEWT Position

◆ SCB_CACR_SIWT_Msk [1/2]

#define SCB_CACR_SIWT_Msk   (1UL /*<< SCB_CACR_SIWT_Pos*/)

SCB CACR: SIWT Mask

◆ SCB_CACR_SIWT_Msk [2/2]

#define SCB_CACR_SIWT_Msk   (1UL /*<< SCB_CACR_SIWT_Pos*/)

SCB CACR: SIWT Mask

◆ SCB_CACR_SIWT_Pos [1/2]

#define SCB_CACR_SIWT_Pos   0U

SCB CACR: SIWT Position

◆ SCB_CACR_SIWT_Pos [2/2]

#define SCB_CACR_SIWT_Pos   0U

SCB CACR: SIWT Position

◆ SCB_CCR_BFHFNMIGN_Msk [1/8]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

◆ SCB_CCR_BFHFNMIGN_Msk [2/8]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

◆ SCB_CCR_BFHFNMIGN_Msk [3/8]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

◆ SCB_CCR_BFHFNMIGN_Msk [4/8]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

◆ SCB_CCR_BFHFNMIGN_Msk [5/8]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

◆ SCB_CCR_BFHFNMIGN_Msk [6/8]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

◆ SCB_CCR_BFHFNMIGN_Msk [7/8]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

◆ SCB_CCR_BFHFNMIGN_Msk [8/8]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

◆ SCB_CCR_BFHFNMIGN_Pos [1/8]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

◆ SCB_CCR_BFHFNMIGN_Pos [2/8]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

◆ SCB_CCR_BFHFNMIGN_Pos [3/8]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

◆ SCB_CCR_BFHFNMIGN_Pos [4/8]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

◆ SCB_CCR_BFHFNMIGN_Pos [5/8]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

◆ SCB_CCR_BFHFNMIGN_Pos [6/8]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

◆ SCB_CCR_BFHFNMIGN_Pos [7/8]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

◆ SCB_CCR_BFHFNMIGN_Pos [8/8]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

◆ SCB_CCR_BP_Msk [1/2]

#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)

SCB CCR: BP Mask

SCB CCR: Branch prediction enable bit Mask

◆ SCB_CCR_BP_Msk [2/2]

#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)

SCB CCR: BP Mask

SCB CCR: Branch prediction enable bit Mask

◆ SCB_CCR_BP_Pos [1/2]

#define SCB_CCR_BP_Pos   18U

SCB CCR: BP Position

SCB CCR: Branch prediction enable bit Position

◆ SCB_CCR_BP_Pos [2/2]

#define SCB_CCR_BP_Pos   18U

SCB CCR: BP Position

SCB CCR: Branch prediction enable bit Position

◆ SCB_CCR_DC_Msk [1/2]

#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)

SCB CCR: DC Mask

SCB CCR: Cache enable bit Mask

◆ SCB_CCR_DC_Msk [2/2]

#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)

SCB CCR: DC Mask

SCB CCR: Cache enable bit Mask

◆ SCB_CCR_DC_Pos [1/2]

#define SCB_CCR_DC_Pos   16U

SCB CCR: DC Position

SCB CCR: Cache enable bit Position

◆ SCB_CCR_DC_Pos [2/2]

#define SCB_CCR_DC_Pos   16U

SCB CCR: DC Position

SCB CCR: Cache enable bit Position

◆ SCB_CCR_DIV_0_TRP_Msk [1/8]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

◆ SCB_CCR_DIV_0_TRP_Msk [2/8]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

◆ SCB_CCR_DIV_0_TRP_Msk [3/8]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

◆ SCB_CCR_DIV_0_TRP_Msk [4/8]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

◆ SCB_CCR_DIV_0_TRP_Msk [5/8]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

◆ SCB_CCR_DIV_0_TRP_Msk [6/8]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

◆ SCB_CCR_DIV_0_TRP_Msk [7/8]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

◆ SCB_CCR_DIV_0_TRP_Msk [8/8]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

◆ SCB_CCR_DIV_0_TRP_Pos [1/8]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

◆ SCB_CCR_DIV_0_TRP_Pos [2/8]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

◆ SCB_CCR_DIV_0_TRP_Pos [3/8]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

◆ SCB_CCR_DIV_0_TRP_Pos [4/8]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

◆ SCB_CCR_DIV_0_TRP_Pos [5/8]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

◆ SCB_CCR_DIV_0_TRP_Pos [6/8]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

◆ SCB_CCR_DIV_0_TRP_Pos [7/8]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

◆ SCB_CCR_DIV_0_TRP_Pos [8/8]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

◆ SCB_CCR_IC_Msk [1/2]

#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)

SCB CCR: IC Mask

SCB CCR: Instruction cache enable bit Mask

◆ SCB_CCR_IC_Msk [2/2]

#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)

SCB CCR: IC Mask

SCB CCR: Instruction cache enable bit Mask

◆ SCB_CCR_IC_Pos [1/2]

#define SCB_CCR_IC_Pos   17U

SCB CCR: IC Position

SCB CCR: Instruction cache enable bit Position

◆ SCB_CCR_IC_Pos [2/2]

#define SCB_CCR_IC_Pos   17U

SCB CCR: IC Position

SCB CCR: Instruction cache enable bit Position

◆ SCB_CCR_NONBASETHRDENA_Msk [1/4]

#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)

SCB CCR: NONBASETHRDENA Mask

◆ SCB_CCR_NONBASETHRDENA_Msk [2/4]

#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)

SCB CCR: NONBASETHRDENA Mask

◆ SCB_CCR_NONBASETHRDENA_Msk [3/4]

#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)

SCB CCR: NONBASETHRDENA Mask

◆ SCB_CCR_NONBASETHRDENA_Msk [4/4]

#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)

SCB CCR: NONBASETHRDENA Mask

◆ SCB_CCR_NONBASETHRDENA_Pos [1/4]

#define SCB_CCR_NONBASETHRDENA_Pos   0U

SCB CCR: NONBASETHRDENA Position

◆ SCB_CCR_NONBASETHRDENA_Pos [2/4]

#define SCB_CCR_NONBASETHRDENA_Pos   0U

SCB CCR: NONBASETHRDENA Position

◆ SCB_CCR_NONBASETHRDENA_Pos [3/4]

#define SCB_CCR_NONBASETHRDENA_Pos   0U

SCB CCR: NONBASETHRDENA Position

◆ SCB_CCR_NONBASETHRDENA_Pos [4/4]

#define SCB_CCR_NONBASETHRDENA_Pos   0U

SCB CCR: NONBASETHRDENA Position

◆ SCB_CCR_STKALIGN_Msk [1/8]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

◆ SCB_CCR_STKALIGN_Msk [2/8]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

◆ SCB_CCR_STKALIGN_Msk [3/8]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

◆ SCB_CCR_STKALIGN_Msk [4/8]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

◆ SCB_CCR_STKALIGN_Msk [5/8]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

◆ SCB_CCR_STKALIGN_Msk [6/8]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

◆ SCB_CCR_STKALIGN_Msk [7/8]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

◆ SCB_CCR_STKALIGN_Msk [8/8]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

◆ SCB_CCR_STKALIGN_Pos [1/8]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

◆ SCB_CCR_STKALIGN_Pos [2/8]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

◆ SCB_CCR_STKALIGN_Pos [3/8]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

◆ SCB_CCR_STKALIGN_Pos [4/8]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

◆ SCB_CCR_STKALIGN_Pos [5/8]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

◆ SCB_CCR_STKALIGN_Pos [6/8]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

◆ SCB_CCR_STKALIGN_Pos [7/8]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

◆ SCB_CCR_STKALIGN_Pos [8/8]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

◆ SCB_CCR_STKOFHFNMIGN_Msk

#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

SCB CCR: STKOFHFNMIGN Mask

◆ SCB_CCR_STKOFHFNMIGN_Pos

#define SCB_CCR_STKOFHFNMIGN_Pos   10U

SCB CCR: STKOFHFNMIGN Position

◆ SCB_CCR_UNALIGN_TRP_Msk [1/12]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

◆ SCB_CCR_UNALIGN_TRP_Msk [2/12]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

◆ SCB_CCR_UNALIGN_TRP_Msk [3/12]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

◆ SCB_CCR_UNALIGN_TRP_Msk [4/12]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

◆ SCB_CCR_UNALIGN_TRP_Msk [5/12]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

◆ SCB_CCR_UNALIGN_TRP_Msk [6/12]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

◆ SCB_CCR_UNALIGN_TRP_Msk [7/12]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

◆ SCB_CCR_UNALIGN_TRP_Msk [8/12]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

◆ SCB_CCR_UNALIGN_TRP_Msk [9/12]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

◆ SCB_CCR_UNALIGN_TRP_Msk [10/12]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

◆ SCB_CCR_UNALIGN_TRP_Msk [11/12]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

◆ SCB_CCR_UNALIGN_TRP_Msk [12/12]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

◆ SCB_CCR_UNALIGN_TRP_Pos [1/12]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

◆ SCB_CCR_UNALIGN_TRP_Pos [2/12]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

◆ SCB_CCR_UNALIGN_TRP_Pos [3/12]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

◆ SCB_CCR_UNALIGN_TRP_Pos [4/12]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

◆ SCB_CCR_UNALIGN_TRP_Pos [5/12]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

◆ SCB_CCR_UNALIGN_TRP_Pos [6/12]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

◆ SCB_CCR_UNALIGN_TRP_Pos [7/12]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

◆ SCB_CCR_UNALIGN_TRP_Pos [8/12]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

◆ SCB_CCR_UNALIGN_TRP_Pos [9/12]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

◆ SCB_CCR_UNALIGN_TRP_Pos [10/12]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

◆ SCB_CCR_UNALIGN_TRP_Pos [11/12]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

◆ SCB_CCR_UNALIGN_TRP_Pos [12/12]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

◆ SCB_CCR_USERSETMPEND_Msk [1/8]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

◆ SCB_CCR_USERSETMPEND_Msk [2/8]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

◆ SCB_CCR_USERSETMPEND_Msk [3/8]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

◆ SCB_CCR_USERSETMPEND_Msk [4/8]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

◆ SCB_CCR_USERSETMPEND_Msk [5/8]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

◆ SCB_CCR_USERSETMPEND_Msk [6/8]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

◆ SCB_CCR_USERSETMPEND_Msk [7/8]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

◆ SCB_CCR_USERSETMPEND_Msk [8/8]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

◆ SCB_CCR_USERSETMPEND_Pos [1/8]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

◆ SCB_CCR_USERSETMPEND_Pos [2/8]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

◆ SCB_CCR_USERSETMPEND_Pos [3/8]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

◆ SCB_CCR_USERSETMPEND_Pos [4/8]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

◆ SCB_CCR_USERSETMPEND_Pos [5/8]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

◆ SCB_CCR_USERSETMPEND_Pos [6/8]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

◆ SCB_CCR_USERSETMPEND_Pos [7/8]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

◆ SCB_CCR_USERSETMPEND_Pos [8/8]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

◆ SCB_CCSIDR_ASSOCIATIVITY_Msk [1/2]

#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

SCB CCSIDR: Associativity Mask

◆ SCB_CCSIDR_ASSOCIATIVITY_Msk [2/2]

#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

SCB CCSIDR: Associativity Mask

◆ SCB_CCSIDR_ASSOCIATIVITY_Pos [1/2]

#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U

SCB CCSIDR: Associativity Position

◆ SCB_CCSIDR_ASSOCIATIVITY_Pos [2/2]

#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U

SCB CCSIDR: Associativity Position

◆ SCB_CCSIDR_LINESIZE_Msk [1/2]

#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)

SCB CCSIDR: LineSize Mask

◆ SCB_CCSIDR_LINESIZE_Msk [2/2]

#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)

SCB CCSIDR: LineSize Mask

◆ SCB_CCSIDR_LINESIZE_Pos [1/2]

#define SCB_CCSIDR_LINESIZE_Pos   0U

SCB CCSIDR: LineSize Position

◆ SCB_CCSIDR_LINESIZE_Pos [2/2]

#define SCB_CCSIDR_LINESIZE_Pos   0U

SCB CCSIDR: LineSize Position

◆ SCB_CCSIDR_NUMSETS_Msk [1/2]

#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

SCB CCSIDR: NumSets Mask

◆ SCB_CCSIDR_NUMSETS_Msk [2/2]

#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

SCB CCSIDR: NumSets Mask

◆ SCB_CCSIDR_NUMSETS_Pos [1/2]

#define SCB_CCSIDR_NUMSETS_Pos   13U

SCB CCSIDR: NumSets Position

◆ SCB_CCSIDR_NUMSETS_Pos [2/2]

#define SCB_CCSIDR_NUMSETS_Pos   13U

SCB CCSIDR: NumSets Position

◆ SCB_CCSIDR_RA_Msk [1/2]

#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)

SCB CCSIDR: RA Mask

◆ SCB_CCSIDR_RA_Msk [2/2]

#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)

SCB CCSIDR: RA Mask

◆ SCB_CCSIDR_RA_Pos [1/2]

#define SCB_CCSIDR_RA_Pos   29U

SCB CCSIDR: RA Position

◆ SCB_CCSIDR_RA_Pos [2/2]

#define SCB_CCSIDR_RA_Pos   29U

SCB CCSIDR: RA Position

◆ SCB_CCSIDR_WA_Msk [1/2]

#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)

SCB CCSIDR: WA Mask

◆ SCB_CCSIDR_WA_Msk [2/2]

#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)

SCB CCSIDR: WA Mask

◆ SCB_CCSIDR_WA_Pos [1/2]

#define SCB_CCSIDR_WA_Pos   28U

SCB CCSIDR: WA Position

◆ SCB_CCSIDR_WA_Pos [2/2]

#define SCB_CCSIDR_WA_Pos   28U

SCB CCSIDR: WA Position

◆ SCB_CCSIDR_WB_Msk [1/2]

#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)

SCB CCSIDR: WB Mask

◆ SCB_CCSIDR_WB_Msk [2/2]

#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)

SCB CCSIDR: WB Mask

◆ SCB_CCSIDR_WB_Pos [1/2]

#define SCB_CCSIDR_WB_Pos   30U

SCB CCSIDR: WB Position

◆ SCB_CCSIDR_WB_Pos [2/2]

#define SCB_CCSIDR_WB_Pos   30U

SCB CCSIDR: WB Position

◆ SCB_CCSIDR_WT_Msk [1/2]

#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)

SCB CCSIDR: WT Mask

◆ SCB_CCSIDR_WT_Msk [2/2]

#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)

SCB CCSIDR: WT Mask

◆ SCB_CCSIDR_WT_Pos [1/2]

#define SCB_CCSIDR_WT_Pos   31U

SCB CCSIDR: WT Position

◆ SCB_CCSIDR_WT_Pos [2/2]

#define SCB_CCSIDR_WT_Pos   31U

SCB CCSIDR: WT Position

◆ SCB_CFSR_BFARVALID_Msk [1/6]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

◆ SCB_CFSR_BFARVALID_Msk [2/6]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

◆ SCB_CFSR_BFARVALID_Msk [3/6]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

◆ SCB_CFSR_BFARVALID_Msk [4/6]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

◆ SCB_CFSR_BFARVALID_Msk [5/6]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

◆ SCB_CFSR_BFARVALID_Msk [6/6]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

◆ SCB_CFSR_BFARVALID_Pos [1/6]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

◆ SCB_CFSR_BFARVALID_Pos [2/6]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

◆ SCB_CFSR_BFARVALID_Pos [3/6]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

◆ SCB_CFSR_BFARVALID_Pos [4/6]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

◆ SCB_CFSR_BFARVALID_Pos [5/6]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

◆ SCB_CFSR_BFARVALID_Pos [6/6]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

◆ SCB_CFSR_BUSFAULTSR_Msk [1/6]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

◆ SCB_CFSR_BUSFAULTSR_Msk [2/6]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

◆ SCB_CFSR_BUSFAULTSR_Msk [3/6]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

◆ SCB_CFSR_BUSFAULTSR_Msk [4/6]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

◆ SCB_CFSR_BUSFAULTSR_Msk [5/6]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

◆ SCB_CFSR_BUSFAULTSR_Msk [6/6]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

◆ SCB_CFSR_BUSFAULTSR_Pos [1/6]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

◆ SCB_CFSR_BUSFAULTSR_Pos [2/6]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

◆ SCB_CFSR_BUSFAULTSR_Pos [3/6]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

◆ SCB_CFSR_BUSFAULTSR_Pos [4/6]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

◆ SCB_CFSR_BUSFAULTSR_Pos [5/6]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

◆ SCB_CFSR_BUSFAULTSR_Pos [6/6]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

◆ SCB_CFSR_DACCVIOL_Msk [1/6]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

◆ SCB_CFSR_DACCVIOL_Msk [2/6]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

◆ SCB_CFSR_DACCVIOL_Msk [3/6]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

◆ SCB_CFSR_DACCVIOL_Msk [4/6]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

◆ SCB_CFSR_DACCVIOL_Msk [5/6]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

◆ SCB_CFSR_DACCVIOL_Msk [6/6]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

◆ SCB_CFSR_DACCVIOL_Pos [1/6]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

◆ SCB_CFSR_DACCVIOL_Pos [2/6]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

◆ SCB_CFSR_DACCVIOL_Pos [3/6]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

◆ SCB_CFSR_DACCVIOL_Pos [4/6]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

◆ SCB_CFSR_DACCVIOL_Pos [5/6]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

◆ SCB_CFSR_DACCVIOL_Pos [6/6]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

◆ SCB_CFSR_DIVBYZERO_Msk [1/6]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

◆ SCB_CFSR_DIVBYZERO_Msk [2/6]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

◆ SCB_CFSR_DIVBYZERO_Msk [3/6]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

◆ SCB_CFSR_DIVBYZERO_Msk [4/6]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

◆ SCB_CFSR_DIVBYZERO_Msk [5/6]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

◆ SCB_CFSR_DIVBYZERO_Msk [6/6]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

◆ SCB_CFSR_DIVBYZERO_Pos [1/6]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

◆ SCB_CFSR_DIVBYZERO_Pos [2/6]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

◆ SCB_CFSR_DIVBYZERO_Pos [3/6]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

◆ SCB_CFSR_DIVBYZERO_Pos [4/6]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

◆ SCB_CFSR_DIVBYZERO_Pos [5/6]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

◆ SCB_CFSR_DIVBYZERO_Pos [6/6]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

◆ SCB_CFSR_IACCVIOL_Msk [1/6]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

◆ SCB_CFSR_IACCVIOL_Msk [2/6]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

◆ SCB_CFSR_IACCVIOL_Msk [3/6]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

◆ SCB_CFSR_IACCVIOL_Msk [4/6]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

◆ SCB_CFSR_IACCVIOL_Msk [5/6]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

◆ SCB_CFSR_IACCVIOL_Msk [6/6]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

◆ SCB_CFSR_IACCVIOL_Pos [1/6]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

◆ SCB_CFSR_IACCVIOL_Pos [2/6]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

◆ SCB_CFSR_IACCVIOL_Pos [3/6]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

◆ SCB_CFSR_IACCVIOL_Pos [4/6]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

◆ SCB_CFSR_IACCVIOL_Pos [5/6]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

◆ SCB_CFSR_IACCVIOL_Pos [6/6]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

◆ SCB_CFSR_IBUSERR_Msk [1/6]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

◆ SCB_CFSR_IBUSERR_Msk [2/6]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

◆ SCB_CFSR_IBUSERR_Msk [3/6]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

◆ SCB_CFSR_IBUSERR_Msk [4/6]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

◆ SCB_CFSR_IBUSERR_Msk [5/6]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

◆ SCB_CFSR_IBUSERR_Msk [6/6]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

◆ SCB_CFSR_IBUSERR_Pos [1/6]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

◆ SCB_CFSR_IBUSERR_Pos [2/6]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

◆ SCB_CFSR_IBUSERR_Pos [3/6]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

◆ SCB_CFSR_IBUSERR_Pos [4/6]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

◆ SCB_CFSR_IBUSERR_Pos [5/6]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

◆ SCB_CFSR_IBUSERR_Pos [6/6]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

◆ SCB_CFSR_IMPRECISERR_Msk [1/6]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

◆ SCB_CFSR_IMPRECISERR_Msk [2/6]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

◆ SCB_CFSR_IMPRECISERR_Msk [3/6]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

◆ SCB_CFSR_IMPRECISERR_Msk [4/6]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

◆ SCB_CFSR_IMPRECISERR_Msk [5/6]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

◆ SCB_CFSR_IMPRECISERR_Msk [6/6]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

◆ SCB_CFSR_IMPRECISERR_Pos [1/6]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

◆ SCB_CFSR_IMPRECISERR_Pos [2/6]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

◆ SCB_CFSR_IMPRECISERR_Pos [3/6]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

◆ SCB_CFSR_IMPRECISERR_Pos [4/6]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

◆ SCB_CFSR_IMPRECISERR_Pos [5/6]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

◆ SCB_CFSR_IMPRECISERR_Pos [6/6]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

◆ SCB_CFSR_INVPC_Msk [1/6]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

◆ SCB_CFSR_INVPC_Msk [2/6]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

◆ SCB_CFSR_INVPC_Msk [3/6]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

◆ SCB_CFSR_INVPC_Msk [4/6]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

◆ SCB_CFSR_INVPC_Msk [5/6]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

◆ SCB_CFSR_INVPC_Msk [6/6]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

◆ SCB_CFSR_INVPC_Pos [1/6]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

◆ SCB_CFSR_INVPC_Pos [2/6]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

◆ SCB_CFSR_INVPC_Pos [3/6]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

◆ SCB_CFSR_INVPC_Pos [4/6]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

◆ SCB_CFSR_INVPC_Pos [5/6]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

◆ SCB_CFSR_INVPC_Pos [6/6]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

◆ SCB_CFSR_INVSTATE_Msk [1/6]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

◆ SCB_CFSR_INVSTATE_Msk [2/6]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

◆ SCB_CFSR_INVSTATE_Msk [3/6]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

◆ SCB_CFSR_INVSTATE_Msk [4/6]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

◆ SCB_CFSR_INVSTATE_Msk [5/6]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

◆ SCB_CFSR_INVSTATE_Msk [6/6]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

◆ SCB_CFSR_INVSTATE_Pos [1/6]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

◆ SCB_CFSR_INVSTATE_Pos [2/6]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

◆ SCB_CFSR_INVSTATE_Pos [3/6]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

◆ SCB_CFSR_INVSTATE_Pos [4/6]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

◆ SCB_CFSR_INVSTATE_Pos [5/6]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

◆ SCB_CFSR_INVSTATE_Pos [6/6]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

◆ SCB_CFSR_LSPERR_Msk [1/3]

#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

◆ SCB_CFSR_LSPERR_Msk [2/3]

#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

◆ SCB_CFSR_LSPERR_Msk [3/3]

#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

◆ SCB_CFSR_LSPERR_Pos [1/3]

#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

◆ SCB_CFSR_LSPERR_Pos [2/3]

#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

◆ SCB_CFSR_LSPERR_Pos [3/3]

#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

◆ SCB_CFSR_MEMFAULTSR_Msk [1/6]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

◆ SCB_CFSR_MEMFAULTSR_Msk [2/6]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

◆ SCB_CFSR_MEMFAULTSR_Msk [3/6]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

◆ SCB_CFSR_MEMFAULTSR_Msk [4/6]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

◆ SCB_CFSR_MEMFAULTSR_Msk [5/6]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

◆ SCB_CFSR_MEMFAULTSR_Msk [6/6]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

◆ SCB_CFSR_MEMFAULTSR_Pos [1/6]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

◆ SCB_CFSR_MEMFAULTSR_Pos [2/6]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

◆ SCB_CFSR_MEMFAULTSR_Pos [3/6]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

◆ SCB_CFSR_MEMFAULTSR_Pos [4/6]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

◆ SCB_CFSR_MEMFAULTSR_Pos [5/6]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

◆ SCB_CFSR_MEMFAULTSR_Pos [6/6]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

◆ SCB_CFSR_MLSPERR_Msk [1/3]

#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

◆ SCB_CFSR_MLSPERR_Msk [2/3]

#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

◆ SCB_CFSR_MLSPERR_Msk [3/3]

#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

◆ SCB_CFSR_MLSPERR_Pos [1/3]

#define SCB_CFSR_MLSPERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

◆ SCB_CFSR_MLSPERR_Pos [2/3]

#define SCB_CFSR_MLSPERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

◆ SCB_CFSR_MLSPERR_Pos [3/3]

#define SCB_CFSR_MLSPERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

◆ SCB_CFSR_MMARVALID_Msk [1/6]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

◆ SCB_CFSR_MMARVALID_Msk [2/6]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

◆ SCB_CFSR_MMARVALID_Msk [3/6]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

◆ SCB_CFSR_MMARVALID_Msk [4/6]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

◆ SCB_CFSR_MMARVALID_Msk [5/6]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

◆ SCB_CFSR_MMARVALID_Msk [6/6]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

◆ SCB_CFSR_MMARVALID_Pos [1/6]

#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

◆ SCB_CFSR_MMARVALID_Pos [2/6]

#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

◆ SCB_CFSR_MMARVALID_Pos [3/6]

#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

◆ SCB_CFSR_MMARVALID_Pos [4/6]

#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

◆ SCB_CFSR_MMARVALID_Pos [5/6]

#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

◆ SCB_CFSR_MMARVALID_Pos [6/6]

#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

◆ SCB_CFSR_MSTKERR_Msk [1/6]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

◆ SCB_CFSR_MSTKERR_Msk [2/6]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

◆ SCB_CFSR_MSTKERR_Msk [3/6]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

◆ SCB_CFSR_MSTKERR_Msk [4/6]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

◆ SCB_CFSR_MSTKERR_Msk [5/6]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

◆ SCB_CFSR_MSTKERR_Msk [6/6]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

◆ SCB_CFSR_MSTKERR_Pos [1/6]

#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

◆ SCB_CFSR_MSTKERR_Pos [2/6]

#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

◆ SCB_CFSR_MSTKERR_Pos [3/6]

#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

◆ SCB_CFSR_MSTKERR_Pos [4/6]

#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

◆ SCB_CFSR_MSTKERR_Pos [5/6]

#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

◆ SCB_CFSR_MSTKERR_Pos [6/6]

#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

◆ SCB_CFSR_MUNSTKERR_Msk [1/6]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

◆ SCB_CFSR_MUNSTKERR_Msk [2/6]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

◆ SCB_CFSR_MUNSTKERR_Msk [3/6]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

◆ SCB_CFSR_MUNSTKERR_Msk [4/6]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

◆ SCB_CFSR_MUNSTKERR_Msk [5/6]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

◆ SCB_CFSR_MUNSTKERR_Msk [6/6]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

◆ SCB_CFSR_MUNSTKERR_Pos [1/6]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

◆ SCB_CFSR_MUNSTKERR_Pos [2/6]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

◆ SCB_CFSR_MUNSTKERR_Pos [3/6]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

◆ SCB_CFSR_MUNSTKERR_Pos [4/6]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

◆ SCB_CFSR_MUNSTKERR_Pos [5/6]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

◆ SCB_CFSR_MUNSTKERR_Pos [6/6]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

◆ SCB_CFSR_NOCP_Msk [1/6]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

◆ SCB_CFSR_NOCP_Msk [2/6]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

◆ SCB_CFSR_NOCP_Msk [3/6]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

◆ SCB_CFSR_NOCP_Msk [4/6]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

◆ SCB_CFSR_NOCP_Msk [5/6]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

◆ SCB_CFSR_NOCP_Msk [6/6]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

◆ SCB_CFSR_NOCP_Pos [1/6]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

◆ SCB_CFSR_NOCP_Pos [2/6]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

◆ SCB_CFSR_NOCP_Pos [3/6]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

◆ SCB_CFSR_NOCP_Pos [4/6]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

◆ SCB_CFSR_NOCP_Pos [5/6]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

◆ SCB_CFSR_NOCP_Pos [6/6]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

◆ SCB_CFSR_PRECISERR_Msk [1/6]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

◆ SCB_CFSR_PRECISERR_Msk [2/6]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

◆ SCB_CFSR_PRECISERR_Msk [3/6]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

◆ SCB_CFSR_PRECISERR_Msk [4/6]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

◆ SCB_CFSR_PRECISERR_Msk [5/6]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

◆ SCB_CFSR_PRECISERR_Msk [6/6]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

◆ SCB_CFSR_PRECISERR_Pos [1/6]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

◆ SCB_CFSR_PRECISERR_Pos [2/6]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

◆ SCB_CFSR_PRECISERR_Pos [3/6]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

◆ SCB_CFSR_PRECISERR_Pos [4/6]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

◆ SCB_CFSR_PRECISERR_Pos [5/6]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

◆ SCB_CFSR_PRECISERR_Pos [6/6]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

◆ SCB_CFSR_STKERR_Msk [1/6]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

◆ SCB_CFSR_STKERR_Msk [2/6]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

◆ SCB_CFSR_STKERR_Msk [3/6]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

◆ SCB_CFSR_STKERR_Msk [4/6]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

◆ SCB_CFSR_STKERR_Msk [5/6]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

◆ SCB_CFSR_STKERR_Msk [6/6]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

◆ SCB_CFSR_STKERR_Pos [1/6]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

◆ SCB_CFSR_STKERR_Pos [2/6]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

◆ SCB_CFSR_STKERR_Pos [3/6]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

◆ SCB_CFSR_STKERR_Pos [4/6]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

◆ SCB_CFSR_STKERR_Pos [5/6]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

◆ SCB_CFSR_STKERR_Pos [6/6]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

◆ SCB_CFSR_STKOF_Msk

#define SCB_CFSR_STKOF_Msk   (1UL << SCB_CFSR_STKOF_Pos)

SCB CFSR (UFSR): STKOF Mask

◆ SCB_CFSR_STKOF_Pos

#define SCB_CFSR_STKOF_Pos   (SCB_CFSR_USGFAULTSR_Pos + 4U)

SCB CFSR (UFSR): STKOF Position

◆ SCB_CFSR_UNALIGNED_Msk [1/6]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

◆ SCB_CFSR_UNALIGNED_Msk [2/6]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

◆ SCB_CFSR_UNALIGNED_Msk [3/6]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

◆ SCB_CFSR_UNALIGNED_Msk [4/6]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

◆ SCB_CFSR_UNALIGNED_Msk [5/6]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

◆ SCB_CFSR_UNALIGNED_Msk [6/6]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

◆ SCB_CFSR_UNALIGNED_Pos [1/6]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

◆ SCB_CFSR_UNALIGNED_Pos [2/6]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

◆ SCB_CFSR_UNALIGNED_Pos [3/6]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

◆ SCB_CFSR_UNALIGNED_Pos [4/6]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

◆ SCB_CFSR_UNALIGNED_Pos [5/6]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

◆ SCB_CFSR_UNALIGNED_Pos [6/6]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

◆ SCB_CFSR_UNDEFINSTR_Msk [1/6]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

◆ SCB_CFSR_UNDEFINSTR_Msk [2/6]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

◆ SCB_CFSR_UNDEFINSTR_Msk [3/6]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

◆ SCB_CFSR_UNDEFINSTR_Msk [4/6]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

◆ SCB_CFSR_UNDEFINSTR_Msk [5/6]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

◆ SCB_CFSR_UNDEFINSTR_Msk [6/6]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

◆ SCB_CFSR_UNDEFINSTR_Pos [1/6]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

◆ SCB_CFSR_UNDEFINSTR_Pos [2/6]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

◆ SCB_CFSR_UNDEFINSTR_Pos [3/6]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

◆ SCB_CFSR_UNDEFINSTR_Pos [4/6]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

◆ SCB_CFSR_UNDEFINSTR_Pos [5/6]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

◆ SCB_CFSR_UNDEFINSTR_Pos [6/6]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

◆ SCB_CFSR_UNSTKERR_Msk [1/6]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

◆ SCB_CFSR_UNSTKERR_Msk [2/6]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

◆ SCB_CFSR_UNSTKERR_Msk [3/6]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

◆ SCB_CFSR_UNSTKERR_Msk [4/6]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

◆ SCB_CFSR_UNSTKERR_Msk [5/6]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

◆ SCB_CFSR_UNSTKERR_Msk [6/6]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

◆ SCB_CFSR_UNSTKERR_Pos [1/6]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

◆ SCB_CFSR_UNSTKERR_Pos [2/6]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

◆ SCB_CFSR_UNSTKERR_Pos [3/6]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

◆ SCB_CFSR_UNSTKERR_Pos [4/6]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

◆ SCB_CFSR_UNSTKERR_Pos [5/6]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

◆ SCB_CFSR_UNSTKERR_Pos [6/6]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

◆ SCB_CFSR_USGFAULTSR_Msk [1/6]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

◆ SCB_CFSR_USGFAULTSR_Msk [2/6]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

◆ SCB_CFSR_USGFAULTSR_Msk [3/6]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

◆ SCB_CFSR_USGFAULTSR_Msk [4/6]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

◆ SCB_CFSR_USGFAULTSR_Msk [5/6]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

◆ SCB_CFSR_USGFAULTSR_Msk [6/6]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

◆ SCB_CFSR_USGFAULTSR_Pos [1/6]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

◆ SCB_CFSR_USGFAULTSR_Pos [2/6]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

◆ SCB_CFSR_USGFAULTSR_Pos [3/6]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

◆ SCB_CFSR_USGFAULTSR_Pos [4/6]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

◆ SCB_CFSR_USGFAULTSR_Pos [5/6]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

◆ SCB_CFSR_USGFAULTSR_Pos [6/6]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

◆ SCB_CLIDR_LOC_Msk [1/2]

#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)

SCB CLIDR: LoC Mask

◆ SCB_CLIDR_LOC_Msk [2/2]

#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)

SCB CLIDR: LoC Mask

◆ SCB_CLIDR_LOC_Pos [1/2]

#define SCB_CLIDR_LOC_Pos   24U

SCB CLIDR: LoC Position

◆ SCB_CLIDR_LOC_Pos [2/2]

#define SCB_CLIDR_LOC_Pos   24U

SCB CLIDR: LoC Position

◆ SCB_CLIDR_LOUU_Msk [1/2]

#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)

SCB CLIDR: LoUU Mask

◆ SCB_CLIDR_LOUU_Msk [2/2]

#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)

SCB CLIDR: LoUU Mask

◆ SCB_CLIDR_LOUU_Pos [1/2]

#define SCB_CLIDR_LOUU_Pos   27U

SCB CLIDR: LoUU Position

◆ SCB_CLIDR_LOUU_Pos [2/2]

#define SCB_CLIDR_LOUU_Pos   27U

SCB CLIDR: LoUU Position

◆ SCB_CPUID_ARCHITECTURE_Msk [1/12]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

◆ SCB_CPUID_ARCHITECTURE_Msk [2/12]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

◆ SCB_CPUID_ARCHITECTURE_Msk [3/12]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

◆ SCB_CPUID_ARCHITECTURE_Msk [4/12]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

◆ SCB_CPUID_ARCHITECTURE_Msk [5/12]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

◆ SCB_CPUID_ARCHITECTURE_Msk [6/12]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

◆ SCB_CPUID_ARCHITECTURE_Msk [7/12]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

◆ SCB_CPUID_ARCHITECTURE_Msk [8/12]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

◆ SCB_CPUID_ARCHITECTURE_Msk [9/12]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

◆ SCB_CPUID_ARCHITECTURE_Msk [10/12]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

◆ SCB_CPUID_ARCHITECTURE_Msk [11/12]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

◆ SCB_CPUID_ARCHITECTURE_Msk [12/12]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

◆ SCB_CPUID_ARCHITECTURE_Pos [1/12]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

◆ SCB_CPUID_ARCHITECTURE_Pos [2/12]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

◆ SCB_CPUID_ARCHITECTURE_Pos [3/12]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

◆ SCB_CPUID_ARCHITECTURE_Pos [4/12]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

◆ SCB_CPUID_ARCHITECTURE_Pos [5/12]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

◆ SCB_CPUID_ARCHITECTURE_Pos [6/12]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

◆ SCB_CPUID_ARCHITECTURE_Pos [7/12]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

◆ SCB_CPUID_ARCHITECTURE_Pos [8/12]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

◆ SCB_CPUID_ARCHITECTURE_Pos [9/12]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

◆ SCB_CPUID_ARCHITECTURE_Pos [10/12]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

◆ SCB_CPUID_ARCHITECTURE_Pos [11/12]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

◆ SCB_CPUID_ARCHITECTURE_Pos [12/12]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

◆ SCB_CPUID_IMPLEMENTER_Msk [1/12]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

◆ SCB_CPUID_IMPLEMENTER_Msk [2/12]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

◆ SCB_CPUID_IMPLEMENTER_Msk [3/12]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

◆ SCB_CPUID_IMPLEMENTER_Msk [4/12]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

◆ SCB_CPUID_IMPLEMENTER_Msk [5/12]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

◆ SCB_CPUID_IMPLEMENTER_Msk [6/12]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

◆ SCB_CPUID_IMPLEMENTER_Msk [7/12]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

◆ SCB_CPUID_IMPLEMENTER_Msk [8/12]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

◆ SCB_CPUID_IMPLEMENTER_Msk [9/12]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

◆ SCB_CPUID_IMPLEMENTER_Msk [10/12]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

◆ SCB_CPUID_IMPLEMENTER_Msk [11/12]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

◆ SCB_CPUID_IMPLEMENTER_Msk [12/12]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

◆ SCB_CPUID_IMPLEMENTER_Pos [1/12]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

◆ SCB_CPUID_IMPLEMENTER_Pos [2/12]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

◆ SCB_CPUID_IMPLEMENTER_Pos [3/12]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

◆ SCB_CPUID_IMPLEMENTER_Pos [4/12]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

◆ SCB_CPUID_IMPLEMENTER_Pos [5/12]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

◆ SCB_CPUID_IMPLEMENTER_Pos [6/12]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

◆ SCB_CPUID_IMPLEMENTER_Pos [7/12]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

◆ SCB_CPUID_IMPLEMENTER_Pos [8/12]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

◆ SCB_CPUID_IMPLEMENTER_Pos [9/12]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

◆ SCB_CPUID_IMPLEMENTER_Pos [10/12]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

◆ SCB_CPUID_IMPLEMENTER_Pos [11/12]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

◆ SCB_CPUID_IMPLEMENTER_Pos [12/12]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

◆ SCB_CPUID_PARTNO_Msk [1/12]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

◆ SCB_CPUID_PARTNO_Msk [2/12]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

◆ SCB_CPUID_PARTNO_Msk [3/12]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

◆ SCB_CPUID_PARTNO_Msk [4/12]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

◆ SCB_CPUID_PARTNO_Msk [5/12]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

◆ SCB_CPUID_PARTNO_Msk [6/12]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

◆ SCB_CPUID_PARTNO_Msk [7/12]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

◆ SCB_CPUID_PARTNO_Msk [8/12]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

◆ SCB_CPUID_PARTNO_Msk [9/12]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

◆ SCB_CPUID_PARTNO_Msk [10/12]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

◆ SCB_CPUID_PARTNO_Msk [11/12]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

◆ SCB_CPUID_PARTNO_Msk [12/12]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

◆ SCB_CPUID_PARTNO_Pos [1/12]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

◆ SCB_CPUID_PARTNO_Pos [2/12]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

◆ SCB_CPUID_PARTNO_Pos [3/12]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

◆ SCB_CPUID_PARTNO_Pos [4/12]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

◆ SCB_CPUID_PARTNO_Pos [5/12]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

◆ SCB_CPUID_PARTNO_Pos [6/12]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

◆ SCB_CPUID_PARTNO_Pos [7/12]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

◆ SCB_CPUID_PARTNO_Pos [8/12]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

◆ SCB_CPUID_PARTNO_Pos [9/12]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

◆ SCB_CPUID_PARTNO_Pos [10/12]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

◆ SCB_CPUID_PARTNO_Pos [11/12]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

◆ SCB_CPUID_PARTNO_Pos [12/12]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

◆ SCB_CPUID_REVISION_Msk [1/12]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

◆ SCB_CPUID_REVISION_Msk [2/12]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

◆ SCB_CPUID_REVISION_Msk [3/12]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

◆ SCB_CPUID_REVISION_Msk [4/12]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

◆ SCB_CPUID_REVISION_Msk [5/12]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

◆ SCB_CPUID_REVISION_Msk [6/12]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

◆ SCB_CPUID_REVISION_Msk [7/12]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

◆ SCB_CPUID_REVISION_Msk [8/12]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

◆ SCB_CPUID_REVISION_Msk [9/12]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

◆ SCB_CPUID_REVISION_Msk [10/12]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

◆ SCB_CPUID_REVISION_Msk [11/12]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

◆ SCB_CPUID_REVISION_Msk [12/12]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

◆ SCB_CPUID_REVISION_Pos [1/12]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

◆ SCB_CPUID_REVISION_Pos [2/12]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

◆ SCB_CPUID_REVISION_Pos [3/12]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

◆ SCB_CPUID_REVISION_Pos [4/12]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

◆ SCB_CPUID_REVISION_Pos [5/12]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

◆ SCB_CPUID_REVISION_Pos [6/12]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

◆ SCB_CPUID_REVISION_Pos [7/12]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

◆ SCB_CPUID_REVISION_Pos [8/12]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

◆ SCB_CPUID_REVISION_Pos [9/12]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

◆ SCB_CPUID_REVISION_Pos [10/12]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

◆ SCB_CPUID_REVISION_Pos [11/12]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

◆ SCB_CPUID_REVISION_Pos [12/12]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

◆ SCB_CPUID_VARIANT_Msk [1/12]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

◆ SCB_CPUID_VARIANT_Msk [2/12]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

◆ SCB_CPUID_VARIANT_Msk [3/12]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

◆ SCB_CPUID_VARIANT_Msk [4/12]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

◆ SCB_CPUID_VARIANT_Msk [5/12]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

◆ SCB_CPUID_VARIANT_Msk [6/12]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

◆ SCB_CPUID_VARIANT_Msk [7/12]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

◆ SCB_CPUID_VARIANT_Msk [8/12]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

◆ SCB_CPUID_VARIANT_Msk [9/12]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

◆ SCB_CPUID_VARIANT_Msk [10/12]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

◆ SCB_CPUID_VARIANT_Msk [11/12]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

◆ SCB_CPUID_VARIANT_Msk [12/12]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

◆ SCB_CPUID_VARIANT_Pos [1/12]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

◆ SCB_CPUID_VARIANT_Pos [2/12]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

◆ SCB_CPUID_VARIANT_Pos [3/12]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

◆ SCB_CPUID_VARIANT_Pos [4/12]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

◆ SCB_CPUID_VARIANT_Pos [5/12]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

◆ SCB_CPUID_VARIANT_Pos [6/12]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

◆ SCB_CPUID_VARIANT_Pos [7/12]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

◆ SCB_CPUID_VARIANT_Pos [8/12]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

◆ SCB_CPUID_VARIANT_Pos [9/12]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

◆ SCB_CPUID_VARIANT_Pos [10/12]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

◆ SCB_CPUID_VARIANT_Pos [11/12]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

◆ SCB_CPUID_VARIANT_Pos [12/12]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

◆ SCB_CSSELR_IND_Msk [1/2]

#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)

SCB CSSELR: InD Mask

◆ SCB_CSSELR_IND_Msk [2/2]

#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)

SCB CSSELR: InD Mask

◆ SCB_CSSELR_IND_Pos [1/2]

#define SCB_CSSELR_IND_Pos   0U

SCB CSSELR: InD Position

◆ SCB_CSSELR_IND_Pos [2/2]

#define SCB_CSSELR_IND_Pos   0U

SCB CSSELR: InD Position

◆ SCB_CSSELR_LEVEL_Msk [1/2]

#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)

SCB CSSELR: Level Mask

◆ SCB_CSSELR_LEVEL_Msk [2/2]

#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)

SCB CSSELR: Level Mask

◆ SCB_CSSELR_LEVEL_Pos [1/2]

#define SCB_CSSELR_LEVEL_Pos   1U

SCB CSSELR: Level Position

◆ SCB_CSSELR_LEVEL_Pos [2/2]

#define SCB_CSSELR_LEVEL_Pos   1U

SCB CSSELR: Level Position

◆ SCB_CTR_CWG_Msk [1/2]

#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)

SCB CTR: CWG Mask

◆ SCB_CTR_CWG_Msk [2/2]

#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)

SCB CTR: CWG Mask

◆ SCB_CTR_CWG_Pos [1/2]

#define SCB_CTR_CWG_Pos   24U

SCB CTR: CWG Position

◆ SCB_CTR_CWG_Pos [2/2]

#define SCB_CTR_CWG_Pos   24U

SCB CTR: CWG Position

◆ SCB_CTR_DMINLINE_Msk [1/2]

#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)

SCB CTR: DminLine Mask

◆ SCB_CTR_DMINLINE_Msk [2/2]

#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)

SCB CTR: DminLine Mask

◆ SCB_CTR_DMINLINE_Pos [1/2]

#define SCB_CTR_DMINLINE_Pos   16U

SCB CTR: DminLine Position

◆ SCB_CTR_DMINLINE_Pos [2/2]

#define SCB_CTR_DMINLINE_Pos   16U

SCB CTR: DminLine Position

◆ SCB_CTR_ERG_Msk [1/2]

#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)

SCB CTR: ERG Mask

◆ SCB_CTR_ERG_Msk [2/2]

#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)

SCB CTR: ERG Mask

◆ SCB_CTR_ERG_Pos [1/2]

#define SCB_CTR_ERG_Pos   20U

SCB CTR: ERG Position

◆ SCB_CTR_ERG_Pos [2/2]

#define SCB_CTR_ERG_Pos   20U

SCB CTR: ERG Position

◆ SCB_CTR_FORMAT_Msk [1/2]

#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)

SCB CTR: Format Mask

◆ SCB_CTR_FORMAT_Msk [2/2]

#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)

SCB CTR: Format Mask

◆ SCB_CTR_FORMAT_Pos [1/2]

#define SCB_CTR_FORMAT_Pos   29U

SCB CTR: Format Position

◆ SCB_CTR_FORMAT_Pos [2/2]

#define SCB_CTR_FORMAT_Pos   29U

SCB CTR: Format Position

◆ SCB_CTR_IMINLINE_Msk [1/2]

#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)

SCB CTR: ImInLine Mask

◆ SCB_CTR_IMINLINE_Msk [2/2]

#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)

SCB CTR: ImInLine Mask

◆ SCB_CTR_IMINLINE_Pos [1/2]

#define SCB_CTR_IMINLINE_Pos   0U

SCB CTR: ImInLine Position

◆ SCB_CTR_IMINLINE_Pos [2/2]

#define SCB_CTR_IMINLINE_Pos   0U

SCB CTR: ImInLine Position

◆ SCB_DCCISW_SET_Msk [1/2]

#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)

SCB DCCISW: Set Mask

◆ SCB_DCCISW_SET_Msk [2/2]

#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)

SCB DCCISW: Set Mask

◆ SCB_DCCISW_SET_Pos [1/2]

#define SCB_DCCISW_SET_Pos   5U

SCB DCCISW: Set Position

◆ SCB_DCCISW_SET_Pos [2/2]

#define SCB_DCCISW_SET_Pos   5U

SCB DCCISW: Set Position

◆ SCB_DCCISW_WAY_Msk [1/2]

#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)

SCB DCCISW: Way Mask

◆ SCB_DCCISW_WAY_Msk [2/2]

#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)

SCB DCCISW: Way Mask

◆ SCB_DCCISW_WAY_Pos [1/2]

#define SCB_DCCISW_WAY_Pos   30U

SCB DCCISW: Way Position

◆ SCB_DCCISW_WAY_Pos [2/2]

#define SCB_DCCISW_WAY_Pos   30U

SCB DCCISW: Way Position

◆ SCB_DCCSW_SET_Msk [1/2]

#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)

SCB DCCSW: Set Mask

◆ SCB_DCCSW_SET_Msk [2/2]

#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)

SCB DCCSW: Set Mask

◆ SCB_DCCSW_SET_Pos [1/2]

#define SCB_DCCSW_SET_Pos   5U

SCB DCCSW: Set Position

◆ SCB_DCCSW_SET_Pos [2/2]

#define SCB_DCCSW_SET_Pos   5U

SCB DCCSW: Set Position

◆ SCB_DCCSW_WAY_Msk [1/2]

#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)

SCB DCCSW: Way Mask

◆ SCB_DCCSW_WAY_Msk [2/2]

#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)

SCB DCCSW: Way Mask

◆ SCB_DCCSW_WAY_Pos [1/2]

#define SCB_DCCSW_WAY_Pos   30U

SCB DCCSW: Way Position

◆ SCB_DCCSW_WAY_Pos [2/2]

#define SCB_DCCSW_WAY_Pos   30U

SCB DCCSW: Way Position

◆ SCB_DCISW_SET_Msk [1/2]

#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)

SCB DCISW: Set Mask

◆ SCB_DCISW_SET_Msk [2/2]

#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)

SCB DCISW: Set Mask

◆ SCB_DCISW_SET_Pos [1/2]

#define SCB_DCISW_SET_Pos   5U

SCB DCISW: Set Position

◆ SCB_DCISW_SET_Pos [2/2]

#define SCB_DCISW_SET_Pos   5U

SCB DCISW: Set Position

◆ SCB_DCISW_WAY_Msk [1/2]

#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)

SCB DCISW: Way Mask

◆ SCB_DCISW_WAY_Msk [2/2]

#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)

SCB DCISW: Way Mask

◆ SCB_DCISW_WAY_Pos [1/2]

#define SCB_DCISW_WAY_Pos   30U

SCB DCISW: Way Position

◆ SCB_DCISW_WAY_Pos [2/2]

#define SCB_DCISW_WAY_Pos   30U

SCB DCISW: Way Position

◆ SCB_DFSR_BKPT_Msk [1/6]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

◆ SCB_DFSR_BKPT_Msk [2/6]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

◆ SCB_DFSR_BKPT_Msk [3/6]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

◆ SCB_DFSR_BKPT_Msk [4/6]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

◆ SCB_DFSR_BKPT_Msk [5/6]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

◆ SCB_DFSR_BKPT_Msk [6/6]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

◆ SCB_DFSR_BKPT_Pos [1/6]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

◆ SCB_DFSR_BKPT_Pos [2/6]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

◆ SCB_DFSR_BKPT_Pos [3/6]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

◆ SCB_DFSR_BKPT_Pos [4/6]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

◆ SCB_DFSR_BKPT_Pos [5/6]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

◆ SCB_DFSR_BKPT_Pos [6/6]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

◆ SCB_DFSR_DWTTRAP_Msk [1/6]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

◆ SCB_DFSR_DWTTRAP_Msk [2/6]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

◆ SCB_DFSR_DWTTRAP_Msk [3/6]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

◆ SCB_DFSR_DWTTRAP_Msk [4/6]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

◆ SCB_DFSR_DWTTRAP_Msk [5/6]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

◆ SCB_DFSR_DWTTRAP_Msk [6/6]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

◆ SCB_DFSR_DWTTRAP_Pos [1/6]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

◆ SCB_DFSR_DWTTRAP_Pos [2/6]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

◆ SCB_DFSR_DWTTRAP_Pos [3/6]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

◆ SCB_DFSR_DWTTRAP_Pos [4/6]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

◆ SCB_DFSR_DWTTRAP_Pos [5/6]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

◆ SCB_DFSR_DWTTRAP_Pos [6/6]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

◆ SCB_DFSR_EXTERNAL_Msk [1/6]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

◆ SCB_DFSR_EXTERNAL_Msk [2/6]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

◆ SCB_DFSR_EXTERNAL_Msk [3/6]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

◆ SCB_DFSR_EXTERNAL_Msk [4/6]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

◆ SCB_DFSR_EXTERNAL_Msk [5/6]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

◆ SCB_DFSR_EXTERNAL_Msk [6/6]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

◆ SCB_DFSR_EXTERNAL_Pos [1/6]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

◆ SCB_DFSR_EXTERNAL_Pos [2/6]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

◆ SCB_DFSR_EXTERNAL_Pos [3/6]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

◆ SCB_DFSR_EXTERNAL_Pos [4/6]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

◆ SCB_DFSR_EXTERNAL_Pos [5/6]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

◆ SCB_DFSR_EXTERNAL_Pos [6/6]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

◆ SCB_DFSR_HALTED_Msk [1/6]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

◆ SCB_DFSR_HALTED_Msk [2/6]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

◆ SCB_DFSR_HALTED_Msk [3/6]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

◆ SCB_DFSR_HALTED_Msk [4/6]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

◆ SCB_DFSR_HALTED_Msk [5/6]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

◆ SCB_DFSR_HALTED_Msk [6/6]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

◆ SCB_DFSR_HALTED_Pos [1/6]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

◆ SCB_DFSR_HALTED_Pos [2/6]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

◆ SCB_DFSR_HALTED_Pos [3/6]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

◆ SCB_DFSR_HALTED_Pos [4/6]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

◆ SCB_DFSR_HALTED_Pos [5/6]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

◆ SCB_DFSR_HALTED_Pos [6/6]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

◆ SCB_DFSR_VCATCH_Msk [1/6]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

◆ SCB_DFSR_VCATCH_Msk [2/6]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

◆ SCB_DFSR_VCATCH_Msk [3/6]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

◆ SCB_DFSR_VCATCH_Msk [4/6]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

◆ SCB_DFSR_VCATCH_Msk [5/6]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

◆ SCB_DFSR_VCATCH_Msk [6/6]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

◆ SCB_DFSR_VCATCH_Pos [1/6]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

◆ SCB_DFSR_VCATCH_Pos [2/6]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

◆ SCB_DFSR_VCATCH_Pos [3/6]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

◆ SCB_DFSR_VCATCH_Pos [4/6]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

◆ SCB_DFSR_VCATCH_Pos [5/6]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

◆ SCB_DFSR_VCATCH_Pos [6/6]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

◆ SCB_DTCMCR_EN_Msk [1/2]

#define SCB_DTCMCR_EN_Msk   (1UL /*<< SCB_DTCMCR_EN_Pos*/)

SCB DTCMCR: EN Mask

◆ SCB_DTCMCR_EN_Msk [2/2]

#define SCB_DTCMCR_EN_Msk   (1UL /*<< SCB_DTCMCR_EN_Pos*/)

SCB DTCMCR: EN Mask

◆ SCB_DTCMCR_EN_Pos [1/2]

#define SCB_DTCMCR_EN_Pos   0U

SCB DTCMCR: EN Position

◆ SCB_DTCMCR_EN_Pos [2/2]

#define SCB_DTCMCR_EN_Pos   0U

SCB DTCMCR: EN Position

◆ SCB_DTCMCR_RETEN_Msk [1/2]

#define SCB_DTCMCR_RETEN_Msk   (1UL << SCB_DTCMCR_RETEN_Pos)

SCB DTCMCR: RETEN Mask

◆ SCB_DTCMCR_RETEN_Msk [2/2]

#define SCB_DTCMCR_RETEN_Msk   (1UL << SCB_DTCMCR_RETEN_Pos)

SCB DTCMCR: RETEN Mask

◆ SCB_DTCMCR_RETEN_Pos [1/2]

#define SCB_DTCMCR_RETEN_Pos   2U

SCB DTCMCR: RETEN Position

◆ SCB_DTCMCR_RETEN_Pos [2/2]

#define SCB_DTCMCR_RETEN_Pos   2U

SCB DTCMCR: RETEN Position

◆ SCB_DTCMCR_RMW_Msk [1/2]

#define SCB_DTCMCR_RMW_Msk   (1UL << SCB_DTCMCR_RMW_Pos)

SCB DTCMCR: RMW Mask

◆ SCB_DTCMCR_RMW_Msk [2/2]

#define SCB_DTCMCR_RMW_Msk   (1UL << SCB_DTCMCR_RMW_Pos)

SCB DTCMCR: RMW Mask

◆ SCB_DTCMCR_RMW_Pos [1/2]

#define SCB_DTCMCR_RMW_Pos   1U

SCB DTCMCR: RMW Position

◆ SCB_DTCMCR_RMW_Pos [2/2]

#define SCB_DTCMCR_RMW_Pos   1U

SCB DTCMCR: RMW Position

◆ SCB_DTCMCR_SZ_Msk [1/2]

#define SCB_DTCMCR_SZ_Msk   (0xFUL << SCB_DTCMCR_SZ_Pos)

SCB DTCMCR: SZ Mask

◆ SCB_DTCMCR_SZ_Msk [2/2]

#define SCB_DTCMCR_SZ_Msk   (0xFUL << SCB_DTCMCR_SZ_Pos)

SCB DTCMCR: SZ Mask

◆ SCB_DTCMCR_SZ_Pos [1/2]

#define SCB_DTCMCR_SZ_Pos   3U

SCB DTCMCR: SZ Position

◆ SCB_DTCMCR_SZ_Pos [2/2]

#define SCB_DTCMCR_SZ_Pos   3U

SCB DTCMCR: SZ Position

◆ SCB_HFSR_DEBUGEVT_Msk [1/6]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

◆ SCB_HFSR_DEBUGEVT_Msk [2/6]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

◆ SCB_HFSR_DEBUGEVT_Msk [3/6]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

◆ SCB_HFSR_DEBUGEVT_Msk [4/6]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

◆ SCB_HFSR_DEBUGEVT_Msk [5/6]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

◆ SCB_HFSR_DEBUGEVT_Msk [6/6]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

◆ SCB_HFSR_DEBUGEVT_Pos [1/6]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

◆ SCB_HFSR_DEBUGEVT_Pos [2/6]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

◆ SCB_HFSR_DEBUGEVT_Pos [3/6]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

◆ SCB_HFSR_DEBUGEVT_Pos [4/6]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

◆ SCB_HFSR_DEBUGEVT_Pos [5/6]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

◆ SCB_HFSR_DEBUGEVT_Pos [6/6]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

◆ SCB_HFSR_FORCED_Msk [1/6]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

◆ SCB_HFSR_FORCED_Msk [2/6]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

◆ SCB_HFSR_FORCED_Msk [3/6]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

◆ SCB_HFSR_FORCED_Msk [4/6]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

◆ SCB_HFSR_FORCED_Msk [5/6]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

◆ SCB_HFSR_FORCED_Msk [6/6]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

◆ SCB_HFSR_FORCED_Pos [1/6]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

◆ SCB_HFSR_FORCED_Pos [2/6]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

◆ SCB_HFSR_FORCED_Pos [3/6]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

◆ SCB_HFSR_FORCED_Pos [4/6]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

◆ SCB_HFSR_FORCED_Pos [5/6]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

◆ SCB_HFSR_FORCED_Pos [6/6]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

◆ SCB_HFSR_VECTTBL_Msk [1/6]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

◆ SCB_HFSR_VECTTBL_Msk [2/6]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

◆ SCB_HFSR_VECTTBL_Msk [3/6]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

◆ SCB_HFSR_VECTTBL_Msk [4/6]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

◆ SCB_HFSR_VECTTBL_Msk [5/6]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

◆ SCB_HFSR_VECTTBL_Msk [6/6]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

◆ SCB_HFSR_VECTTBL_Pos [1/6]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

◆ SCB_HFSR_VECTTBL_Pos [2/6]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

◆ SCB_HFSR_VECTTBL_Pos [3/6]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

◆ SCB_HFSR_VECTTBL_Pos [4/6]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

◆ SCB_HFSR_VECTTBL_Pos [5/6]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

◆ SCB_HFSR_VECTTBL_Pos [6/6]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

◆ SCB_ICSR_ISRPENDING_Msk [1/12]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

◆ SCB_ICSR_ISRPENDING_Msk [2/12]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

◆ SCB_ICSR_ISRPENDING_Msk [3/12]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

◆ SCB_ICSR_ISRPENDING_Msk [4/12]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

◆ SCB_ICSR_ISRPENDING_Msk [5/12]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

◆ SCB_ICSR_ISRPENDING_Msk [6/12]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

◆ SCB_ICSR_ISRPENDING_Msk [7/12]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

◆ SCB_ICSR_ISRPENDING_Msk [8/12]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

◆ SCB_ICSR_ISRPENDING_Msk [9/12]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

◆ SCB_ICSR_ISRPENDING_Msk [10/12]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

◆ SCB_ICSR_ISRPENDING_Msk [11/12]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

◆ SCB_ICSR_ISRPENDING_Msk [12/12]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

◆ SCB_ICSR_ISRPENDING_Pos [1/12]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

◆ SCB_ICSR_ISRPENDING_Pos [2/12]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

◆ SCB_ICSR_ISRPENDING_Pos [3/12]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

◆ SCB_ICSR_ISRPENDING_Pos [4/12]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

◆ SCB_ICSR_ISRPENDING_Pos [5/12]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

◆ SCB_ICSR_ISRPENDING_Pos [6/12]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

◆ SCB_ICSR_ISRPENDING_Pos [7/12]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

◆ SCB_ICSR_ISRPENDING_Pos [8/12]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

◆ SCB_ICSR_ISRPENDING_Pos [9/12]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

◆ SCB_ICSR_ISRPENDING_Pos [10/12]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

◆ SCB_ICSR_ISRPENDING_Pos [11/12]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

◆ SCB_ICSR_ISRPENDING_Pos [12/12]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

◆ SCB_ICSR_ISRPREEMPT_Msk [1/12]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

◆ SCB_ICSR_ISRPREEMPT_Msk [2/12]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

◆ SCB_ICSR_ISRPREEMPT_Msk [3/12]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

◆ SCB_ICSR_ISRPREEMPT_Msk [4/12]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

◆ SCB_ICSR_ISRPREEMPT_Msk [5/12]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

◆ SCB_ICSR_ISRPREEMPT_Msk [6/12]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

◆ SCB_ICSR_ISRPREEMPT_Msk [7/12]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

◆ SCB_ICSR_ISRPREEMPT_Msk [8/12]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

◆ SCB_ICSR_ISRPREEMPT_Msk [9/12]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

◆ SCB_ICSR_ISRPREEMPT_Msk [10/12]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

◆ SCB_ICSR_ISRPREEMPT_Msk [11/12]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

◆ SCB_ICSR_ISRPREEMPT_Msk [12/12]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

◆ SCB_ICSR_ISRPREEMPT_Pos [1/12]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

◆ SCB_ICSR_ISRPREEMPT_Pos [2/12]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

◆ SCB_ICSR_ISRPREEMPT_Pos [3/12]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

◆ SCB_ICSR_ISRPREEMPT_Pos [4/12]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

◆ SCB_ICSR_ISRPREEMPT_Pos [5/12]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

◆ SCB_ICSR_ISRPREEMPT_Pos [6/12]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

◆ SCB_ICSR_ISRPREEMPT_Pos [7/12]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

◆ SCB_ICSR_ISRPREEMPT_Pos [8/12]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

◆ SCB_ICSR_ISRPREEMPT_Pos [9/12]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

◆ SCB_ICSR_ISRPREEMPT_Pos [10/12]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

◆ SCB_ICSR_ISRPREEMPT_Pos [11/12]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

◆ SCB_ICSR_ISRPREEMPT_Pos [12/12]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

◆ SCB_ICSR_NMIPENDSET_Msk [1/12]

#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk

SCB ICSR: NMIPENDSET Mask, backward compatibility

SCB ICSR: NMIPENDSET Mask

◆ SCB_ICSR_NMIPENDSET_Msk [2/12]

#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk

SCB ICSR: NMIPENDSET Mask, backward compatibility

SCB ICSR: NMIPENDSET Mask

◆ SCB_ICSR_NMIPENDSET_Msk [3/12]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

SCB ICSR: NMIPENDSET Mask, backward compatibility

◆ SCB_ICSR_NMIPENDSET_Msk [4/12]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

SCB ICSR: NMIPENDSET Mask, backward compatibility

◆ SCB_ICSR_NMIPENDSET_Msk [5/12]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

SCB ICSR: NMIPENDSET Mask, backward compatibility

◆ SCB_ICSR_NMIPENDSET_Msk [6/12]

#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk

SCB ICSR: NMIPENDSET Mask, backward compatibility

SCB ICSR: NMIPENDSET Mask

◆ SCB_ICSR_NMIPENDSET_Msk [7/12]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

SCB ICSR: NMIPENDSET Mask, backward compatibility

◆ SCB_ICSR_NMIPENDSET_Msk [8/12]

#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk

SCB ICSR: NMIPENDSET Mask, backward compatibility

SCB ICSR: NMIPENDSET Mask

◆ SCB_ICSR_NMIPENDSET_Msk [9/12]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

◆ SCB_ICSR_NMIPENDSET_Msk [10/12]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

◆ SCB_ICSR_NMIPENDSET_Msk [11/12]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

◆ SCB_ICSR_NMIPENDSET_Msk [12/12]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

◆ SCB_ICSR_NMIPENDSET_Pos [1/12]

#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos

SCB ICSR: NMIPENDSET Position, backward compatibility

SCB ICSR: NMIPENDSET Position

◆ SCB_ICSR_NMIPENDSET_Pos [2/12]

#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos

SCB ICSR: NMIPENDSET Position, backward compatibility

SCB ICSR: NMIPENDSET Position

◆ SCB_ICSR_NMIPENDSET_Pos [3/12]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

SCB ICSR: NMIPENDSET Position, backward compatibility

◆ SCB_ICSR_NMIPENDSET_Pos [4/12]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

SCB ICSR: NMIPENDSET Position, backward compatibility

◆ SCB_ICSR_NMIPENDSET_Pos [5/12]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

SCB ICSR: NMIPENDSET Position, backward compatibility

◆ SCB_ICSR_NMIPENDSET_Pos [6/12]

#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos

SCB ICSR: NMIPENDSET Position, backward compatibility

SCB ICSR: NMIPENDSET Position

◆ SCB_ICSR_NMIPENDSET_Pos [7/12]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

SCB ICSR: NMIPENDSET Position, backward compatibility

◆ SCB_ICSR_NMIPENDSET_Pos [8/12]

#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos

SCB ICSR: NMIPENDSET Position, backward compatibility

SCB ICSR: NMIPENDSET Position

◆ SCB_ICSR_NMIPENDSET_Pos [9/12]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

◆ SCB_ICSR_NMIPENDSET_Pos [10/12]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

◆ SCB_ICSR_NMIPENDSET_Pos [11/12]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

◆ SCB_ICSR_NMIPENDSET_Pos [12/12]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

◆ SCB_ICSR_PENDNMICLR_Msk

#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)

SCB ICSR: PENDNMICLR Mask

◆ SCB_ICSR_PENDNMICLR_Pos

#define SCB_ICSR_PENDNMICLR_Pos   30U

SCB ICSR: PENDNMICLR Position

◆ SCB_ICSR_PENDNMISET_Msk

#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)

SCB ICSR: PENDNMISET Mask

◆ SCB_ICSR_PENDNMISET_Pos

#define SCB_ICSR_PENDNMISET_Pos   31U

SCB ICSR: PENDNMISET Position

◆ SCB_ICSR_PENDSTCLR_Msk [1/12]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

◆ SCB_ICSR_PENDSTCLR_Msk [2/12]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

◆ SCB_ICSR_PENDSTCLR_Msk [3/12]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

◆ SCB_ICSR_PENDSTCLR_Msk [4/12]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

◆ SCB_ICSR_PENDSTCLR_Msk [5/12]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

◆ SCB_ICSR_PENDSTCLR_Msk [6/12]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

◆ SCB_ICSR_PENDSTCLR_Msk [7/12]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

◆ SCB_ICSR_PENDSTCLR_Msk [8/12]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

◆ SCB_ICSR_PENDSTCLR_Msk [9/12]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

◆ SCB_ICSR_PENDSTCLR_Msk [10/12]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

◆ SCB_ICSR_PENDSTCLR_Msk [11/12]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

◆ SCB_ICSR_PENDSTCLR_Msk [12/12]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

◆ SCB_ICSR_PENDSTCLR_Pos [1/12]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

◆ SCB_ICSR_PENDSTCLR_Pos [2/12]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

◆ SCB_ICSR_PENDSTCLR_Pos [3/12]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

◆ SCB_ICSR_PENDSTCLR_Pos [4/12]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

◆ SCB_ICSR_PENDSTCLR_Pos [5/12]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

◆ SCB_ICSR_PENDSTCLR_Pos [6/12]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

◆ SCB_ICSR_PENDSTCLR_Pos [7/12]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

◆ SCB_ICSR_PENDSTCLR_Pos [8/12]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

◆ SCB_ICSR_PENDSTCLR_Pos [9/12]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

◆ SCB_ICSR_PENDSTCLR_Pos [10/12]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

◆ SCB_ICSR_PENDSTCLR_Pos [11/12]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

◆ SCB_ICSR_PENDSTCLR_Pos [12/12]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

◆ SCB_ICSR_PENDSTSET_Msk [1/12]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

◆ SCB_ICSR_PENDSTSET_Msk [2/12]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

◆ SCB_ICSR_PENDSTSET_Msk [3/12]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

◆ SCB_ICSR_PENDSTSET_Msk [4/12]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

◆ SCB_ICSR_PENDSTSET_Msk [5/12]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

◆ SCB_ICSR_PENDSTSET_Msk [6/12]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

◆ SCB_ICSR_PENDSTSET_Msk [7/12]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

◆ SCB_ICSR_PENDSTSET_Msk [8/12]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

◆ SCB_ICSR_PENDSTSET_Msk [9/12]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

◆ SCB_ICSR_PENDSTSET_Msk [10/12]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

◆ SCB_ICSR_PENDSTSET_Msk [11/12]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

◆ SCB_ICSR_PENDSTSET_Msk [12/12]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

◆ SCB_ICSR_PENDSTSET_Pos [1/12]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

◆ SCB_ICSR_PENDSTSET_Pos [2/12]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

◆ SCB_ICSR_PENDSTSET_Pos [3/12]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

◆ SCB_ICSR_PENDSTSET_Pos [4/12]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

◆ SCB_ICSR_PENDSTSET_Pos [5/12]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

◆ SCB_ICSR_PENDSTSET_Pos [6/12]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

◆ SCB_ICSR_PENDSTSET_Pos [7/12]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

◆ SCB_ICSR_PENDSTSET_Pos [8/12]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

◆ SCB_ICSR_PENDSTSET_Pos [9/12]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

◆ SCB_ICSR_PENDSTSET_Pos [10/12]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

◆ SCB_ICSR_PENDSTSET_Pos [11/12]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

◆ SCB_ICSR_PENDSTSET_Pos [12/12]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

◆ SCB_ICSR_PENDSVCLR_Msk [1/12]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

◆ SCB_ICSR_PENDSVCLR_Msk [2/12]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

◆ SCB_ICSR_PENDSVCLR_Msk [3/12]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

◆ SCB_ICSR_PENDSVCLR_Msk [4/12]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

◆ SCB_ICSR_PENDSVCLR_Msk [5/12]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

◆ SCB_ICSR_PENDSVCLR_Msk [6/12]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

◆ SCB_ICSR_PENDSVCLR_Msk [7/12]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

◆ SCB_ICSR_PENDSVCLR_Msk [8/12]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

◆ SCB_ICSR_PENDSVCLR_Msk [9/12]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

◆ SCB_ICSR_PENDSVCLR_Msk [10/12]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

◆ SCB_ICSR_PENDSVCLR_Msk [11/12]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

◆ SCB_ICSR_PENDSVCLR_Msk [12/12]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

◆ SCB_ICSR_PENDSVCLR_Pos [1/12]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

◆ SCB_ICSR_PENDSVCLR_Pos [2/12]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

◆ SCB_ICSR_PENDSVCLR_Pos [3/12]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

◆ SCB_ICSR_PENDSVCLR_Pos [4/12]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

◆ SCB_ICSR_PENDSVCLR_Pos [5/12]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

◆ SCB_ICSR_PENDSVCLR_Pos [6/12]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

◆ SCB_ICSR_PENDSVCLR_Pos [7/12]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

◆ SCB_ICSR_PENDSVCLR_Pos [8/12]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

◆ SCB_ICSR_PENDSVCLR_Pos [9/12]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

◆ SCB_ICSR_PENDSVCLR_Pos [10/12]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

◆ SCB_ICSR_PENDSVCLR_Pos [11/12]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

◆ SCB_ICSR_PENDSVCLR_Pos [12/12]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

◆ SCB_ICSR_PENDSVSET_Msk [1/12]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

◆ SCB_ICSR_PENDSVSET_Msk [2/12]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

◆ SCB_ICSR_PENDSVSET_Msk [3/12]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

◆ SCB_ICSR_PENDSVSET_Msk [4/12]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

◆ SCB_ICSR_PENDSVSET_Msk [5/12]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

◆ SCB_ICSR_PENDSVSET_Msk [6/12]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

◆ SCB_ICSR_PENDSVSET_Msk [7/12]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

◆ SCB_ICSR_PENDSVSET_Msk [8/12]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

◆ SCB_ICSR_PENDSVSET_Msk [9/12]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

◆ SCB_ICSR_PENDSVSET_Msk [10/12]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

◆ SCB_ICSR_PENDSVSET_Msk [11/12]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

◆ SCB_ICSR_PENDSVSET_Msk [12/12]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

◆ SCB_ICSR_PENDSVSET_Pos [1/12]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

◆ SCB_ICSR_PENDSVSET_Pos [2/12]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

◆ SCB_ICSR_PENDSVSET_Pos [3/12]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

◆ SCB_ICSR_PENDSVSET_Pos [4/12]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

◆ SCB_ICSR_PENDSVSET_Pos [5/12]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

◆ SCB_ICSR_PENDSVSET_Pos [6/12]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

◆ SCB_ICSR_PENDSVSET_Pos [7/12]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

◆ SCB_ICSR_PENDSVSET_Pos [8/12]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

◆ SCB_ICSR_PENDSVSET_Pos [9/12]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

◆ SCB_ICSR_PENDSVSET_Pos [10/12]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

◆ SCB_ICSR_PENDSVSET_Pos [11/12]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

◆ SCB_ICSR_PENDSVSET_Pos [12/12]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

◆ SCB_ICSR_RETTOBASE_Msk [1/8]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

◆ SCB_ICSR_RETTOBASE_Msk [2/8]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

◆ SCB_ICSR_RETTOBASE_Msk [3/8]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

◆ SCB_ICSR_RETTOBASE_Msk [4/8]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

◆ SCB_ICSR_RETTOBASE_Msk [5/8]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

◆ SCB_ICSR_RETTOBASE_Msk [6/8]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

◆ SCB_ICSR_RETTOBASE_Msk [7/8]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

◆ SCB_ICSR_RETTOBASE_Msk [8/8]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

◆ SCB_ICSR_RETTOBASE_Pos [1/8]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

◆ SCB_ICSR_RETTOBASE_Pos [2/8]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

◆ SCB_ICSR_RETTOBASE_Pos [3/8]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

◆ SCB_ICSR_RETTOBASE_Pos [4/8]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

◆ SCB_ICSR_RETTOBASE_Pos [5/8]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

◆ SCB_ICSR_RETTOBASE_Pos [6/8]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

◆ SCB_ICSR_RETTOBASE_Pos [7/8]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

◆ SCB_ICSR_RETTOBASE_Pos [8/8]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

◆ SCB_ICSR_STTNS_Msk

#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)

SCB ICSR: STTNS Mask (Security Extension)

◆ SCB_ICSR_STTNS_Pos

#define SCB_ICSR_STTNS_Pos   24U

SCB ICSR: STTNS Position (Security Extension)

◆ SCB_ICSR_VECTACTIVE_Msk [1/12]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

◆ SCB_ICSR_VECTACTIVE_Msk [2/12]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

◆ SCB_ICSR_VECTACTIVE_Msk [3/12]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

◆ SCB_ICSR_VECTACTIVE_Msk [4/12]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

◆ SCB_ICSR_VECTACTIVE_Msk [5/12]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

◆ SCB_ICSR_VECTACTIVE_Msk [6/12]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

◆ SCB_ICSR_VECTACTIVE_Msk [7/12]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

◆ SCB_ICSR_VECTACTIVE_Msk [8/12]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

◆ SCB_ICSR_VECTACTIVE_Msk [9/12]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

◆ SCB_ICSR_VECTACTIVE_Msk [10/12]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

◆ SCB_ICSR_VECTACTIVE_Msk [11/12]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

◆ SCB_ICSR_VECTACTIVE_Msk [12/12]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

◆ SCB_ICSR_VECTACTIVE_Pos [1/12]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

◆ SCB_ICSR_VECTACTIVE_Pos [2/12]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

◆ SCB_ICSR_VECTACTIVE_Pos [3/12]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

◆ SCB_ICSR_VECTACTIVE_Pos [4/12]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

◆ SCB_ICSR_VECTACTIVE_Pos [5/12]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

◆ SCB_ICSR_VECTACTIVE_Pos [6/12]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

◆ SCB_ICSR_VECTACTIVE_Pos [7/12]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

◆ SCB_ICSR_VECTACTIVE_Pos [8/12]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

◆ SCB_ICSR_VECTACTIVE_Pos [9/12]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

◆ SCB_ICSR_VECTACTIVE_Pos [10/12]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

◆ SCB_ICSR_VECTACTIVE_Pos [11/12]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

◆ SCB_ICSR_VECTACTIVE_Pos [12/12]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

◆ SCB_ICSR_VECTPENDING_Msk [1/12]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

◆ SCB_ICSR_VECTPENDING_Msk [2/12]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

◆ SCB_ICSR_VECTPENDING_Msk [3/12]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

◆ SCB_ICSR_VECTPENDING_Msk [4/12]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

◆ SCB_ICSR_VECTPENDING_Msk [5/12]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

◆ SCB_ICSR_VECTPENDING_Msk [6/12]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

◆ SCB_ICSR_VECTPENDING_Msk [7/12]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

◆ SCB_ICSR_VECTPENDING_Msk [8/12]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

◆ SCB_ICSR_VECTPENDING_Msk [9/12]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

◆ SCB_ICSR_VECTPENDING_Msk [10/12]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

◆ SCB_ICSR_VECTPENDING_Msk [11/12]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

◆ SCB_ICSR_VECTPENDING_Msk [12/12]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

◆ SCB_ICSR_VECTPENDING_Pos [1/12]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

◆ SCB_ICSR_VECTPENDING_Pos [2/12]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

◆ SCB_ICSR_VECTPENDING_Pos [3/12]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

◆ SCB_ICSR_VECTPENDING_Pos [4/12]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

◆ SCB_ICSR_VECTPENDING_Pos [5/12]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

◆ SCB_ICSR_VECTPENDING_Pos [6/12]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

◆ SCB_ICSR_VECTPENDING_Pos [7/12]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

◆ SCB_ICSR_VECTPENDING_Pos [8/12]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

◆ SCB_ICSR_VECTPENDING_Pos [9/12]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

◆ SCB_ICSR_VECTPENDING_Pos [10/12]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

◆ SCB_ICSR_VECTPENDING_Pos [11/12]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

◆ SCB_ICSR_VECTPENDING_Pos [12/12]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

◆ SCB_ITCMCR_EN_Msk [1/2]

#define SCB_ITCMCR_EN_Msk   (1UL /*<< SCB_ITCMCR_EN_Pos*/)

SCB ITCMCR: EN Mask

◆ SCB_ITCMCR_EN_Msk [2/2]

#define SCB_ITCMCR_EN_Msk   (1UL /*<< SCB_ITCMCR_EN_Pos*/)

SCB ITCMCR: EN Mask

◆ SCB_ITCMCR_EN_Pos [1/2]

#define SCB_ITCMCR_EN_Pos   0U

SCB ITCMCR: EN Position

◆ SCB_ITCMCR_EN_Pos [2/2]

#define SCB_ITCMCR_EN_Pos   0U

SCB ITCMCR: EN Position

◆ SCB_ITCMCR_RETEN_Msk [1/2]

#define SCB_ITCMCR_RETEN_Msk   (1UL << SCB_ITCMCR_RETEN_Pos)

SCB ITCMCR: RETEN Mask

◆ SCB_ITCMCR_RETEN_Msk [2/2]

#define SCB_ITCMCR_RETEN_Msk   (1UL << SCB_ITCMCR_RETEN_Pos)

SCB ITCMCR: RETEN Mask

◆ SCB_ITCMCR_RETEN_Pos [1/2]

#define SCB_ITCMCR_RETEN_Pos   2U

SCB ITCMCR: RETEN Position

◆ SCB_ITCMCR_RETEN_Pos [2/2]

#define SCB_ITCMCR_RETEN_Pos   2U

SCB ITCMCR: RETEN Position

◆ SCB_ITCMCR_RMW_Msk [1/2]

#define SCB_ITCMCR_RMW_Msk   (1UL << SCB_ITCMCR_RMW_Pos)

SCB ITCMCR: RMW Mask

◆ SCB_ITCMCR_RMW_Msk [2/2]

#define SCB_ITCMCR_RMW_Msk   (1UL << SCB_ITCMCR_RMW_Pos)

SCB ITCMCR: RMW Mask

◆ SCB_ITCMCR_RMW_Pos [1/2]

#define SCB_ITCMCR_RMW_Pos   1U

SCB ITCMCR: RMW Position

◆ SCB_ITCMCR_RMW_Pos [2/2]

#define SCB_ITCMCR_RMW_Pos   1U

SCB ITCMCR: RMW Position

◆ SCB_ITCMCR_SZ_Msk [1/2]

#define SCB_ITCMCR_SZ_Msk   (0xFUL << SCB_ITCMCR_SZ_Pos)

SCB ITCMCR: SZ Mask

◆ SCB_ITCMCR_SZ_Msk [2/2]

#define SCB_ITCMCR_SZ_Msk   (0xFUL << SCB_ITCMCR_SZ_Pos)

SCB ITCMCR: SZ Mask

◆ SCB_ITCMCR_SZ_Pos [1/2]

#define SCB_ITCMCR_SZ_Pos   3U

SCB ITCMCR: SZ Position

◆ SCB_ITCMCR_SZ_Pos [2/2]

#define SCB_ITCMCR_SZ_Pos   3U

SCB ITCMCR: SZ Position

◆ SCB_NSACR_CP10_Msk

#define SCB_NSACR_CP10_Msk   (1UL << SCB_NSACR_CP10_Pos)

SCB NSACR: CP10 Mask

◆ SCB_NSACR_CP10_Pos

#define SCB_NSACR_CP10_Pos   10U

SCB NSACR: CP10 Position

◆ SCB_NSACR_CP11_Msk

#define SCB_NSACR_CP11_Msk   (1UL << SCB_NSACR_CP11_Pos)

SCB NSACR: CP11 Mask

◆ SCB_NSACR_CP11_Pos

#define SCB_NSACR_CP11_Pos   11U

SCB NSACR: CP11 Position

◆ SCB_NSACR_CPn_Msk

#define SCB_NSACR_CPn_Msk   (1UL /*<< SCB_NSACR_CPn_Pos*/)

SCB NSACR: CPn Mask

◆ SCB_NSACR_CPn_Pos

#define SCB_NSACR_CPn_Pos   0U

SCB NSACR: CPn Position

◆ SCB_SCR_SEVONPEND_Msk [1/12]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

◆ SCB_SCR_SEVONPEND_Msk [2/12]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

◆ SCB_SCR_SEVONPEND_Msk [3/12]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

◆ SCB_SCR_SEVONPEND_Msk [4/12]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

◆ SCB_SCR_SEVONPEND_Msk [5/12]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

◆ SCB_SCR_SEVONPEND_Msk [6/12]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

◆ SCB_SCR_SEVONPEND_Msk [7/12]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

◆ SCB_SCR_SEVONPEND_Msk [8/12]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

◆ SCB_SCR_SEVONPEND_Msk [9/12]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

◆ SCB_SCR_SEVONPEND_Msk [10/12]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

◆ SCB_SCR_SEVONPEND_Msk [11/12]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

◆ SCB_SCR_SEVONPEND_Msk [12/12]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

◆ SCB_SCR_SEVONPEND_Pos [1/12]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

◆ SCB_SCR_SEVONPEND_Pos [2/12]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

◆ SCB_SCR_SEVONPEND_Pos [3/12]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

◆ SCB_SCR_SEVONPEND_Pos [4/12]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

◆ SCB_SCR_SEVONPEND_Pos [5/12]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

◆ SCB_SCR_SEVONPEND_Pos [6/12]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

◆ SCB_SCR_SEVONPEND_Pos [7/12]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

◆ SCB_SCR_SEVONPEND_Pos [8/12]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

◆ SCB_SCR_SEVONPEND_Pos [9/12]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

◆ SCB_SCR_SEVONPEND_Pos [10/12]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

◆ SCB_SCR_SEVONPEND_Pos [11/12]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

◆ SCB_SCR_SEVONPEND_Pos [12/12]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

◆ SCB_SCR_SLEEPDEEP_Msk [1/12]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

◆ SCB_SCR_SLEEPDEEP_Msk [2/12]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

◆ SCB_SCR_SLEEPDEEP_Msk [3/12]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

◆ SCB_SCR_SLEEPDEEP_Msk [4/12]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

◆ SCB_SCR_SLEEPDEEP_Msk [5/12]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

◆ SCB_SCR_SLEEPDEEP_Msk [6/12]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

◆ SCB_SCR_SLEEPDEEP_Msk [7/12]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

◆ SCB_SCR_SLEEPDEEP_Msk [8/12]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

◆ SCB_SCR_SLEEPDEEP_Msk [9/12]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

◆ SCB_SCR_SLEEPDEEP_Msk [10/12]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

◆ SCB_SCR_SLEEPDEEP_Msk [11/12]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

◆ SCB_SCR_SLEEPDEEP_Msk [12/12]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

◆ SCB_SCR_SLEEPDEEP_Pos [1/12]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

◆ SCB_SCR_SLEEPDEEP_Pos [2/12]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

◆ SCB_SCR_SLEEPDEEP_Pos [3/12]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

◆ SCB_SCR_SLEEPDEEP_Pos [4/12]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

◆ SCB_SCR_SLEEPDEEP_Pos [5/12]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

◆ SCB_SCR_SLEEPDEEP_Pos [6/12]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

◆ SCB_SCR_SLEEPDEEP_Pos [7/12]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

◆ SCB_SCR_SLEEPDEEP_Pos [8/12]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

◆ SCB_SCR_SLEEPDEEP_Pos [9/12]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

◆ SCB_SCR_SLEEPDEEP_Pos [10/12]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

◆ SCB_SCR_SLEEPDEEP_Pos [11/12]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

◆ SCB_SCR_SLEEPDEEP_Pos [12/12]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

◆ SCB_SCR_SLEEPDEEPS_Msk

#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)

SCB SCR: SLEEPDEEPS Mask

◆ SCB_SCR_SLEEPDEEPS_Pos

#define SCB_SCR_SLEEPDEEPS_Pos   3U

SCB SCR: SLEEPDEEPS Position

◆ SCB_SCR_SLEEPONEXIT_Msk [1/12]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

◆ SCB_SCR_SLEEPONEXIT_Msk [2/12]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

◆ SCB_SCR_SLEEPONEXIT_Msk [3/12]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

◆ SCB_SCR_SLEEPONEXIT_Msk [4/12]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

◆ SCB_SCR_SLEEPONEXIT_Msk [5/12]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

◆ SCB_SCR_SLEEPONEXIT_Msk [6/12]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

◆ SCB_SCR_SLEEPONEXIT_Msk [7/12]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

◆ SCB_SCR_SLEEPONEXIT_Msk [8/12]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

◆ SCB_SCR_SLEEPONEXIT_Msk [9/12]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

◆ SCB_SCR_SLEEPONEXIT_Msk [10/12]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

◆ SCB_SCR_SLEEPONEXIT_Msk [11/12]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

◆ SCB_SCR_SLEEPONEXIT_Msk [12/12]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

◆ SCB_SCR_SLEEPONEXIT_Pos [1/12]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

◆ SCB_SCR_SLEEPONEXIT_Pos [2/12]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

◆ SCB_SCR_SLEEPONEXIT_Pos [3/12]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

◆ SCB_SCR_SLEEPONEXIT_Pos [4/12]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

◆ SCB_SCR_SLEEPONEXIT_Pos [5/12]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

◆ SCB_SCR_SLEEPONEXIT_Pos [6/12]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

◆ SCB_SCR_SLEEPONEXIT_Pos [7/12]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

◆ SCB_SCR_SLEEPONEXIT_Pos [8/12]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

◆ SCB_SCR_SLEEPONEXIT_Pos [9/12]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

◆ SCB_SCR_SLEEPONEXIT_Pos [10/12]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

◆ SCB_SCR_SLEEPONEXIT_Pos [11/12]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

◆ SCB_SCR_SLEEPONEXIT_Pos [12/12]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

◆ SCB_SHCSR_BUSFAULTACT_Msk [1/6]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

◆ SCB_SHCSR_BUSFAULTACT_Msk [2/6]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

◆ SCB_SHCSR_BUSFAULTACT_Msk [3/6]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

◆ SCB_SHCSR_BUSFAULTACT_Msk [4/6]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

◆ SCB_SHCSR_BUSFAULTACT_Msk [5/6]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

◆ SCB_SHCSR_BUSFAULTACT_Msk [6/6]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

◆ SCB_SHCSR_BUSFAULTACT_Pos [1/6]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

◆ SCB_SHCSR_BUSFAULTACT_Pos [2/6]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

◆ SCB_SHCSR_BUSFAULTACT_Pos [3/6]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

◆ SCB_SHCSR_BUSFAULTACT_Pos [4/6]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

◆ SCB_SHCSR_BUSFAULTACT_Pos [5/6]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

◆ SCB_SHCSR_BUSFAULTACT_Pos [6/6]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

◆ SCB_SHCSR_BUSFAULTENA_Msk [1/6]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

◆ SCB_SHCSR_BUSFAULTENA_Msk [2/6]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

◆ SCB_SHCSR_BUSFAULTENA_Msk [3/6]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

◆ SCB_SHCSR_BUSFAULTENA_Msk [4/6]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

◆ SCB_SHCSR_BUSFAULTENA_Msk [5/6]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

◆ SCB_SHCSR_BUSFAULTENA_Msk [6/6]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

◆ SCB_SHCSR_BUSFAULTENA_Pos [1/6]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

◆ SCB_SHCSR_BUSFAULTENA_Pos [2/6]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

◆ SCB_SHCSR_BUSFAULTENA_Pos [3/6]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

◆ SCB_SHCSR_BUSFAULTENA_Pos [4/6]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

◆ SCB_SHCSR_BUSFAULTENA_Pos [5/6]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

◆ SCB_SHCSR_BUSFAULTENA_Pos [6/6]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [1/6]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [2/6]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [3/6]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [4/6]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [5/6]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [6/6]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [1/6]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [2/6]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [3/6]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [4/6]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [5/6]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [6/6]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

◆ SCB_SHCSR_HARDFAULTACT_Msk

#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

SCB SHCSR: HARDFAULTACT Mask

◆ SCB_SHCSR_HARDFAULTACT_Pos

#define SCB_SHCSR_HARDFAULTACT_Pos   2U

SCB SHCSR: HARDFAULTACT Position

◆ SCB_SHCSR_HARDFAULTPENDED_Msk

#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

SCB SHCSR: HARDFAULTPENDED Mask

◆ SCB_SHCSR_HARDFAULTPENDED_Pos

#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U

SCB SHCSR: HARDFAULTPENDED Position

◆ SCB_SHCSR_MEMFAULTACT_Msk [1/6]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

◆ SCB_SHCSR_MEMFAULTACT_Msk [2/6]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

◆ SCB_SHCSR_MEMFAULTACT_Msk [3/6]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

◆ SCB_SHCSR_MEMFAULTACT_Msk [4/6]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

◆ SCB_SHCSR_MEMFAULTACT_Msk [5/6]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

◆ SCB_SHCSR_MEMFAULTACT_Msk [6/6]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

◆ SCB_SHCSR_MEMFAULTACT_Pos [1/6]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

◆ SCB_SHCSR_MEMFAULTACT_Pos [2/6]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

◆ SCB_SHCSR_MEMFAULTACT_Pos [3/6]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

◆ SCB_SHCSR_MEMFAULTACT_Pos [4/6]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

◆ SCB_SHCSR_MEMFAULTACT_Pos [5/6]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

◆ SCB_SHCSR_MEMFAULTACT_Pos [6/6]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

◆ SCB_SHCSR_MEMFAULTENA_Msk [1/6]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

◆ SCB_SHCSR_MEMFAULTENA_Msk [2/6]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

◆ SCB_SHCSR_MEMFAULTENA_Msk [3/6]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

◆ SCB_SHCSR_MEMFAULTENA_Msk [4/6]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

◆ SCB_SHCSR_MEMFAULTENA_Msk [5/6]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

◆ SCB_SHCSR_MEMFAULTENA_Msk [6/6]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

◆ SCB_SHCSR_MEMFAULTENA_Pos [1/6]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

◆ SCB_SHCSR_MEMFAULTENA_Pos [2/6]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

◆ SCB_SHCSR_MEMFAULTENA_Pos [3/6]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

◆ SCB_SHCSR_MEMFAULTENA_Pos [4/6]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

◆ SCB_SHCSR_MEMFAULTENA_Pos [5/6]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

◆ SCB_SHCSR_MEMFAULTENA_Pos [6/6]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [1/6]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [2/6]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [3/6]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [4/6]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [5/6]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [6/6]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [1/6]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [2/6]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [3/6]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [4/6]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [5/6]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [6/6]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

◆ SCB_SHCSR_MONITORACT_Msk [1/6]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

◆ SCB_SHCSR_MONITORACT_Msk [2/6]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

◆ SCB_SHCSR_MONITORACT_Msk [3/6]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

◆ SCB_SHCSR_MONITORACT_Msk [4/6]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

◆ SCB_SHCSR_MONITORACT_Msk [5/6]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

◆ SCB_SHCSR_MONITORACT_Msk [6/6]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

◆ SCB_SHCSR_MONITORACT_Pos [1/6]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

◆ SCB_SHCSR_MONITORACT_Pos [2/6]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

◆ SCB_SHCSR_MONITORACT_Pos [3/6]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

◆ SCB_SHCSR_MONITORACT_Pos [4/6]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

◆ SCB_SHCSR_MONITORACT_Pos [5/6]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

◆ SCB_SHCSR_MONITORACT_Pos [6/6]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

◆ SCB_SHCSR_NMIACT_Msk

#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)

SCB SHCSR: NMIACT Mask

◆ SCB_SHCSR_NMIACT_Pos

#define SCB_SHCSR_NMIACT_Pos   5U

SCB SHCSR: NMIACT Position

◆ SCB_SHCSR_PENDSVACT_Msk [1/8]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

◆ SCB_SHCSR_PENDSVACT_Msk [2/8]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

◆ SCB_SHCSR_PENDSVACT_Msk [3/8]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

◆ SCB_SHCSR_PENDSVACT_Msk [4/8]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

◆ SCB_SHCSR_PENDSVACT_Msk [5/8]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

◆ SCB_SHCSR_PENDSVACT_Msk [6/8]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

◆ SCB_SHCSR_PENDSVACT_Msk [7/8]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

◆ SCB_SHCSR_PENDSVACT_Msk [8/8]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

◆ SCB_SHCSR_PENDSVACT_Pos [1/8]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

◆ SCB_SHCSR_PENDSVACT_Pos [2/8]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

◆ SCB_SHCSR_PENDSVACT_Pos [3/8]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

◆ SCB_SHCSR_PENDSVACT_Pos [4/8]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

◆ SCB_SHCSR_PENDSVACT_Pos [5/8]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

◆ SCB_SHCSR_PENDSVACT_Pos [6/8]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

◆ SCB_SHCSR_PENDSVACT_Pos [7/8]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

◆ SCB_SHCSR_PENDSVACT_Pos [8/8]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

◆ SCB_SHCSR_SECUREFAULTACT_Msk

#define SCB_SHCSR_SECUREFAULTACT_Msk   (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)

SCB SHCSR: SECUREFAULTACT Mask

◆ SCB_SHCSR_SECUREFAULTACT_Pos

#define SCB_SHCSR_SECUREFAULTACT_Pos   4U

SCB SHCSR: SECUREFAULTACT Position

◆ SCB_SHCSR_SECUREFAULTENA_Msk

#define SCB_SHCSR_SECUREFAULTENA_Msk   (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)

SCB SHCSR: SECUREFAULTENA Mask

◆ SCB_SHCSR_SECUREFAULTENA_Pos

#define SCB_SHCSR_SECUREFAULTENA_Pos   19U

SCB SHCSR: SECUREFAULTENA Position

◆ SCB_SHCSR_SECUREFAULTPENDED_Msk

#define SCB_SHCSR_SECUREFAULTPENDED_Msk   (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)

SCB SHCSR: SECUREFAULTPENDED Mask

◆ SCB_SHCSR_SECUREFAULTPENDED_Pos

#define SCB_SHCSR_SECUREFAULTPENDED_Pos   20U

SCB SHCSR: SECUREFAULTPENDED Position

◆ SCB_SHCSR_SVCALLACT_Msk [1/8]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

◆ SCB_SHCSR_SVCALLACT_Msk [2/8]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

◆ SCB_SHCSR_SVCALLACT_Msk [3/8]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

◆ SCB_SHCSR_SVCALLACT_Msk [4/8]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

◆ SCB_SHCSR_SVCALLACT_Msk [5/8]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

◆ SCB_SHCSR_SVCALLACT_Msk [6/8]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

◆ SCB_SHCSR_SVCALLACT_Msk [7/8]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

◆ SCB_SHCSR_SVCALLACT_Msk [8/8]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

◆ SCB_SHCSR_SVCALLACT_Pos [1/8]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

◆ SCB_SHCSR_SVCALLACT_Pos [2/8]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

◆ SCB_SHCSR_SVCALLACT_Pos [3/8]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

◆ SCB_SHCSR_SVCALLACT_Pos [4/8]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

◆ SCB_SHCSR_SVCALLACT_Pos [5/8]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

◆ SCB_SHCSR_SVCALLACT_Pos [6/8]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

◆ SCB_SHCSR_SVCALLACT_Pos [7/8]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

◆ SCB_SHCSR_SVCALLACT_Pos [8/8]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

◆ SCB_SHCSR_SVCALLPENDED_Msk [1/12]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

◆ SCB_SHCSR_SVCALLPENDED_Msk [2/12]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

◆ SCB_SHCSR_SVCALLPENDED_Msk [3/12]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

◆ SCB_SHCSR_SVCALLPENDED_Msk [4/12]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

◆ SCB_SHCSR_SVCALLPENDED_Msk [5/12]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

◆ SCB_SHCSR_SVCALLPENDED_Msk [6/12]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

◆ SCB_SHCSR_SVCALLPENDED_Msk [7/12]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

◆ SCB_SHCSR_SVCALLPENDED_Msk [8/12]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

◆ SCB_SHCSR_SVCALLPENDED_Msk [9/12]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

◆ SCB_SHCSR_SVCALLPENDED_Msk [10/12]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

◆ SCB_SHCSR_SVCALLPENDED_Msk [11/12]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

◆ SCB_SHCSR_SVCALLPENDED_Msk [12/12]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

◆ SCB_SHCSR_SVCALLPENDED_Pos [1/12]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

◆ SCB_SHCSR_SVCALLPENDED_Pos [2/12]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

◆ SCB_SHCSR_SVCALLPENDED_Pos [3/12]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

◆ SCB_SHCSR_SVCALLPENDED_Pos [4/12]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

◆ SCB_SHCSR_SVCALLPENDED_Pos [5/12]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

◆ SCB_SHCSR_SVCALLPENDED_Pos [6/12]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

◆ SCB_SHCSR_SVCALLPENDED_Pos [7/12]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

◆ SCB_SHCSR_SVCALLPENDED_Pos [8/12]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

◆ SCB_SHCSR_SVCALLPENDED_Pos [9/12]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

◆ SCB_SHCSR_SVCALLPENDED_Pos [10/12]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

◆ SCB_SHCSR_SVCALLPENDED_Pos [11/12]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

◆ SCB_SHCSR_SVCALLPENDED_Pos [12/12]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

◆ SCB_SHCSR_SYSTICKACT_Msk [1/8]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

◆ SCB_SHCSR_SYSTICKACT_Msk [2/8]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

◆ SCB_SHCSR_SYSTICKACT_Msk [3/8]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

◆ SCB_SHCSR_SYSTICKACT_Msk [4/8]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

◆ SCB_SHCSR_SYSTICKACT_Msk [5/8]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

◆ SCB_SHCSR_SYSTICKACT_Msk [6/8]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

◆ SCB_SHCSR_SYSTICKACT_Msk [7/8]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

◆ SCB_SHCSR_SYSTICKACT_Msk [8/8]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

◆ SCB_SHCSR_SYSTICKACT_Pos [1/8]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

◆ SCB_SHCSR_SYSTICKACT_Pos [2/8]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

◆ SCB_SHCSR_SYSTICKACT_Pos [3/8]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

◆ SCB_SHCSR_SYSTICKACT_Pos [4/8]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

◆ SCB_SHCSR_SYSTICKACT_Pos [5/8]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

◆ SCB_SHCSR_SYSTICKACT_Pos [6/8]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

◆ SCB_SHCSR_SYSTICKACT_Pos [7/8]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

◆ SCB_SHCSR_SYSTICKACT_Pos [8/8]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

◆ SCB_SHCSR_USGFAULTACT_Msk [1/6]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

◆ SCB_SHCSR_USGFAULTACT_Msk [2/6]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

◆ SCB_SHCSR_USGFAULTACT_Msk [3/6]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

◆ SCB_SHCSR_USGFAULTACT_Msk [4/6]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

◆ SCB_SHCSR_USGFAULTACT_Msk [5/6]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

◆ SCB_SHCSR_USGFAULTACT_Msk [6/6]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

◆ SCB_SHCSR_USGFAULTACT_Pos [1/6]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

◆ SCB_SHCSR_USGFAULTACT_Pos [2/6]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

◆ SCB_SHCSR_USGFAULTACT_Pos [3/6]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

◆ SCB_SHCSR_USGFAULTACT_Pos [4/6]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

◆ SCB_SHCSR_USGFAULTACT_Pos [5/6]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

◆ SCB_SHCSR_USGFAULTACT_Pos [6/6]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

◆ SCB_SHCSR_USGFAULTENA_Msk [1/6]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

◆ SCB_SHCSR_USGFAULTENA_Msk [2/6]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

◆ SCB_SHCSR_USGFAULTENA_Msk [3/6]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

◆ SCB_SHCSR_USGFAULTENA_Msk [4/6]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

◆ SCB_SHCSR_USGFAULTENA_Msk [5/6]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

◆ SCB_SHCSR_USGFAULTENA_Msk [6/6]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

◆ SCB_SHCSR_USGFAULTENA_Pos [1/6]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

◆ SCB_SHCSR_USGFAULTENA_Pos [2/6]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

◆ SCB_SHCSR_USGFAULTENA_Pos [3/6]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

◆ SCB_SHCSR_USGFAULTENA_Pos [4/6]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

◆ SCB_SHCSR_USGFAULTENA_Pos [5/6]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

◆ SCB_SHCSR_USGFAULTENA_Pos [6/6]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

◆ SCB_SHCSR_USGFAULTPENDED_Msk [1/6]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

◆ SCB_SHCSR_USGFAULTPENDED_Msk [2/6]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

◆ SCB_SHCSR_USGFAULTPENDED_Msk [3/6]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

◆ SCB_SHCSR_USGFAULTPENDED_Msk [4/6]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

◆ SCB_SHCSR_USGFAULTPENDED_Msk [5/6]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

◆ SCB_SHCSR_USGFAULTPENDED_Msk [6/6]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

◆ SCB_SHCSR_USGFAULTPENDED_Pos [1/6]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

◆ SCB_SHCSR_USGFAULTPENDED_Pos [2/6]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

◆ SCB_SHCSR_USGFAULTPENDED_Pos [3/6]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

◆ SCB_SHCSR_USGFAULTPENDED_Pos [4/6]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

◆ SCB_SHCSR_USGFAULTPENDED_Pos [5/6]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

◆ SCB_SHCSR_USGFAULTPENDED_Pos [6/6]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

◆ SCB_STIR_INTID_Msk [1/2]

#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)

SCB STIR: INTID Mask

◆ SCB_STIR_INTID_Msk [2/2]

#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)

SCB STIR: INTID Mask

◆ SCB_STIR_INTID_Pos [1/2]

#define SCB_STIR_INTID_Pos   0U

SCB STIR: INTID Position

◆ SCB_STIR_INTID_Pos [2/2]

#define SCB_STIR_INTID_Pos   0U

SCB STIR: INTID Position

◆ SCB_VTOR_TBLBASE_Msk [1/2]

#define SCB_VTOR_TBLBASE_Msk   (1UL << SCB_VTOR_TBLBASE_Pos)

SCB VTOR: TBLBASE Mask

◆ SCB_VTOR_TBLBASE_Msk [2/2]

#define SCB_VTOR_TBLBASE_Msk   (1UL << SCB_VTOR_TBLBASE_Pos)

SCB VTOR: TBLBASE Mask

◆ SCB_VTOR_TBLBASE_Pos [1/2]

#define SCB_VTOR_TBLBASE_Pos   29U

SCB VTOR: TBLBASE Position

◆ SCB_VTOR_TBLBASE_Pos [2/2]

#define SCB_VTOR_TBLBASE_Pos   29U

SCB VTOR: TBLBASE Position

◆ SCB_VTOR_TBLOFF_Msk [1/7]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

◆ SCB_VTOR_TBLOFF_Msk [2/7]

#define SCB_VTOR_TBLOFF_Msk   (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

◆ SCB_VTOR_TBLOFF_Msk [3/7]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

◆ SCB_VTOR_TBLOFF_Msk [4/7]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

◆ SCB_VTOR_TBLOFF_Msk [5/7]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

◆ SCB_VTOR_TBLOFF_Msk [6/7]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

◆ SCB_VTOR_TBLOFF_Msk [7/7]

#define SCB_VTOR_TBLOFF_Msk   (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

◆ SCB_VTOR_TBLOFF_Pos [1/7]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

◆ SCB_VTOR_TBLOFF_Pos [2/7]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

◆ SCB_VTOR_TBLOFF_Pos [3/7]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

◆ SCB_VTOR_TBLOFF_Pos [4/7]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

◆ SCB_VTOR_TBLOFF_Pos [5/7]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

◆ SCB_VTOR_TBLOFF_Pos [6/7]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

◆ SCB_VTOR_TBLOFF_Pos [7/7]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

◆ SCnSCB [1/8]

#define SCnSCB   ((SCnSCB_Type *) SCS_BASE )

System control Register not in SCB

◆ SCnSCB [2/8]

#define SCnSCB   ((SCnSCB_Type *) SCS_BASE )

System control Register not in SCB

◆ SCnSCB [3/8]

#define SCnSCB   ((SCnSCB_Type *) SCS_BASE )

System control Register not in SCB

◆ SCnSCB [4/8]

#define SCnSCB   ((SCnSCB_Type *) SCS_BASE )

System control Register not in SCB

◆ SCnSCB [5/8]

#define SCnSCB   ((SCnSCB_Type *) SCS_BASE )

System control Register not in SCB

◆ SCnSCB [6/8]

#define SCnSCB   ((SCnSCB_Type *) SCS_BASE )

System control Register not in SCB

◆ SCnSCB [7/8]

#define SCnSCB   ((SCnSCB_Type *) SCS_BASE )

System control Register not in SCB

◆ SCnSCB [8/8]

#define SCnSCB   ((SCnSCB_Type *) SCS_BASE )

System control Register not in SCB

◆ SCnSCB_ACTLR_DISFOLD_Msk

#define SCnSCB_ACTLR_DISFOLD_Msk   (1UL << SCnSCB_ACTLR_DISFOLD_Pos)

ACTLR: DISFOLD Mask

◆ SCnSCB_ACTLR_DISFOLD_Pos

#define SCnSCB_ACTLR_DISFOLD_Pos   2U

ACTLR: DISFOLD Position

◆ SCnSCB_ICTR_INTLINESNUM_Msk [1/6]

#define SCnSCB_ICTR_INTLINESNUM_Msk   (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)

ICTR: INTLINESNUM Mask

◆ SCnSCB_ICTR_INTLINESNUM_Msk [2/6]

#define SCnSCB_ICTR_INTLINESNUM_Msk   (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)

ICTR: INTLINESNUM Mask

◆ SCnSCB_ICTR_INTLINESNUM_Msk [3/6]

#define SCnSCB_ICTR_INTLINESNUM_Msk   (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)

ICTR: INTLINESNUM Mask

◆ SCnSCB_ICTR_INTLINESNUM_Msk [4/6]

#define SCnSCB_ICTR_INTLINESNUM_Msk   (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)

ICTR: INTLINESNUM Mask

◆ SCnSCB_ICTR_INTLINESNUM_Msk [5/6]

#define SCnSCB_ICTR_INTLINESNUM_Msk   (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)

ICTR: INTLINESNUM Mask

◆ SCnSCB_ICTR_INTLINESNUM_Msk [6/6]

#define SCnSCB_ICTR_INTLINESNUM_Msk   (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)

ICTR: INTLINESNUM Mask

◆ SCnSCB_ICTR_INTLINESNUM_Pos [1/6]

#define SCnSCB_ICTR_INTLINESNUM_Pos   0U

ICTR: INTLINESNUM Position

◆ SCnSCB_ICTR_INTLINESNUM_Pos [2/6]

#define SCnSCB_ICTR_INTLINESNUM_Pos   0U

ICTR: INTLINESNUM Position

◆ SCnSCB_ICTR_INTLINESNUM_Pos [3/6]

#define SCnSCB_ICTR_INTLINESNUM_Pos   0U

ICTR: INTLINESNUM Position

◆ SCnSCB_ICTR_INTLINESNUM_Pos [4/6]

#define SCnSCB_ICTR_INTLINESNUM_Pos   0U

ICTR: INTLINESNUM Position

◆ SCnSCB_ICTR_INTLINESNUM_Pos [5/6]

#define SCnSCB_ICTR_INTLINESNUM_Pos   0U

ICTR: INTLINESNUM Position

◆ SCnSCB_ICTR_INTLINESNUM_Pos [6/6]

#define SCnSCB_ICTR_INTLINESNUM_Pos   0U

ICTR: INTLINESNUM Position

◆ SCS_BASE [1/12]

#define SCS_BASE   (0xE000E000UL)

System Control Space Base Address

◆ SCS_BASE [2/12]

#define SCS_BASE   (0xE000E000UL)

System Control Space Base Address

◆ SCS_BASE [3/12]

#define SCS_BASE   (0xE000E000UL)

System Control Space Base Address

◆ SCS_BASE [4/12]

#define SCS_BASE   (0xE000E000UL)

System Control Space Base Address

◆ SCS_BASE [5/12]

#define SCS_BASE   (0xE000E000UL)

System Control Space Base Address

◆ SCS_BASE [6/12]

#define SCS_BASE   (0xE000E000UL)

System Control Space Base Address

◆ SCS_BASE [7/12]

#define SCS_BASE   (0xE000E000UL)

System Control Space Base Address

◆ SCS_BASE [8/12]

#define SCS_BASE   (0xE000E000UL)

System Control Space Base Address

◆ SCS_BASE [9/12]

#define SCS_BASE   (0xE000E000UL)

System Control Space Base Address

◆ SCS_BASE [10/12]

#define SCS_BASE   (0xE000E000UL)

System Control Space Base Address

◆ SCS_BASE [11/12]

#define SCS_BASE   (0xE000E000UL)

System Control Space Base Address

◆ SCS_BASE [12/12]

#define SCS_BASE   (0xE000E000UL)

System Control Space Base Address

◆ SysTick [1/12]

#define SysTick   ((SysTick_Type *) SysTick_BASE )

SysTick configuration struct

◆ SysTick [2/12]

#define SysTick   ((SysTick_Type *) SysTick_BASE )

SysTick configuration struct

◆ SysTick [3/12]

#define SysTick   ((SysTick_Type *) SysTick_BASE )

SysTick configuration struct

◆ SysTick [4/12]

#define SysTick   ((SysTick_Type *) SysTick_BASE )

SysTick configuration struct

◆ SysTick [5/12]

#define SysTick   ((SysTick_Type *) SysTick_BASE )

SysTick configuration struct

◆ SysTick [6/12]

#define SysTick   ((SysTick_Type *) SysTick_BASE )

SysTick configuration struct

◆ SysTick [7/12]

#define SysTick   ((SysTick_Type *) SysTick_BASE )

SysTick configuration struct

◆ SysTick [8/12]

#define SysTick   ((SysTick_Type *) SysTick_BASE )

SysTick configuration struct

◆ SysTick [9/12]

#define SysTick   ((SysTick_Type *) SysTick_BASE )

SysTick configuration struct

◆ SysTick [10/12]

#define SysTick   ((SysTick_Type *) SysTick_BASE )

SysTick configuration struct

◆ SysTick [11/12]

#define SysTick   ((SysTick_Type *) SysTick_BASE )

SysTick configuration struct

◆ SysTick [12/12]

#define SysTick   ((SysTick_Type *) SysTick_BASE )

SysTick configuration struct

◆ SysTick_BASE [1/12]

#define SysTick_BASE   (SCS_BASE + 0x0010UL)

SysTick Base Address

◆ SysTick_BASE [2/12]

#define SysTick_BASE   (SCS_BASE + 0x0010UL)

SysTick Base Address

◆ SysTick_BASE [3/12]

#define SysTick_BASE   (SCS_BASE + 0x0010UL)

SysTick Base Address

◆ SysTick_BASE [4/12]

#define SysTick_BASE   (SCS_BASE + 0x0010UL)

SysTick Base Address

◆ SysTick_BASE [5/12]

#define SysTick_BASE   (SCS_BASE + 0x0010UL)

SysTick Base Address

◆ SysTick_BASE [6/12]

#define SysTick_BASE   (SCS_BASE + 0x0010UL)

SysTick Base Address

◆ SysTick_BASE [7/12]

#define SysTick_BASE   (SCS_BASE + 0x0010UL)

SysTick Base Address

◆ SysTick_BASE [8/12]

#define SysTick_BASE   (SCS_BASE + 0x0010UL)

SysTick Base Address

◆ SysTick_BASE [9/12]

#define SysTick_BASE   (SCS_BASE + 0x0010UL)

SysTick Base Address

◆ SysTick_BASE [10/12]

#define SysTick_BASE   (SCS_BASE + 0x0010UL)

SysTick Base Address

◆ SysTick_BASE [11/12]

#define SysTick_BASE   (SCS_BASE + 0x0010UL)

SysTick Base Address

◆ SysTick_BASE [12/12]

#define SysTick_BASE   (SCS_BASE + 0x0010UL)

SysTick Base Address

◆ SysTick_CALIB_NOREF_Msk [1/12]

#define SysTick_CALIB_NOREF_Msk   (1UL << SysTick_CALIB_NOREF_Pos)

SysTick CALIB: NOREF Mask

◆ SysTick_CALIB_NOREF_Msk [2/12]

#define SysTick_CALIB_NOREF_Msk   (1UL << SysTick_CALIB_NOREF_Pos)

SysTick CALIB: NOREF Mask

◆ SysTick_CALIB_NOREF_Msk [3/12]

#define SysTick_CALIB_NOREF_Msk   (1UL << SysTick_CALIB_NOREF_Pos)

SysTick CALIB: NOREF Mask

◆ SysTick_CALIB_NOREF_Msk [4/12]

#define SysTick_CALIB_NOREF_Msk   (1UL << SysTick_CALIB_NOREF_Pos)

SysTick CALIB: NOREF Mask

◆ SysTick_CALIB_NOREF_Msk [5/12]

#define SysTick_CALIB_NOREF_Msk   (1UL << SysTick_CALIB_NOREF_Pos)

SysTick CALIB: NOREF Mask

◆ SysTick_CALIB_NOREF_Msk [6/12]

#define SysTick_CALIB_NOREF_Msk   (1UL << SysTick_CALIB_NOREF_Pos)

SysTick CALIB: NOREF Mask

◆ SysTick_CALIB_NOREF_Msk [7/12]

#define SysTick_CALIB_NOREF_Msk   (1UL << SysTick_CALIB_NOREF_Pos)

SysTick CALIB: NOREF Mask

◆ SysTick_CALIB_NOREF_Msk [8/12]

#define SysTick_CALIB_NOREF_Msk   (1UL << SysTick_CALIB_NOREF_Pos)

SysTick CALIB: NOREF Mask

◆ SysTick_CALIB_NOREF_Msk [9/12]

#define SysTick_CALIB_NOREF_Msk   (1UL << SysTick_CALIB_NOREF_Pos)

SysTick CALIB: NOREF Mask

◆ SysTick_CALIB_NOREF_Msk [10/12]

#define SysTick_CALIB_NOREF_Msk   (1UL << SysTick_CALIB_NOREF_Pos)

SysTick CALIB: NOREF Mask

◆ SysTick_CALIB_NOREF_Msk [11/12]

#define SysTick_CALIB_NOREF_Msk   (1UL << SysTick_CALIB_NOREF_Pos)

SysTick CALIB: NOREF Mask

◆ SysTick_CALIB_NOREF_Msk [12/12]

#define SysTick_CALIB_NOREF_Msk   (1UL << SysTick_CALIB_NOREF_Pos)

SysTick CALIB: NOREF Mask

◆ SysTick_CALIB_NOREF_Pos [1/12]

#define SysTick_CALIB_NOREF_Pos   31U

SysTick CALIB: NOREF Position

◆ SysTick_CALIB_NOREF_Pos [2/12]

#define SysTick_CALIB_NOREF_Pos   31U

SysTick CALIB: NOREF Position

◆ SysTick_CALIB_NOREF_Pos [3/12]

#define SysTick_CALIB_NOREF_Pos   31U

SysTick CALIB: NOREF Position

◆ SysTick_CALIB_NOREF_Pos [4/12]

#define SysTick_CALIB_NOREF_Pos   31U

SysTick CALIB: NOREF Position

◆ SysTick_CALIB_NOREF_Pos [5/12]

#define SysTick_CALIB_NOREF_Pos   31U

SysTick CALIB: NOREF Position

◆ SysTick_CALIB_NOREF_Pos [6/12]

#define SysTick_CALIB_NOREF_Pos   31U

SysTick CALIB: NOREF Position

◆ SysTick_CALIB_NOREF_Pos [7/12]

#define SysTick_CALIB_NOREF_Pos   31U

SysTick CALIB: NOREF Position

◆ SysTick_CALIB_NOREF_Pos [8/12]

#define SysTick_CALIB_NOREF_Pos   31U

SysTick CALIB: NOREF Position

◆ SysTick_CALIB_NOREF_Pos [9/12]

#define SysTick_CALIB_NOREF_Pos   31U

SysTick CALIB: NOREF Position

◆ SysTick_CALIB_NOREF_Pos [10/12]

#define SysTick_CALIB_NOREF_Pos   31U

SysTick CALIB: NOREF Position

◆ SysTick_CALIB_NOREF_Pos [11/12]

#define SysTick_CALIB_NOREF_Pos   31U

SysTick CALIB: NOREF Position

◆ SysTick_CALIB_NOREF_Pos [12/12]

#define SysTick_CALIB_NOREF_Pos   31U

SysTick CALIB: NOREF Position

◆ SysTick_CALIB_SKEW_Msk [1/12]

#define SysTick_CALIB_SKEW_Msk   (1UL << SysTick_CALIB_SKEW_Pos)

SysTick CALIB: SKEW Mask

◆ SysTick_CALIB_SKEW_Msk [2/12]

#define SysTick_CALIB_SKEW_Msk   (1UL << SysTick_CALIB_SKEW_Pos)

SysTick CALIB: SKEW Mask

◆ SysTick_CALIB_SKEW_Msk [3/12]

#define SysTick_CALIB_SKEW_Msk   (1UL << SysTick_CALIB_SKEW_Pos)

SysTick CALIB: SKEW Mask

◆ SysTick_CALIB_SKEW_Msk [4/12]

#define SysTick_CALIB_SKEW_Msk   (1UL << SysTick_CALIB_SKEW_Pos)

SysTick CALIB: SKEW Mask

◆ SysTick_CALIB_SKEW_Msk [5/12]

#define SysTick_CALIB_SKEW_Msk   (1UL << SysTick_CALIB_SKEW_Pos)

SysTick CALIB: SKEW Mask

◆ SysTick_CALIB_SKEW_Msk [6/12]

#define SysTick_CALIB_SKEW_Msk   (1UL << SysTick_CALIB_SKEW_Pos)

SysTick CALIB: SKEW Mask

◆ SysTick_CALIB_SKEW_Msk [7/12]

#define SysTick_CALIB_SKEW_Msk   (1UL << SysTick_CALIB_SKEW_Pos)

SysTick CALIB: SKEW Mask

◆ SysTick_CALIB_SKEW_Msk [8/12]

#define SysTick_CALIB_SKEW_Msk   (1UL << SysTick_CALIB_SKEW_Pos)

SysTick CALIB: SKEW Mask

◆ SysTick_CALIB_SKEW_Msk [9/12]

#define SysTick_CALIB_SKEW_Msk   (1UL << SysTick_CALIB_SKEW_Pos)

SysTick CALIB: SKEW Mask

◆ SysTick_CALIB_SKEW_Msk [10/12]

#define SysTick_CALIB_SKEW_Msk   (1UL << SysTick_CALIB_SKEW_Pos)

SysTick CALIB: SKEW Mask

◆ SysTick_CALIB_SKEW_Msk [11/12]

#define SysTick_CALIB_SKEW_Msk   (1UL << SysTick_CALIB_SKEW_Pos)

SysTick CALIB: SKEW Mask

◆ SysTick_CALIB_SKEW_Msk [12/12]

#define SysTick_CALIB_SKEW_Msk   (1UL << SysTick_CALIB_SKEW_Pos)

SysTick CALIB: SKEW Mask

◆ SysTick_CALIB_SKEW_Pos [1/12]

#define SysTick_CALIB_SKEW_Pos   30U

SysTick CALIB: SKEW Position

◆ SysTick_CALIB_SKEW_Pos [2/12]

#define SysTick_CALIB_SKEW_Pos   30U

SysTick CALIB: SKEW Position

◆ SysTick_CALIB_SKEW_Pos [3/12]

#define SysTick_CALIB_SKEW_Pos   30U

SysTick CALIB: SKEW Position

◆ SysTick_CALIB_SKEW_Pos [4/12]

#define SysTick_CALIB_SKEW_Pos   30U

SysTick CALIB: SKEW Position

◆ SysTick_CALIB_SKEW_Pos [5/12]

#define SysTick_CALIB_SKEW_Pos   30U

SysTick CALIB: SKEW Position

◆ SysTick_CALIB_SKEW_Pos [6/12]

#define SysTick_CALIB_SKEW_Pos   30U

SysTick CALIB: SKEW Position

◆ SysTick_CALIB_SKEW_Pos [7/12]

#define SysTick_CALIB_SKEW_Pos   30U

SysTick CALIB: SKEW Position

◆ SysTick_CALIB_SKEW_Pos [8/12]

#define SysTick_CALIB_SKEW_Pos   30U

SysTick CALIB: SKEW Position

◆ SysTick_CALIB_SKEW_Pos [9/12]

#define SysTick_CALIB_SKEW_Pos   30U

SysTick CALIB: SKEW Position

◆ SysTick_CALIB_SKEW_Pos [10/12]

#define SysTick_CALIB_SKEW_Pos   30U

SysTick CALIB: SKEW Position

◆ SysTick_CALIB_SKEW_Pos [11/12]

#define SysTick_CALIB_SKEW_Pos   30U

SysTick CALIB: SKEW Position

◆ SysTick_CALIB_SKEW_Pos [12/12]

#define SysTick_CALIB_SKEW_Pos   30U

SysTick CALIB: SKEW Position

◆ SysTick_CALIB_TENMS_Msk [1/12]

#define SysTick_CALIB_TENMS_Msk   (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)

SysTick CALIB: TENMS Mask

◆ SysTick_CALIB_TENMS_Msk [2/12]

#define SysTick_CALIB_TENMS_Msk   (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)

SysTick CALIB: TENMS Mask

◆ SysTick_CALIB_TENMS_Msk [3/12]

#define SysTick_CALIB_TENMS_Msk   (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)

SysTick CALIB: TENMS Mask

◆ SysTick_CALIB_TENMS_Msk [4/12]

#define SysTick_CALIB_TENMS_Msk   (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)

SysTick CALIB: TENMS Mask

◆ SysTick_CALIB_TENMS_Msk [5/12]

#define SysTick_CALIB_TENMS_Msk   (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)

SysTick CALIB: TENMS Mask

◆ SysTick_CALIB_TENMS_Msk [6/12]

#define SysTick_CALIB_TENMS_Msk   (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)

SysTick CALIB: TENMS Mask

◆ SysTick_CALIB_TENMS_Msk [7/12]

#define SysTick_CALIB_TENMS_Msk   (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)

SysTick CALIB: TENMS Mask

◆ SysTick_CALIB_TENMS_Msk [8/12]

#define SysTick_CALIB_TENMS_Msk   (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)

SysTick CALIB: TENMS Mask

◆ SysTick_CALIB_TENMS_Msk [9/12]

#define SysTick_CALIB_TENMS_Msk   (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)

SysTick CALIB: TENMS Mask

◆ SysTick_CALIB_TENMS_Msk [10/12]

#define SysTick_CALIB_TENMS_Msk   (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)

SysTick CALIB: TENMS Mask

◆ SysTick_CALIB_TENMS_Msk [11/12]

#define SysTick_CALIB_TENMS_Msk   (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)

SysTick CALIB: TENMS Mask

◆ SysTick_CALIB_TENMS_Msk [12/12]

#define SysTick_CALIB_TENMS_Msk   (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)

SysTick CALIB: TENMS Mask

◆ SysTick_CALIB_TENMS_Pos [1/12]

#define SysTick_CALIB_TENMS_Pos   0U

SysTick CALIB: TENMS Position

◆ SysTick_CALIB_TENMS_Pos [2/12]

#define SysTick_CALIB_TENMS_Pos   0U

SysTick CALIB: TENMS Position

◆ SysTick_CALIB_TENMS_Pos [3/12]

#define SysTick_CALIB_TENMS_Pos   0U

SysTick CALIB: TENMS Position

◆ SysTick_CALIB_TENMS_Pos [4/12]

#define SysTick_CALIB_TENMS_Pos   0U

SysTick CALIB: TENMS Position

◆ SysTick_CALIB_TENMS_Pos [5/12]

#define SysTick_CALIB_TENMS_Pos   0U

SysTick CALIB: TENMS Position

◆ SysTick_CALIB_TENMS_Pos [6/12]

#define SysTick_CALIB_TENMS_Pos   0U

SysTick CALIB: TENMS Position

◆ SysTick_CALIB_TENMS_Pos [7/12]

#define SysTick_CALIB_TENMS_Pos   0U

SysTick CALIB: TENMS Position

◆ SysTick_CALIB_TENMS_Pos [8/12]

#define SysTick_CALIB_TENMS_Pos   0U

SysTick CALIB: TENMS Position

◆ SysTick_CALIB_TENMS_Pos [9/12]

#define SysTick_CALIB_TENMS_Pos   0U

SysTick CALIB: TENMS Position

◆ SysTick_CALIB_TENMS_Pos [10/12]

#define SysTick_CALIB_TENMS_Pos   0U

SysTick CALIB: TENMS Position

◆ SysTick_CALIB_TENMS_Pos [11/12]

#define SysTick_CALIB_TENMS_Pos   0U

SysTick CALIB: TENMS Position

◆ SysTick_CALIB_TENMS_Pos [12/12]

#define SysTick_CALIB_TENMS_Pos   0U

SysTick CALIB: TENMS Position

◆ SysTick_CTRL_CLKSOURCE_Msk [1/12]

#define SysTick_CTRL_CLKSOURCE_Msk   (1UL << SysTick_CTRL_CLKSOURCE_Pos)

SysTick CTRL: CLKSOURCE Mask

◆ SysTick_CTRL_CLKSOURCE_Msk [2/12]

#define SysTick_CTRL_CLKSOURCE_Msk   (1UL << SysTick_CTRL_CLKSOURCE_Pos)

SysTick CTRL: CLKSOURCE Mask

◆ SysTick_CTRL_CLKSOURCE_Msk [3/12]

#define SysTick_CTRL_CLKSOURCE_Msk   (1UL << SysTick_CTRL_CLKSOURCE_Pos)

SysTick CTRL: CLKSOURCE Mask

◆ SysTick_CTRL_CLKSOURCE_Msk [4/12]

#define SysTick_CTRL_CLKSOURCE_Msk   (1UL << SysTick_CTRL_CLKSOURCE_Pos)

SysTick CTRL: CLKSOURCE Mask

◆ SysTick_CTRL_CLKSOURCE_Msk [5/12]

#define SysTick_CTRL_CLKSOURCE_Msk   (1UL << SysTick_CTRL_CLKSOURCE_Pos)

SysTick CTRL: CLKSOURCE Mask

◆ SysTick_CTRL_CLKSOURCE_Msk [6/12]

#define SysTick_CTRL_CLKSOURCE_Msk   (1UL << SysTick_CTRL_CLKSOURCE_Pos)

SysTick CTRL: CLKSOURCE Mask

◆ SysTick_CTRL_CLKSOURCE_Msk [7/12]

#define SysTick_CTRL_CLKSOURCE_Msk   (1UL << SysTick_CTRL_CLKSOURCE_Pos)

SysTick CTRL: CLKSOURCE Mask

◆ SysTick_CTRL_CLKSOURCE_Msk [8/12]

#define SysTick_CTRL_CLKSOURCE_Msk   (1UL << SysTick_CTRL_CLKSOURCE_Pos)

SysTick CTRL: CLKSOURCE Mask

◆ SysTick_CTRL_CLKSOURCE_Msk [9/12]

#define SysTick_CTRL_CLKSOURCE_Msk   (1UL << SysTick_CTRL_CLKSOURCE_Pos)

SysTick CTRL: CLKSOURCE Mask

◆ SysTick_CTRL_CLKSOURCE_Msk [10/12]

#define SysTick_CTRL_CLKSOURCE_Msk   (1UL << SysTick_CTRL_CLKSOURCE_Pos)

SysTick CTRL: CLKSOURCE Mask

◆ SysTick_CTRL_CLKSOURCE_Msk [11/12]

#define SysTick_CTRL_CLKSOURCE_Msk   (1UL << SysTick_CTRL_CLKSOURCE_Pos)

SysTick CTRL: CLKSOURCE Mask

◆ SysTick_CTRL_CLKSOURCE_Msk [12/12]

#define SysTick_CTRL_CLKSOURCE_Msk   (1UL << SysTick_CTRL_CLKSOURCE_Pos)

SysTick CTRL: CLKSOURCE Mask

◆ SysTick_CTRL_CLKSOURCE_Pos [1/12]

#define SysTick_CTRL_CLKSOURCE_Pos   2U

SysTick CTRL: CLKSOURCE Position

◆ SysTick_CTRL_CLKSOURCE_Pos [2/12]

#define SysTick_CTRL_CLKSOURCE_Pos   2U

SysTick CTRL: CLKSOURCE Position

◆ SysTick_CTRL_CLKSOURCE_Pos [3/12]

#define SysTick_CTRL_CLKSOURCE_Pos   2U

SysTick CTRL: CLKSOURCE Position

◆ SysTick_CTRL_CLKSOURCE_Pos [4/12]

#define SysTick_CTRL_CLKSOURCE_Pos   2U

SysTick CTRL: CLKSOURCE Position

◆ SysTick_CTRL_CLKSOURCE_Pos [5/12]

#define SysTick_CTRL_CLKSOURCE_Pos   2U

SysTick CTRL: CLKSOURCE Position

◆ SysTick_CTRL_CLKSOURCE_Pos [6/12]

#define SysTick_CTRL_CLKSOURCE_Pos   2U

SysTick CTRL: CLKSOURCE Position

◆ SysTick_CTRL_CLKSOURCE_Pos [7/12]

#define SysTick_CTRL_CLKSOURCE_Pos   2U

SysTick CTRL: CLKSOURCE Position

◆ SysTick_CTRL_CLKSOURCE_Pos [8/12]

#define SysTick_CTRL_CLKSOURCE_Pos   2U

SysTick CTRL: CLKSOURCE Position

◆ SysTick_CTRL_CLKSOURCE_Pos [9/12]

#define SysTick_CTRL_CLKSOURCE_Pos   2U

SysTick CTRL: CLKSOURCE Position

◆ SysTick_CTRL_CLKSOURCE_Pos [10/12]

#define SysTick_CTRL_CLKSOURCE_Pos   2U

SysTick CTRL: CLKSOURCE Position

◆ SysTick_CTRL_CLKSOURCE_Pos [11/12]

#define SysTick_CTRL_CLKSOURCE_Pos   2U

SysTick CTRL: CLKSOURCE Position

◆ SysTick_CTRL_CLKSOURCE_Pos [12/12]

#define SysTick_CTRL_CLKSOURCE_Pos   2U

SysTick CTRL: CLKSOURCE Position

◆ SysTick_CTRL_COUNTFLAG_Msk [1/12]

#define SysTick_CTRL_COUNTFLAG_Msk   (1UL << SysTick_CTRL_COUNTFLAG_Pos)

SysTick CTRL: COUNTFLAG Mask

◆ SysTick_CTRL_COUNTFLAG_Msk [2/12]

#define SysTick_CTRL_COUNTFLAG_Msk   (1UL << SysTick_CTRL_COUNTFLAG_Pos)

SysTick CTRL: COUNTFLAG Mask

◆ SysTick_CTRL_COUNTFLAG_Msk [3/12]

#define SysTick_CTRL_COUNTFLAG_Msk   (1UL << SysTick_CTRL_COUNTFLAG_Pos)

SysTick CTRL: COUNTFLAG Mask

◆ SysTick_CTRL_COUNTFLAG_Msk [4/12]

#define SysTick_CTRL_COUNTFLAG_Msk   (1UL << SysTick_CTRL_COUNTFLAG_Pos)

SysTick CTRL: COUNTFLAG Mask

◆ SysTick_CTRL_COUNTFLAG_Msk [5/12]

#define SysTick_CTRL_COUNTFLAG_Msk   (1UL << SysTick_CTRL_COUNTFLAG_Pos)

SysTick CTRL: COUNTFLAG Mask

◆ SysTick_CTRL_COUNTFLAG_Msk [6/12]

#define SysTick_CTRL_COUNTFLAG_Msk   (1UL << SysTick_CTRL_COUNTFLAG_Pos)

SysTick CTRL: COUNTFLAG Mask

◆ SysTick_CTRL_COUNTFLAG_Msk [7/12]

#define SysTick_CTRL_COUNTFLAG_Msk   (1UL << SysTick_CTRL_COUNTFLAG_Pos)

SysTick CTRL: COUNTFLAG Mask

◆ SysTick_CTRL_COUNTFLAG_Msk [8/12]

#define SysTick_CTRL_COUNTFLAG_Msk   (1UL << SysTick_CTRL_COUNTFLAG_Pos)

SysTick CTRL: COUNTFLAG Mask

◆ SysTick_CTRL_COUNTFLAG_Msk [9/12]

#define SysTick_CTRL_COUNTFLAG_Msk   (1UL << SysTick_CTRL_COUNTFLAG_Pos)

SysTick CTRL: COUNTFLAG Mask

◆ SysTick_CTRL_COUNTFLAG_Msk [10/12]

#define SysTick_CTRL_COUNTFLAG_Msk   (1UL << SysTick_CTRL_COUNTFLAG_Pos)

SysTick CTRL: COUNTFLAG Mask

◆ SysTick_CTRL_COUNTFLAG_Msk [11/12]

#define SysTick_CTRL_COUNTFLAG_Msk   (1UL << SysTick_CTRL_COUNTFLAG_Pos)

SysTick CTRL: COUNTFLAG Mask

◆ SysTick_CTRL_COUNTFLAG_Msk [12/12]

#define SysTick_CTRL_COUNTFLAG_Msk   (1UL << SysTick_CTRL_COUNTFLAG_Pos)

SysTick CTRL: COUNTFLAG Mask

◆ SysTick_CTRL_COUNTFLAG_Pos [1/12]

#define SysTick_CTRL_COUNTFLAG_Pos   16U

SysTick CTRL: COUNTFLAG Position

◆ SysTick_CTRL_COUNTFLAG_Pos [2/12]

#define SysTick_CTRL_COUNTFLAG_Pos   16U

SysTick CTRL: COUNTFLAG Position

◆ SysTick_CTRL_COUNTFLAG_Pos [3/12]

#define SysTick_CTRL_COUNTFLAG_Pos   16U

SysTick CTRL: COUNTFLAG Position

◆ SysTick_CTRL_COUNTFLAG_Pos [4/12]

#define SysTick_CTRL_COUNTFLAG_Pos   16U

SysTick CTRL: COUNTFLAG Position

◆ SysTick_CTRL_COUNTFLAG_Pos [5/12]

#define SysTick_CTRL_COUNTFLAG_Pos   16U

SysTick CTRL: COUNTFLAG Position

◆ SysTick_CTRL_COUNTFLAG_Pos [6/12]

#define SysTick_CTRL_COUNTFLAG_Pos   16U

SysTick CTRL: COUNTFLAG Position

◆ SysTick_CTRL_COUNTFLAG_Pos [7/12]

#define SysTick_CTRL_COUNTFLAG_Pos   16U

SysTick CTRL: COUNTFLAG Position

◆ SysTick_CTRL_COUNTFLAG_Pos [8/12]

#define SysTick_CTRL_COUNTFLAG_Pos   16U

SysTick CTRL: COUNTFLAG Position

◆ SysTick_CTRL_COUNTFLAG_Pos [9/12]

#define SysTick_CTRL_COUNTFLAG_Pos   16U

SysTick CTRL: COUNTFLAG Position

◆ SysTick_CTRL_COUNTFLAG_Pos [10/12]

#define SysTick_CTRL_COUNTFLAG_Pos   16U

SysTick CTRL: COUNTFLAG Position

◆ SysTick_CTRL_COUNTFLAG_Pos [11/12]

#define SysTick_CTRL_COUNTFLAG_Pos   16U

SysTick CTRL: COUNTFLAG Position

◆ SysTick_CTRL_COUNTFLAG_Pos [12/12]

#define SysTick_CTRL_COUNTFLAG_Pos   16U

SysTick CTRL: COUNTFLAG Position

◆ SysTick_CTRL_ENABLE_Msk [1/12]

#define SysTick_CTRL_ENABLE_Msk   (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)

SysTick CTRL: ENABLE Mask

◆ SysTick_CTRL_ENABLE_Msk [2/12]

#define SysTick_CTRL_ENABLE_Msk   (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)

SysTick CTRL: ENABLE Mask

◆ SysTick_CTRL_ENABLE_Msk [3/12]

#define SysTick_CTRL_ENABLE_Msk   (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)

SysTick CTRL: ENABLE Mask

◆ SysTick_CTRL_ENABLE_Msk [4/12]

#define SysTick_CTRL_ENABLE_Msk   (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)

SysTick CTRL: ENABLE Mask

◆ SysTick_CTRL_ENABLE_Msk [5/12]

#define SysTick_CTRL_ENABLE_Msk   (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)

SysTick CTRL: ENABLE Mask

◆ SysTick_CTRL_ENABLE_Msk [6/12]

#define SysTick_CTRL_ENABLE_Msk   (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)

SysTick CTRL: ENABLE Mask

◆ SysTick_CTRL_ENABLE_Msk [7/12]

#define SysTick_CTRL_ENABLE_Msk   (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)

SysTick CTRL: ENABLE Mask

◆ SysTick_CTRL_ENABLE_Msk [8/12]

#define SysTick_CTRL_ENABLE_Msk   (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)

SysTick CTRL: ENABLE Mask

◆ SysTick_CTRL_ENABLE_Msk [9/12]

#define SysTick_CTRL_ENABLE_Msk   (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)

SysTick CTRL: ENABLE Mask

◆ SysTick_CTRL_ENABLE_Msk [10/12]

#define SysTick_CTRL_ENABLE_Msk   (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)

SysTick CTRL: ENABLE Mask

◆ SysTick_CTRL_ENABLE_Msk [11/12]

#define SysTick_CTRL_ENABLE_Msk   (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)

SysTick CTRL: ENABLE Mask

◆ SysTick_CTRL_ENABLE_Msk [12/12]

#define SysTick_CTRL_ENABLE_Msk   (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)

SysTick CTRL: ENABLE Mask

◆ SysTick_CTRL_ENABLE_Pos [1/12]

#define SysTick_CTRL_ENABLE_Pos   0U

SysTick CTRL: ENABLE Position

◆ SysTick_CTRL_ENABLE_Pos [2/12]

#define SysTick_CTRL_ENABLE_Pos   0U

SysTick CTRL: ENABLE Position

◆ SysTick_CTRL_ENABLE_Pos [3/12]

#define SysTick_CTRL_ENABLE_Pos   0U

SysTick CTRL: ENABLE Position

◆ SysTick_CTRL_ENABLE_Pos [4/12]

#define SysTick_CTRL_ENABLE_Pos   0U

SysTick CTRL: ENABLE Position

◆ SysTick_CTRL_ENABLE_Pos [5/12]

#define SysTick_CTRL_ENABLE_Pos   0U

SysTick CTRL: ENABLE Position

◆ SysTick_CTRL_ENABLE_Pos [6/12]

#define SysTick_CTRL_ENABLE_Pos   0U

SysTick CTRL: ENABLE Position

◆ SysTick_CTRL_ENABLE_Pos [7/12]

#define SysTick_CTRL_ENABLE_Pos   0U

SysTick CTRL: ENABLE Position

◆ SysTick_CTRL_ENABLE_Pos [8/12]

#define SysTick_CTRL_ENABLE_Pos   0U

SysTick CTRL: ENABLE Position

◆ SysTick_CTRL_ENABLE_Pos [9/12]

#define SysTick_CTRL_ENABLE_Pos   0U

SysTick CTRL: ENABLE Position

◆ SysTick_CTRL_ENABLE_Pos [10/12]

#define SysTick_CTRL_ENABLE_Pos   0U

SysTick CTRL: ENABLE Position

◆ SysTick_CTRL_ENABLE_Pos [11/12]

#define SysTick_CTRL_ENABLE_Pos   0U

SysTick CTRL: ENABLE Position

◆ SysTick_CTRL_ENABLE_Pos [12/12]

#define SysTick_CTRL_ENABLE_Pos   0U

SysTick CTRL: ENABLE Position

◆ SysTick_CTRL_TICKINT_Msk [1/12]

#define SysTick_CTRL_TICKINT_Msk   (1UL << SysTick_CTRL_TICKINT_Pos)

SysTick CTRL: TICKINT Mask

◆ SysTick_CTRL_TICKINT_Msk [2/12]

#define SysTick_CTRL_TICKINT_Msk   (1UL << SysTick_CTRL_TICKINT_Pos)

SysTick CTRL: TICKINT Mask

◆ SysTick_CTRL_TICKINT_Msk [3/12]

#define SysTick_CTRL_TICKINT_Msk   (1UL << SysTick_CTRL_TICKINT_Pos)

SysTick CTRL: TICKINT Mask

◆ SysTick_CTRL_TICKINT_Msk [4/12]

#define SysTick_CTRL_TICKINT_Msk   (1UL << SysTick_CTRL_TICKINT_Pos)

SysTick CTRL: TICKINT Mask

◆ SysTick_CTRL_TICKINT_Msk [5/12]

#define SysTick_CTRL_TICKINT_Msk   (1UL << SysTick_CTRL_TICKINT_Pos)

SysTick CTRL: TICKINT Mask

◆ SysTick_CTRL_TICKINT_Msk [6/12]

#define SysTick_CTRL_TICKINT_Msk   (1UL << SysTick_CTRL_TICKINT_Pos)

SysTick CTRL: TICKINT Mask

◆ SysTick_CTRL_TICKINT_Msk [7/12]

#define SysTick_CTRL_TICKINT_Msk   (1UL << SysTick_CTRL_TICKINT_Pos)

SysTick CTRL: TICKINT Mask

◆ SysTick_CTRL_TICKINT_Msk [8/12]

#define SysTick_CTRL_TICKINT_Msk   (1UL << SysTick_CTRL_TICKINT_Pos)

SysTick CTRL: TICKINT Mask

◆ SysTick_CTRL_TICKINT_Msk [9/12]

#define SysTick_CTRL_TICKINT_Msk   (1UL << SysTick_CTRL_TICKINT_Pos)

SysTick CTRL: TICKINT Mask

◆ SysTick_CTRL_TICKINT_Msk [10/12]

#define SysTick_CTRL_TICKINT_Msk   (1UL << SysTick_CTRL_TICKINT_Pos)

SysTick CTRL: TICKINT Mask

◆ SysTick_CTRL_TICKINT_Msk [11/12]

#define SysTick_CTRL_TICKINT_Msk   (1UL << SysTick_CTRL_TICKINT_Pos)

SysTick CTRL: TICKINT Mask

◆ SysTick_CTRL_TICKINT_Msk [12/12]

#define SysTick_CTRL_TICKINT_Msk   (1UL << SysTick_CTRL_TICKINT_Pos)

SysTick CTRL: TICKINT Mask

◆ SysTick_CTRL_TICKINT_Pos [1/12]

#define SysTick_CTRL_TICKINT_Pos   1U

SysTick CTRL: TICKINT Position

◆ SysTick_CTRL_TICKINT_Pos [2/12]

#define SysTick_CTRL_TICKINT_Pos   1U

SysTick CTRL: TICKINT Position

◆ SysTick_CTRL_TICKINT_Pos [3/12]

#define SysTick_CTRL_TICKINT_Pos   1U

SysTick CTRL: TICKINT Position

◆ SysTick_CTRL_TICKINT_Pos [4/12]

#define SysTick_CTRL_TICKINT_Pos   1U

SysTick CTRL: TICKINT Position

◆ SysTick_CTRL_TICKINT_Pos [5/12]

#define SysTick_CTRL_TICKINT_Pos   1U

SysTick CTRL: TICKINT Position

◆ SysTick_CTRL_TICKINT_Pos [6/12]

#define SysTick_CTRL_TICKINT_Pos   1U

SysTick CTRL: TICKINT Position

◆ SysTick_CTRL_TICKINT_Pos [7/12]

#define SysTick_CTRL_TICKINT_Pos   1U

SysTick CTRL: TICKINT Position

◆ SysTick_CTRL_TICKINT_Pos [8/12]

#define SysTick_CTRL_TICKINT_Pos   1U

SysTick CTRL: TICKINT Position

◆ SysTick_CTRL_TICKINT_Pos [9/12]

#define SysTick_CTRL_TICKINT_Pos   1U

SysTick CTRL: TICKINT Position

◆ SysTick_CTRL_TICKINT_Pos [10/12]

#define SysTick_CTRL_TICKINT_Pos   1U

SysTick CTRL: TICKINT Position

◆ SysTick_CTRL_TICKINT_Pos [11/12]

#define SysTick_CTRL_TICKINT_Pos   1U

SysTick CTRL: TICKINT Position

◆ SysTick_CTRL_TICKINT_Pos [12/12]

#define SysTick_CTRL_TICKINT_Pos   1U

SysTick CTRL: TICKINT Position

◆ SysTick_LOAD_RELOAD_Msk [1/12]

#define SysTick_LOAD_RELOAD_Msk   (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)

SysTick LOAD: RELOAD Mask

◆ SysTick_LOAD_RELOAD_Msk [2/12]

#define SysTick_LOAD_RELOAD_Msk   (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)

SysTick LOAD: RELOAD Mask

◆ SysTick_LOAD_RELOAD_Msk [3/12]

#define SysTick_LOAD_RELOAD_Msk   (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)

SysTick LOAD: RELOAD Mask

◆ SysTick_LOAD_RELOAD_Msk [4/12]

#define SysTick_LOAD_RELOAD_Msk   (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)

SysTick LOAD: RELOAD Mask

◆ SysTick_LOAD_RELOAD_Msk [5/12]

#define SysTick_LOAD_RELOAD_Msk   (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)

SysTick LOAD: RELOAD Mask

◆ SysTick_LOAD_RELOAD_Msk [6/12]

#define SysTick_LOAD_RELOAD_Msk   (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)

SysTick LOAD: RELOAD Mask

◆ SysTick_LOAD_RELOAD_Msk [7/12]

#define SysTick_LOAD_RELOAD_Msk   (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)

SysTick LOAD: RELOAD Mask

◆ SysTick_LOAD_RELOAD_Msk [8/12]

#define SysTick_LOAD_RELOAD_Msk   (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)

SysTick LOAD: RELOAD Mask

◆ SysTick_LOAD_RELOAD_Msk [9/12]

#define SysTick_LOAD_RELOAD_Msk   (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)

SysTick LOAD: RELOAD Mask

◆ SysTick_LOAD_RELOAD_Msk [10/12]

#define SysTick_LOAD_RELOAD_Msk   (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)

SysTick LOAD: RELOAD Mask

◆ SysTick_LOAD_RELOAD_Msk [11/12]

#define SysTick_LOAD_RELOAD_Msk   (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)

SysTick LOAD: RELOAD Mask

◆ SysTick_LOAD_RELOAD_Msk [12/12]

#define SysTick_LOAD_RELOAD_Msk   (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)

SysTick LOAD: RELOAD Mask

◆ SysTick_LOAD_RELOAD_Pos [1/12]

#define SysTick_LOAD_RELOAD_Pos   0U

SysTick LOAD: RELOAD Position

◆ SysTick_LOAD_RELOAD_Pos [2/12]

#define SysTick_LOAD_RELOAD_Pos   0U

SysTick LOAD: RELOAD Position

◆ SysTick_LOAD_RELOAD_Pos [3/12]

#define SysTick_LOAD_RELOAD_Pos   0U

SysTick LOAD: RELOAD Position

◆ SysTick_LOAD_RELOAD_Pos [4/12]

#define SysTick_LOAD_RELOAD_Pos   0U

SysTick LOAD: RELOAD Position

◆ SysTick_LOAD_RELOAD_Pos [5/12]

#define SysTick_LOAD_RELOAD_Pos   0U

SysTick LOAD: RELOAD Position

◆ SysTick_LOAD_RELOAD_Pos [6/12]

#define SysTick_LOAD_RELOAD_Pos   0U

SysTick LOAD: RELOAD Position

◆ SysTick_LOAD_RELOAD_Pos [7/12]

#define SysTick_LOAD_RELOAD_Pos   0U

SysTick LOAD: RELOAD Position

◆ SysTick_LOAD_RELOAD_Pos [8/12]

#define SysTick_LOAD_RELOAD_Pos   0U

SysTick LOAD: RELOAD Position

◆ SysTick_LOAD_RELOAD_Pos [9/12]

#define SysTick_LOAD_RELOAD_Pos   0U

SysTick LOAD: RELOAD Position

◆ SysTick_LOAD_RELOAD_Pos [10/12]

#define SysTick_LOAD_RELOAD_Pos   0U

SysTick LOAD: RELOAD Position

◆ SysTick_LOAD_RELOAD_Pos [11/12]

#define SysTick_LOAD_RELOAD_Pos   0U

SysTick LOAD: RELOAD Position

◆ SysTick_LOAD_RELOAD_Pos [12/12]

#define SysTick_LOAD_RELOAD_Pos   0U

SysTick LOAD: RELOAD Position

◆ SysTick_VAL_CURRENT_Msk [1/12]

#define SysTick_VAL_CURRENT_Msk   (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)

SysTick VAL: CURRENT Mask

◆ SysTick_VAL_CURRENT_Msk [2/12]

#define SysTick_VAL_CURRENT_Msk   (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)

SysTick VAL: CURRENT Mask

◆ SysTick_VAL_CURRENT_Msk [3/12]

#define SysTick_VAL_CURRENT_Msk   (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)

SysTick VAL: CURRENT Mask

◆ SysTick_VAL_CURRENT_Msk [4/12]

#define SysTick_VAL_CURRENT_Msk   (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)

SysTick VAL: CURRENT Mask

◆ SysTick_VAL_CURRENT_Msk [5/12]

#define SysTick_VAL_CURRENT_Msk   (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)

SysTick VAL: CURRENT Mask

◆ SysTick_VAL_CURRENT_Msk [6/12]

#define SysTick_VAL_CURRENT_Msk   (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)

SysTick VAL: CURRENT Mask

◆ SysTick_VAL_CURRENT_Msk [7/12]

#define SysTick_VAL_CURRENT_Msk   (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)

SysTick VAL: CURRENT Mask

◆ SysTick_VAL_CURRENT_Msk [8/12]

#define SysTick_VAL_CURRENT_Msk   (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)

SysTick VAL: CURRENT Mask

◆ SysTick_VAL_CURRENT_Msk [9/12]

#define SysTick_VAL_CURRENT_Msk   (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)

SysTick VAL: CURRENT Mask

◆ SysTick_VAL_CURRENT_Msk [10/12]

#define SysTick_VAL_CURRENT_Msk   (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)

SysTick VAL: CURRENT Mask

◆ SysTick_VAL_CURRENT_Msk [11/12]

#define SysTick_VAL_CURRENT_Msk   (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)

SysTick VAL: CURRENT Mask

◆ SysTick_VAL_CURRENT_Msk [12/12]

#define SysTick_VAL_CURRENT_Msk   (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)

SysTick VAL: CURRENT Mask

◆ SysTick_VAL_CURRENT_Pos [1/12]

#define SysTick_VAL_CURRENT_Pos   0U

SysTick VAL: CURRENT Position

◆ SysTick_VAL_CURRENT_Pos [2/12]

#define SysTick_VAL_CURRENT_Pos   0U

SysTick VAL: CURRENT Position

◆ SysTick_VAL_CURRENT_Pos [3/12]

#define SysTick_VAL_CURRENT_Pos   0U

SysTick VAL: CURRENT Position

◆ SysTick_VAL_CURRENT_Pos [4/12]

#define SysTick_VAL_CURRENT_Pos   0U

SysTick VAL: CURRENT Position

◆ SysTick_VAL_CURRENT_Pos [5/12]

#define SysTick_VAL_CURRENT_Pos   0U

SysTick VAL: CURRENT Position

◆ SysTick_VAL_CURRENT_Pos [6/12]

#define SysTick_VAL_CURRENT_Pos   0U

SysTick VAL: CURRENT Position

◆ SysTick_VAL_CURRENT_Pos [7/12]

#define SysTick_VAL_CURRENT_Pos   0U

SysTick VAL: CURRENT Position

◆ SysTick_VAL_CURRENT_Pos [8/12]

#define SysTick_VAL_CURRENT_Pos   0U

SysTick VAL: CURRENT Position

◆ SysTick_VAL_CURRENT_Pos [9/12]

#define SysTick_VAL_CURRENT_Pos   0U

SysTick VAL: CURRENT Position

◆ SysTick_VAL_CURRENT_Pos [10/12]

#define SysTick_VAL_CURRENT_Pos   0U

SysTick VAL: CURRENT Position

◆ SysTick_VAL_CURRENT_Pos [11/12]

#define SysTick_VAL_CURRENT_Pos   0U

SysTick VAL: CURRENT Position

◆ SysTick_VAL_CURRENT_Pos [12/12]

#define SysTick_VAL_CURRENT_Pos   0U

SysTick VAL: CURRENT Position

◆ TPI [1/8]

#define TPI   ((TPI_Type *) TPI_BASE )

TPI configuration struct

◆ TPI [2/8]

#define TPI   ((TPI_Type *) TPI_BASE )

TPI configuration struct

◆ TPI [3/8]

#define TPI   ((TPI_Type *) TPI_BASE )

TPI configuration struct

◆ TPI [4/8]

#define TPI   ((TPI_Type *) TPI_BASE )

TPI configuration struct

◆ TPI [5/8]

#define TPI   ((TPI_Type *) TPI_BASE )

TPI configuration struct

◆ TPI [6/8]

#define TPI   ((TPI_Type *) TPI_BASE )

TPI configuration struct

◆ TPI [7/8]

#define TPI   ((TPI_Type *) TPI_BASE )

TPI configuration struct

◆ TPI [8/8]

#define TPI   ((TPI_Type *) TPI_BASE )

TPI configuration struct

◆ TPI_ACPR_PRESCALER_Msk [1/6]

#define TPI_ACPR_PRESCALER_Msk   (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

◆ TPI_ACPR_PRESCALER_Msk [2/6]

#define TPI_ACPR_PRESCALER_Msk   (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

◆ TPI_ACPR_PRESCALER_Msk [3/6]

#define TPI_ACPR_PRESCALER_Msk   (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

◆ TPI_ACPR_PRESCALER_Msk [4/6]

#define TPI_ACPR_PRESCALER_Msk   (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

◆ TPI_ACPR_PRESCALER_Msk [5/6]

#define TPI_ACPR_PRESCALER_Msk   (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

◆ TPI_ACPR_PRESCALER_Msk [6/6]

#define TPI_ACPR_PRESCALER_Msk   (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

◆ TPI_ACPR_PRESCALER_Pos [1/6]

#define TPI_ACPR_PRESCALER_Pos   0U

TPI ACPR: PRESCALER Position

◆ TPI_ACPR_PRESCALER_Pos [2/6]

#define TPI_ACPR_PRESCALER_Pos   0U

TPI ACPR: PRESCALER Position

◆ TPI_ACPR_PRESCALER_Pos [3/6]

#define TPI_ACPR_PRESCALER_Pos   0U

TPI ACPR: PRESCALER Position

◆ TPI_ACPR_PRESCALER_Pos [4/6]

#define TPI_ACPR_PRESCALER_Pos   0U

TPI ACPR: PRESCALER Position

◆ TPI_ACPR_PRESCALER_Pos [5/6]

#define TPI_ACPR_PRESCALER_Pos   0U

TPI ACPR: PRESCALER Position

◆ TPI_ACPR_PRESCALER_Pos [6/6]

#define TPI_ACPR_PRESCALER_Pos   0U

TPI ACPR: PRESCALER Position

◆ TPI_BASE [1/8]

#define TPI_BASE   (0xE0040000UL)

TPI Base Address

◆ TPI_BASE [2/8]

#define TPI_BASE   (0xE0040000UL)

TPI Base Address

◆ TPI_BASE [3/8]

#define TPI_BASE   (0xE0040000UL)

TPI Base Address

◆ TPI_BASE [4/8]

#define TPI_BASE   (0xE0040000UL)

TPI Base Address

◆ TPI_BASE [5/8]

#define TPI_BASE   (0xE0040000UL)

TPI Base Address

◆ TPI_BASE [6/8]

#define TPI_BASE   (0xE0040000UL)

TPI Base Address

◆ TPI_BASE [7/8]

#define TPI_BASE   (0xE0040000UL)

TPI Base Address

◆ TPI_BASE [8/8]

#define TPI_BASE   (0xE0040000UL)

TPI Base Address

◆ TPI_DEVID_AsynClkIn_Msk [1/4]

#define TPI_DEVID_AsynClkIn_Msk   (0x1UL << TPI_DEVID_AsynClkIn_Pos)

TPI DEVID: AsynClkIn Mask

◆ TPI_DEVID_AsynClkIn_Msk [2/4]

#define TPI_DEVID_AsynClkIn_Msk   (0x1UL << TPI_DEVID_AsynClkIn_Pos)

TPI DEVID: AsynClkIn Mask

◆ TPI_DEVID_AsynClkIn_Msk [3/4]

#define TPI_DEVID_AsynClkIn_Msk   (0x1UL << TPI_DEVID_AsynClkIn_Pos)

TPI DEVID: AsynClkIn Mask

◆ TPI_DEVID_AsynClkIn_Msk [4/4]

#define TPI_DEVID_AsynClkIn_Msk   (0x1UL << TPI_DEVID_AsynClkIn_Pos)

TPI DEVID: AsynClkIn Mask

◆ TPI_DEVID_AsynClkIn_Pos [1/4]

#define TPI_DEVID_AsynClkIn_Pos   5U

TPI DEVID: AsynClkIn Position

◆ TPI_DEVID_AsynClkIn_Pos [2/4]

#define TPI_DEVID_AsynClkIn_Pos   5U

TPI DEVID: AsynClkIn Position

◆ TPI_DEVID_AsynClkIn_Pos [3/4]

#define TPI_DEVID_AsynClkIn_Pos   5U

TPI DEVID: AsynClkIn Position

◆ TPI_DEVID_AsynClkIn_Pos [4/4]

#define TPI_DEVID_AsynClkIn_Pos   5U

TPI DEVID: AsynClkIn Position

◆ TPI_DEVID_FIFOSZ_Msk

#define TPI_DEVID_FIFOSZ_Msk   (0x7UL << TPI_DEVID_FIFOSZ_Pos)

TPI DEVID: FIFO depth Mask

TPI DEVID: FIFOSZ Mask

◆ TPI_DEVID_FIFOSZ_Pos

#define TPI_DEVID_FIFOSZ_Pos   6U

TPI DEVID: FIFO depth Position

TPI DEVID: FIFOSZ Position

◆ TPI_DEVID_MANCVALID_Msk [1/8]

#define TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

◆ TPI_DEVID_MANCVALID_Msk [2/8]

#define TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

◆ TPI_DEVID_MANCVALID_Msk [3/8]

#define TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

◆ TPI_DEVID_MANCVALID_Msk [4/8]

#define TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

◆ TPI_DEVID_MANCVALID_Msk [5/8]

#define TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

◆ TPI_DEVID_MANCVALID_Msk [6/8]

#define TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

◆ TPI_DEVID_MANCVALID_Msk [7/8]

#define TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

◆ TPI_DEVID_MANCVALID_Msk [8/8]

#define TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

◆ TPI_DEVID_MANCVALID_Pos [1/8]

#define TPI_DEVID_MANCVALID_Pos   10U

TPI DEVID: MANCVALID Position

◆ TPI_DEVID_MANCVALID_Pos [2/8]

#define TPI_DEVID_MANCVALID_Pos   10U

TPI DEVID: MANCVALID Position

◆ TPI_DEVID_MANCVALID_Pos [3/8]

#define TPI_DEVID_MANCVALID_Pos   10U

TPI DEVID: MANCVALID Position

◆ TPI_DEVID_MANCVALID_Pos [4/8]

#define TPI_DEVID_MANCVALID_Pos   10U

TPI DEVID: MANCVALID Position

◆ TPI_DEVID_MANCVALID_Pos [5/8]

#define TPI_DEVID_MANCVALID_Pos   10U

TPI DEVID: MANCVALID Position

◆ TPI_DEVID_MANCVALID_Pos [6/8]

#define TPI_DEVID_MANCVALID_Pos   10U

TPI DEVID: MANCVALID Position

◆ TPI_DEVID_MANCVALID_Pos [7/8]

#define TPI_DEVID_MANCVALID_Pos   10U

TPI DEVID: MANCVALID Position

◆ TPI_DEVID_MANCVALID_Pos [8/8]

#define TPI_DEVID_MANCVALID_Pos   10U

TPI DEVID: MANCVALID Position

◆ TPI_DEVID_MinBufSz_Msk [1/4]

#define TPI_DEVID_MinBufSz_Msk   (0x7UL << TPI_DEVID_MinBufSz_Pos)

TPI DEVID: MinBufSz Mask

◆ TPI_DEVID_MinBufSz_Msk [2/4]

#define TPI_DEVID_MinBufSz_Msk   (0x7UL << TPI_DEVID_MinBufSz_Pos)

TPI DEVID: MinBufSz Mask

◆ TPI_DEVID_MinBufSz_Msk [3/4]

#define TPI_DEVID_MinBufSz_Msk   (0x7UL << TPI_DEVID_MinBufSz_Pos)

TPI DEVID: MinBufSz Mask

◆ TPI_DEVID_MinBufSz_Msk [4/4]

#define TPI_DEVID_MinBufSz_Msk   (0x7UL << TPI_DEVID_MinBufSz_Pos)

TPI DEVID: MinBufSz Mask

◆ TPI_DEVID_MinBufSz_Pos [1/4]

#define TPI_DEVID_MinBufSz_Pos   6U

TPI DEVID: MinBufSz Position

◆ TPI_DEVID_MinBufSz_Pos [2/4]

#define TPI_DEVID_MinBufSz_Pos   6U

TPI DEVID: MinBufSz Position

◆ TPI_DEVID_MinBufSz_Pos [3/4]

#define TPI_DEVID_MinBufSz_Pos   6U

TPI DEVID: MinBufSz Position

◆ TPI_DEVID_MinBufSz_Pos [4/4]

#define TPI_DEVID_MinBufSz_Pos   6U

TPI DEVID: MinBufSz Position

◆ TPI_DEVID_NrTraceInput_Msk [1/6]

#define TPI_DEVID_NrTraceInput_Msk   (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

◆ TPI_DEVID_NrTraceInput_Msk [2/6]

#define TPI_DEVID_NrTraceInput_Msk   (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

◆ TPI_DEVID_NrTraceInput_Msk [3/6]

#define TPI_DEVID_NrTraceInput_Msk   (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

◆ TPI_DEVID_NrTraceInput_Msk [4/6]

#define TPI_DEVID_NrTraceInput_Msk   (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

◆ TPI_DEVID_NrTraceInput_Msk [5/6]

#define TPI_DEVID_NrTraceInput_Msk   (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

◆ TPI_DEVID_NrTraceInput_Msk [6/6]

#define TPI_DEVID_NrTraceInput_Msk   (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

◆ TPI_DEVID_NrTraceInput_Pos [1/6]

#define TPI_DEVID_NrTraceInput_Pos   0U

TPI DEVID: NrTraceInput Position

◆ TPI_DEVID_NrTraceInput_Pos [2/6]

#define TPI_DEVID_NrTraceInput_Pos   0U

TPI DEVID: NrTraceInput Position

◆ TPI_DEVID_NrTraceInput_Pos [3/6]

#define TPI_DEVID_NrTraceInput_Pos   0U

TPI DEVID: NrTraceInput Position

◆ TPI_DEVID_NrTraceInput_Pos [4/6]

#define TPI_DEVID_NrTraceInput_Pos   0U

TPI DEVID: NrTraceInput Position

◆ TPI_DEVID_NrTraceInput_Pos [5/6]

#define TPI_DEVID_NrTraceInput_Pos   0U

TPI DEVID: NrTraceInput Position

◆ TPI_DEVID_NrTraceInput_Pos [6/6]

#define TPI_DEVID_NrTraceInput_Pos   0U

TPI DEVID: NrTraceInput Position

◆ TPI_DEVID_NRZVALID_Msk [1/8]

#define TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

◆ TPI_DEVID_NRZVALID_Msk [2/8]

#define TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

◆ TPI_DEVID_NRZVALID_Msk [3/8]

#define TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

◆ TPI_DEVID_NRZVALID_Msk [4/8]

#define TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

◆ TPI_DEVID_NRZVALID_Msk [5/8]

#define TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

◆ TPI_DEVID_NRZVALID_Msk [6/8]

#define TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

◆ TPI_DEVID_NRZVALID_Msk [7/8]

#define TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

◆ TPI_DEVID_NRZVALID_Msk [8/8]

#define TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

◆ TPI_DEVID_NRZVALID_Pos [1/8]

#define TPI_DEVID_NRZVALID_Pos   11U

TPI DEVID: NRZVALID Position

◆ TPI_DEVID_NRZVALID_Pos [2/8]

#define TPI_DEVID_NRZVALID_Pos   11U

TPI DEVID: NRZVALID Position

◆ TPI_DEVID_NRZVALID_Pos [3/8]

#define TPI_DEVID_NRZVALID_Pos   11U

TPI DEVID: NRZVALID Position

◆ TPI_DEVID_NRZVALID_Pos [4/8]

#define TPI_DEVID_NRZVALID_Pos   11U

TPI DEVID: NRZVALID Position

◆ TPI_DEVID_NRZVALID_Pos [5/8]

#define TPI_DEVID_NRZVALID_Pos   11U

TPI DEVID: NRZVALID Position

◆ TPI_DEVID_NRZVALID_Pos [6/8]

#define TPI_DEVID_NRZVALID_Pos   11U

TPI DEVID: NRZVALID Position

◆ TPI_DEVID_NRZVALID_Pos [7/8]

#define TPI_DEVID_NRZVALID_Pos   11U

TPI DEVID: NRZVALID Position

◆ TPI_DEVID_NRZVALID_Pos [8/8]

#define TPI_DEVID_NRZVALID_Pos   11U

TPI DEVID: NRZVALID Position

◆ TPI_DEVID_PTINVALID_Msk [1/8]

#define TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

◆ TPI_DEVID_PTINVALID_Msk [2/8]

#define TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

◆ TPI_DEVID_PTINVALID_Msk [3/8]

#define TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

◆ TPI_DEVID_PTINVALID_Msk [4/8]

#define TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

◆ TPI_DEVID_PTINVALID_Msk [5/8]

#define TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

◆ TPI_DEVID_PTINVALID_Msk [6/8]

#define TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

◆ TPI_DEVID_PTINVALID_Msk [7/8]

#define TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

◆ TPI_DEVID_PTINVALID_Msk [8/8]

#define TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

◆ TPI_DEVID_PTINVALID_Pos [1/8]

#define TPI_DEVID_PTINVALID_Pos   9U

TPI DEVID: PTINVALID Position

◆ TPI_DEVID_PTINVALID_Pos [2/8]

#define TPI_DEVID_PTINVALID_Pos   9U

TPI DEVID: PTINVALID Position

◆ TPI_DEVID_PTINVALID_Pos [3/8]

#define TPI_DEVID_PTINVALID_Pos   9U

TPI DEVID: PTINVALID Position

◆ TPI_DEVID_PTINVALID_Pos [4/8]

#define TPI_DEVID_PTINVALID_Pos   9U

TPI DEVID: PTINVALID Position

◆ TPI_DEVID_PTINVALID_Pos [5/8]

#define TPI_DEVID_PTINVALID_Pos   9U

TPI DEVID: PTINVALID Position

◆ TPI_DEVID_PTINVALID_Pos [6/8]

#define TPI_DEVID_PTINVALID_Pos   9U

TPI DEVID: PTINVALID Position

◆ TPI_DEVID_PTINVALID_Pos [7/8]

#define TPI_DEVID_PTINVALID_Pos   9U

TPI DEVID: PTINVALID Position

◆ TPI_DEVID_PTINVALID_Pos [8/8]

#define TPI_DEVID_PTINVALID_Pos   9U

TPI DEVID: PTINVALID Position

◆ TPI_DEVTYPE_MajorType_Msk [1/8]

#define TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

◆ TPI_DEVTYPE_MajorType_Msk [2/8]

#define TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

◆ TPI_DEVTYPE_MajorType_Msk [3/8]

#define TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

◆ TPI_DEVTYPE_MajorType_Msk [4/8]

#define TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

◆ TPI_DEVTYPE_MajorType_Msk [5/8]

#define TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

◆ TPI_DEVTYPE_MajorType_Msk [6/8]

#define TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

◆ TPI_DEVTYPE_MajorType_Msk [7/8]

#define TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

◆ TPI_DEVTYPE_MajorType_Msk [8/8]

#define TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

◆ TPI_DEVTYPE_MajorType_Pos [1/8]

#define TPI_DEVTYPE_MajorType_Pos   0U

TPI DEVTYPE: MajorType Position

◆ TPI_DEVTYPE_MajorType_Pos [2/8]

#define TPI_DEVTYPE_MajorType_Pos   0U

TPI DEVTYPE: MajorType Position

◆ TPI_DEVTYPE_MajorType_Pos [3/8]

#define TPI_DEVTYPE_MajorType_Pos   0U

TPI DEVTYPE: MajorType Position

◆ TPI_DEVTYPE_MajorType_Pos [4/8]

#define TPI_DEVTYPE_MajorType_Pos   0U

TPI DEVTYPE: MajorType Position

◆ TPI_DEVTYPE_MajorType_Pos [5/8]

#define TPI_DEVTYPE_MajorType_Pos   0U

TPI DEVTYPE: MajorType Position

◆ TPI_DEVTYPE_MajorType_Pos [6/8]

#define TPI_DEVTYPE_MajorType_Pos   0U

TPI DEVTYPE: MajorType Position

◆ TPI_DEVTYPE_MajorType_Pos [7/8]

#define TPI_DEVTYPE_MajorType_Pos   0U

TPI DEVTYPE: MajorType Position

◆ TPI_DEVTYPE_MajorType_Pos [8/8]

#define TPI_DEVTYPE_MajorType_Pos   0U

TPI DEVTYPE: MajorType Position

◆ TPI_DEVTYPE_SubType_Msk [1/8]

#define TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)

TPI DEVTYPE: SubType Mask

◆ TPI_DEVTYPE_SubType_Msk [2/8]

#define TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)

TPI DEVTYPE: SubType Mask

◆ TPI_DEVTYPE_SubType_Msk [3/8]

#define TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)

TPI DEVTYPE: SubType Mask

◆ TPI_DEVTYPE_SubType_Msk [4/8]

#define TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)

TPI DEVTYPE: SubType Mask

◆ TPI_DEVTYPE_SubType_Msk [5/8]

#define TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)

TPI DEVTYPE: SubType Mask

◆ TPI_DEVTYPE_SubType_Msk [6/8]

#define TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)

TPI DEVTYPE: SubType Mask

◆ TPI_DEVTYPE_SubType_Msk [7/8]

#define TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)

TPI DEVTYPE: SubType Mask

◆ TPI_DEVTYPE_SubType_Msk [8/8]

#define TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)

TPI DEVTYPE: SubType Mask

◆ TPI_DEVTYPE_SubType_Pos [1/8]

#define TPI_DEVTYPE_SubType_Pos   4U

TPI DEVTYPE: SubType Position

◆ TPI_DEVTYPE_SubType_Pos [2/8]

#define TPI_DEVTYPE_SubType_Pos   4U

TPI DEVTYPE: SubType Position

◆ TPI_DEVTYPE_SubType_Pos [3/8]

#define TPI_DEVTYPE_SubType_Pos   4U

TPI DEVTYPE: SubType Position

◆ TPI_DEVTYPE_SubType_Pos [4/8]

#define TPI_DEVTYPE_SubType_Pos   4U

TPI DEVTYPE: SubType Position

◆ TPI_DEVTYPE_SubType_Pos [5/8]

#define TPI_DEVTYPE_SubType_Pos   4U

TPI DEVTYPE: SubType Position

◆ TPI_DEVTYPE_SubType_Pos [6/8]

#define TPI_DEVTYPE_SubType_Pos   4U

TPI DEVTYPE: SubType Position

◆ TPI_DEVTYPE_SubType_Pos [7/8]

#define TPI_DEVTYPE_SubType_Pos   4U

TPI DEVTYPE: SubType Position

◆ TPI_DEVTYPE_SubType_Pos [8/8]

#define TPI_DEVTYPE_SubType_Pos   4U

TPI DEVTYPE: SubType Position

◆ TPI_FFCR_EnFCont_Msk [1/8]

#define TPI_FFCR_EnFCont_Msk   (0x1UL << TPI_FFCR_EnFCont_Pos)

TPI FFCR: EnFCont Mask

◆ TPI_FFCR_EnFCont_Msk [2/8]

#define TPI_FFCR_EnFCont_Msk   (0x1UL << TPI_FFCR_EnFCont_Pos)

TPI FFCR: EnFCont Mask

◆ TPI_FFCR_EnFCont_Msk [3/8]

#define TPI_FFCR_EnFCont_Msk   (0x1UL << TPI_FFCR_EnFCont_Pos)

TPI FFCR: EnFCont Mask

◆ TPI_FFCR_EnFCont_Msk [4/8]

#define TPI_FFCR_EnFCont_Msk   (0x1UL << TPI_FFCR_EnFCont_Pos)

TPI FFCR: EnFCont Mask

◆ TPI_FFCR_EnFCont_Msk [5/8]

#define TPI_FFCR_EnFCont_Msk   (0x1UL << TPI_FFCR_EnFCont_Pos)

TPI FFCR: EnFCont Mask

◆ TPI_FFCR_EnFCont_Msk [6/8]

#define TPI_FFCR_EnFCont_Msk   (0x1UL << TPI_FFCR_EnFCont_Pos)

TPI FFCR: EnFCont Mask

◆ TPI_FFCR_EnFCont_Msk [7/8]

#define TPI_FFCR_EnFCont_Msk   (0x1UL << TPI_FFCR_EnFCont_Pos)

TPI FFCR: EnFCont Mask

◆ TPI_FFCR_EnFCont_Msk [8/8]

#define TPI_FFCR_EnFCont_Msk   (0x1UL << TPI_FFCR_EnFCont_Pos)

TPI FFCR: EnFCont Mask

◆ TPI_FFCR_EnFCont_Pos [1/8]

#define TPI_FFCR_EnFCont_Pos   1U

TPI FFCR: EnFCont Position

◆ TPI_FFCR_EnFCont_Pos [2/8]

#define TPI_FFCR_EnFCont_Pos   1U

TPI FFCR: EnFCont Position

◆ TPI_FFCR_EnFCont_Pos [3/8]

#define TPI_FFCR_EnFCont_Pos   1U

TPI FFCR: EnFCont Position

◆ TPI_FFCR_EnFCont_Pos [4/8]

#define TPI_FFCR_EnFCont_Pos   1U

TPI FFCR: EnFCont Position

◆ TPI_FFCR_EnFCont_Pos [5/8]

#define TPI_FFCR_EnFCont_Pos   1U

TPI FFCR: EnFCont Position

◆ TPI_FFCR_EnFCont_Pos [6/8]

#define TPI_FFCR_EnFCont_Pos   1U

TPI FFCR: EnFCont Position

◆ TPI_FFCR_EnFCont_Pos [7/8]

#define TPI_FFCR_EnFCont_Pos   1U

TPI FFCR: EnFCont Position

◆ TPI_FFCR_EnFCont_Pos [8/8]

#define TPI_FFCR_EnFCont_Pos   1U

TPI FFCR: EnFCont Position

◆ TPI_FFCR_FOnMan_Msk

#define TPI_FFCR_FOnMan_Msk   (0x1UL << TPI_FFCR_FOnMan_Pos)

TPI FFCR: FOnMan Mask

◆ TPI_FFCR_FOnMan_Pos

#define TPI_FFCR_FOnMan_Pos   6U

TPI FFCR: FOnMan Position

◆ TPI_FFCR_TrigIn_Msk [1/8]

#define TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)

TPI FFCR: TrigIn Mask

◆ TPI_FFCR_TrigIn_Msk [2/8]

#define TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)

TPI FFCR: TrigIn Mask

◆ TPI_FFCR_TrigIn_Msk [3/8]

#define TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)

TPI FFCR: TrigIn Mask

◆ TPI_FFCR_TrigIn_Msk [4/8]

#define TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)

TPI FFCR: TrigIn Mask

◆ TPI_FFCR_TrigIn_Msk [5/8]

#define TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)

TPI FFCR: TrigIn Mask

◆ TPI_FFCR_TrigIn_Msk [6/8]

#define TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)

TPI FFCR: TrigIn Mask

◆ TPI_FFCR_TrigIn_Msk [7/8]

#define TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)

TPI FFCR: TrigIn Mask

◆ TPI_FFCR_TrigIn_Msk [8/8]

#define TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)

TPI FFCR: TrigIn Mask

◆ TPI_FFCR_TrigIn_Pos [1/8]

#define TPI_FFCR_TrigIn_Pos   8U

TPI FFCR: TrigIn Position

◆ TPI_FFCR_TrigIn_Pos [2/8]

#define TPI_FFCR_TrigIn_Pos   8U

TPI FFCR: TrigIn Position

◆ TPI_FFCR_TrigIn_Pos [3/8]

#define TPI_FFCR_TrigIn_Pos   8U

TPI FFCR: TrigIn Position

◆ TPI_FFCR_TrigIn_Pos [4/8]

#define TPI_FFCR_TrigIn_Pos   8U

TPI FFCR: TrigIn Position

◆ TPI_FFCR_TrigIn_Pos [5/8]

#define TPI_FFCR_TrigIn_Pos   8U

TPI FFCR: TrigIn Position

◆ TPI_FFCR_TrigIn_Pos [6/8]

#define TPI_FFCR_TrigIn_Pos   8U

TPI FFCR: TrigIn Position

◆ TPI_FFCR_TrigIn_Pos [7/8]

#define TPI_FFCR_TrigIn_Pos   8U

TPI FFCR: TrigIn Position

◆ TPI_FFCR_TrigIn_Pos [8/8]

#define TPI_FFCR_TrigIn_Pos   8U

TPI FFCR: TrigIn Position

◆ TPI_FFSR_FlInProg_Msk [1/8]

#define TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)

TPI FFSR: FlInProg Mask

◆ TPI_FFSR_FlInProg_Msk [2/8]

#define TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)

TPI FFSR: FlInProg Mask

◆ TPI_FFSR_FlInProg_Msk [3/8]

#define TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)

TPI FFSR: FlInProg Mask

◆ TPI_FFSR_FlInProg_Msk [4/8]

#define TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)

TPI FFSR: FlInProg Mask

◆ TPI_FFSR_FlInProg_Msk [5/8]

#define TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)

TPI FFSR: FlInProg Mask

◆ TPI_FFSR_FlInProg_Msk [6/8]

#define TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)

TPI FFSR: FlInProg Mask

◆ TPI_FFSR_FlInProg_Msk [7/8]

#define TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)

TPI FFSR: FlInProg Mask

◆ TPI_FFSR_FlInProg_Msk [8/8]

#define TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)

TPI FFSR: FlInProg Mask

◆ TPI_FFSR_FlInProg_Pos [1/8]

#define TPI_FFSR_FlInProg_Pos   0U

TPI FFSR: FlInProg Position

◆ TPI_FFSR_FlInProg_Pos [2/8]

#define TPI_FFSR_FlInProg_Pos   0U

TPI FFSR: FlInProg Position

◆ TPI_FFSR_FlInProg_Pos [3/8]

#define TPI_FFSR_FlInProg_Pos   0U

TPI FFSR: FlInProg Position

◆ TPI_FFSR_FlInProg_Pos [4/8]

#define TPI_FFSR_FlInProg_Pos   0U

TPI FFSR: FlInProg Position

◆ TPI_FFSR_FlInProg_Pos [5/8]

#define TPI_FFSR_FlInProg_Pos   0U

TPI FFSR: FlInProg Position

◆ TPI_FFSR_FlInProg_Pos [6/8]

#define TPI_FFSR_FlInProg_Pos   0U

TPI FFSR: FlInProg Position

◆ TPI_FFSR_FlInProg_Pos [7/8]

#define TPI_FFSR_FlInProg_Pos   0U

TPI FFSR: FlInProg Position

◆ TPI_FFSR_FlInProg_Pos [8/8]

#define TPI_FFSR_FlInProg_Pos   0U

TPI FFSR: FlInProg Position

◆ TPI_FFSR_FtNonStop_Msk [1/8]

#define TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)

TPI FFSR: FtNonStop Mask

◆ TPI_FFSR_FtNonStop_Msk [2/8]

#define TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)

TPI FFSR: FtNonStop Mask

◆ TPI_FFSR_FtNonStop_Msk [3/8]

#define TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)

TPI FFSR: FtNonStop Mask

◆ TPI_FFSR_FtNonStop_Msk [4/8]

#define TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)

TPI FFSR: FtNonStop Mask

◆ TPI_FFSR_FtNonStop_Msk [5/8]

#define TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)

TPI FFSR: FtNonStop Mask

◆ TPI_FFSR_FtNonStop_Msk [6/8]

#define TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)

TPI FFSR: FtNonStop Mask

◆ TPI_FFSR_FtNonStop_Msk [7/8]

#define TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)

TPI FFSR: FtNonStop Mask

◆ TPI_FFSR_FtNonStop_Msk [8/8]

#define TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)

TPI FFSR: FtNonStop Mask

◆ TPI_FFSR_FtNonStop_Pos [1/8]

#define TPI_FFSR_FtNonStop_Pos   3U

TPI FFSR: FtNonStop Position

◆ TPI_FFSR_FtNonStop_Pos [2/8]

#define TPI_FFSR_FtNonStop_Pos   3U

TPI FFSR: FtNonStop Position

◆ TPI_FFSR_FtNonStop_Pos [3/8]

#define TPI_FFSR_FtNonStop_Pos   3U

TPI FFSR: FtNonStop Position

◆ TPI_FFSR_FtNonStop_Pos [4/8]

#define TPI_FFSR_FtNonStop_Pos   3U

TPI FFSR: FtNonStop Position

◆ TPI_FFSR_FtNonStop_Pos [5/8]

#define TPI_FFSR_FtNonStop_Pos   3U

TPI FFSR: FtNonStop Position

◆ TPI_FFSR_FtNonStop_Pos [6/8]

#define TPI_FFSR_FtNonStop_Pos   3U

TPI FFSR: FtNonStop Position

◆ TPI_FFSR_FtNonStop_Pos [7/8]

#define TPI_FFSR_FtNonStop_Pos   3U

TPI FFSR: FtNonStop Position

◆ TPI_FFSR_FtNonStop_Pos [8/8]

#define TPI_FFSR_FtNonStop_Pos   3U

TPI FFSR: FtNonStop Position

◆ TPI_FFSR_FtStopped_Msk [1/8]

#define TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)

TPI FFSR: FtStopped Mask

◆ TPI_FFSR_FtStopped_Msk [2/8]

#define TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)

TPI FFSR: FtStopped Mask

◆ TPI_FFSR_FtStopped_Msk [3/8]

#define TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)

TPI FFSR: FtStopped Mask

◆ TPI_FFSR_FtStopped_Msk [4/8]

#define TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)

TPI FFSR: FtStopped Mask

◆ TPI_FFSR_FtStopped_Msk [5/8]

#define TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)

TPI FFSR: FtStopped Mask

◆ TPI_FFSR_FtStopped_Msk [6/8]

#define TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)

TPI FFSR: FtStopped Mask

◆ TPI_FFSR_FtStopped_Msk [7/8]

#define TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)

TPI FFSR: FtStopped Mask

◆ TPI_FFSR_FtStopped_Msk [8/8]

#define TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)

TPI FFSR: FtStopped Mask

◆ TPI_FFSR_FtStopped_Pos [1/8]

#define TPI_FFSR_FtStopped_Pos   1U

TPI FFSR: FtStopped Position

◆ TPI_FFSR_FtStopped_Pos [2/8]

#define TPI_FFSR_FtStopped_Pos   1U

TPI FFSR: FtStopped Position

◆ TPI_FFSR_FtStopped_Pos [3/8]

#define TPI_FFSR_FtStopped_Pos   1U

TPI FFSR: FtStopped Position

◆ TPI_FFSR_FtStopped_Pos [4/8]

#define TPI_FFSR_FtStopped_Pos   1U

TPI FFSR: FtStopped Position

◆ TPI_FFSR_FtStopped_Pos [5/8]

#define TPI_FFSR_FtStopped_Pos   1U

TPI FFSR: FtStopped Position

◆ TPI_FFSR_FtStopped_Pos [6/8]

#define TPI_FFSR_FtStopped_Pos   1U

TPI FFSR: FtStopped Position

◆ TPI_FFSR_FtStopped_Pos [7/8]

#define TPI_FFSR_FtStopped_Pos   1U

TPI FFSR: FtStopped Position

◆ TPI_FFSR_FtStopped_Pos [8/8]

#define TPI_FFSR_FtStopped_Pos   1U

TPI FFSR: FtStopped Position

◆ TPI_FFSR_TCPresent_Msk [1/8]

#define TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)

TPI FFSR: TCPresent Mask

◆ TPI_FFSR_TCPresent_Msk [2/8]

#define TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)

TPI FFSR: TCPresent Mask

◆ TPI_FFSR_TCPresent_Msk [3/8]

#define TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)

TPI FFSR: TCPresent Mask

◆ TPI_FFSR_TCPresent_Msk [4/8]

#define TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)

TPI FFSR: TCPresent Mask

◆ TPI_FFSR_TCPresent_Msk [5/8]

#define TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)

TPI FFSR: TCPresent Mask

◆ TPI_FFSR_TCPresent_Msk [6/8]

#define TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)

TPI FFSR: TCPresent Mask

◆ TPI_FFSR_TCPresent_Msk [7/8]

#define TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)

TPI FFSR: TCPresent Mask

◆ TPI_FFSR_TCPresent_Msk [8/8]

#define TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)

TPI FFSR: TCPresent Mask

◆ TPI_FFSR_TCPresent_Pos [1/8]

#define TPI_FFSR_TCPresent_Pos   2U

TPI FFSR: TCPresent Position

◆ TPI_FFSR_TCPresent_Pos [2/8]

#define TPI_FFSR_TCPresent_Pos   2U

TPI FFSR: TCPresent Position

◆ TPI_FFSR_TCPresent_Pos [3/8]

#define TPI_FFSR_TCPresent_Pos   2U

TPI FFSR: TCPresent Position

◆ TPI_FFSR_TCPresent_Pos [4/8]

#define TPI_FFSR_TCPresent_Pos   2U

TPI FFSR: TCPresent Position

◆ TPI_FFSR_TCPresent_Pos [5/8]

#define TPI_FFSR_TCPresent_Pos   2U

TPI FFSR: TCPresent Position

◆ TPI_FFSR_TCPresent_Pos [6/8]

#define TPI_FFSR_TCPresent_Pos   2U

TPI FFSR: TCPresent Position

◆ TPI_FFSR_TCPresent_Pos [7/8]

#define TPI_FFSR_TCPresent_Pos   2U

TPI FFSR: TCPresent Position

◆ TPI_FFSR_TCPresent_Pos [8/8]

#define TPI_FFSR_TCPresent_Pos   2U

TPI FFSR: TCPresent Position

◆ TPI_FIFO0_ETM0_Msk [1/4]

#define TPI_FIFO0_ETM0_Msk   (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)

TPI FIFO0: ETM0 Mask

◆ TPI_FIFO0_ETM0_Msk [2/4]

#define TPI_FIFO0_ETM0_Msk   (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)

TPI FIFO0: ETM0 Mask

◆ TPI_FIFO0_ETM0_Msk [3/4]

#define TPI_FIFO0_ETM0_Msk   (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)

TPI FIFO0: ETM0 Mask

◆ TPI_FIFO0_ETM0_Msk [4/4]

#define TPI_FIFO0_ETM0_Msk   (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)

TPI FIFO0: ETM0 Mask

◆ TPI_FIFO0_ETM0_Pos [1/4]

#define TPI_FIFO0_ETM0_Pos   0U

TPI FIFO0: ETM0 Position

◆ TPI_FIFO0_ETM0_Pos [2/4]

#define TPI_FIFO0_ETM0_Pos   0U

TPI FIFO0: ETM0 Position

◆ TPI_FIFO0_ETM0_Pos [3/4]

#define TPI_FIFO0_ETM0_Pos   0U

TPI FIFO0: ETM0 Position

◆ TPI_FIFO0_ETM0_Pos [4/4]

#define TPI_FIFO0_ETM0_Pos   0U

TPI FIFO0: ETM0 Position

◆ TPI_FIFO0_ETM1_Msk [1/4]

#define TPI_FIFO0_ETM1_Msk   (0xFFUL << TPI_FIFO0_ETM1_Pos)

TPI FIFO0: ETM1 Mask

◆ TPI_FIFO0_ETM1_Msk [2/4]

#define TPI_FIFO0_ETM1_Msk   (0xFFUL << TPI_FIFO0_ETM1_Pos)

TPI FIFO0: ETM1 Mask

◆ TPI_FIFO0_ETM1_Msk [3/4]

#define TPI_FIFO0_ETM1_Msk   (0xFFUL << TPI_FIFO0_ETM1_Pos)

TPI FIFO0: ETM1 Mask

◆ TPI_FIFO0_ETM1_Msk [4/4]

#define TPI_FIFO0_ETM1_Msk   (0xFFUL << TPI_FIFO0_ETM1_Pos)

TPI FIFO0: ETM1 Mask

◆ TPI_FIFO0_ETM1_Pos [1/4]

#define TPI_FIFO0_ETM1_Pos   8U

TPI FIFO0: ETM1 Position

◆ TPI_FIFO0_ETM1_Pos [2/4]

#define TPI_FIFO0_ETM1_Pos   8U

TPI FIFO0: ETM1 Position

◆ TPI_FIFO0_ETM1_Pos [3/4]

#define TPI_FIFO0_ETM1_Pos   8U

TPI FIFO0: ETM1 Position

◆ TPI_FIFO0_ETM1_Pos [4/4]

#define TPI_FIFO0_ETM1_Pos   8U

TPI FIFO0: ETM1 Position

◆ TPI_FIFO0_ETM2_Msk [1/4]

#define TPI_FIFO0_ETM2_Msk   (0xFFUL << TPI_FIFO0_ETM2_Pos)

TPI FIFO0: ETM2 Mask

◆ TPI_FIFO0_ETM2_Msk [2/4]

#define TPI_FIFO0_ETM2_Msk   (0xFFUL << TPI_FIFO0_ETM2_Pos)

TPI FIFO0: ETM2 Mask

◆ TPI_FIFO0_ETM2_Msk [3/4]

#define TPI_FIFO0_ETM2_Msk   (0xFFUL << TPI_FIFO0_ETM2_Pos)

TPI FIFO0: ETM2 Mask

◆ TPI_FIFO0_ETM2_Msk [4/4]

#define TPI_FIFO0_ETM2_Msk   (0xFFUL << TPI_FIFO0_ETM2_Pos)

TPI FIFO0: ETM2 Mask

◆ TPI_FIFO0_ETM2_Pos [1/4]

#define TPI_FIFO0_ETM2_Pos   16U

TPI FIFO0: ETM2 Position

◆ TPI_FIFO0_ETM2_Pos [2/4]

#define TPI_FIFO0_ETM2_Pos   16U

TPI FIFO0: ETM2 Position

◆ TPI_FIFO0_ETM2_Pos [3/4]

#define TPI_FIFO0_ETM2_Pos   16U

TPI FIFO0: ETM2 Position

◆ TPI_FIFO0_ETM2_Pos [4/4]

#define TPI_FIFO0_ETM2_Pos   16U

TPI FIFO0: ETM2 Position

◆ TPI_FIFO0_ETM_ATVALID_Msk [1/4]

#define TPI_FIFO0_ETM_ATVALID_Msk   (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)

TPI FIFO0: ETM_ATVALID Mask

◆ TPI_FIFO0_ETM_ATVALID_Msk [2/4]

#define TPI_FIFO0_ETM_ATVALID_Msk   (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)

TPI FIFO0: ETM_ATVALID Mask

◆ TPI_FIFO0_ETM_ATVALID_Msk [3/4]

#define TPI_FIFO0_ETM_ATVALID_Msk   (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)

TPI FIFO0: ETM_ATVALID Mask

◆ TPI_FIFO0_ETM_ATVALID_Msk [4/4]

#define TPI_FIFO0_ETM_ATVALID_Msk   (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)

TPI FIFO0: ETM_ATVALID Mask

◆ TPI_FIFO0_ETM_ATVALID_Pos [1/4]

#define TPI_FIFO0_ETM_ATVALID_Pos   26U

TPI FIFO0: ETM_ATVALID Position

◆ TPI_FIFO0_ETM_ATVALID_Pos [2/4]

#define TPI_FIFO0_ETM_ATVALID_Pos   26U

TPI FIFO0: ETM_ATVALID Position

◆ TPI_FIFO0_ETM_ATVALID_Pos [3/4]

#define TPI_FIFO0_ETM_ATVALID_Pos   26U

TPI FIFO0: ETM_ATVALID Position

◆ TPI_FIFO0_ETM_ATVALID_Pos [4/4]

#define TPI_FIFO0_ETM_ATVALID_Pos   26U

TPI FIFO0: ETM_ATVALID Position

◆ TPI_FIFO0_ETM_bytecount_Msk [1/4]

#define TPI_FIFO0_ETM_bytecount_Msk   (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)

TPI FIFO0: ETM_bytecount Mask

◆ TPI_FIFO0_ETM_bytecount_Msk [2/4]

#define TPI_FIFO0_ETM_bytecount_Msk   (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)

TPI FIFO0: ETM_bytecount Mask

◆ TPI_FIFO0_ETM_bytecount_Msk [3/4]

#define TPI_FIFO0_ETM_bytecount_Msk   (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)

TPI FIFO0: ETM_bytecount Mask

◆ TPI_FIFO0_ETM_bytecount_Msk [4/4]

#define TPI_FIFO0_ETM_bytecount_Msk   (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)

TPI FIFO0: ETM_bytecount Mask

◆ TPI_FIFO0_ETM_bytecount_Pos [1/4]

#define TPI_FIFO0_ETM_bytecount_Pos   24U

TPI FIFO0: ETM_bytecount Position

◆ TPI_FIFO0_ETM_bytecount_Pos [2/4]

#define TPI_FIFO0_ETM_bytecount_Pos   24U

TPI FIFO0: ETM_bytecount Position

◆ TPI_FIFO0_ETM_bytecount_Pos [3/4]

#define TPI_FIFO0_ETM_bytecount_Pos   24U

TPI FIFO0: ETM_bytecount Position

◆ TPI_FIFO0_ETM_bytecount_Pos [4/4]

#define TPI_FIFO0_ETM_bytecount_Pos   24U

TPI FIFO0: ETM_bytecount Position

◆ TPI_FIFO0_ITM_ATVALID_Msk [1/4]

#define TPI_FIFO0_ITM_ATVALID_Msk   (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)

TPI FIFO0: ITM_ATVALID Mask

◆ TPI_FIFO0_ITM_ATVALID_Msk [2/4]

#define TPI_FIFO0_ITM_ATVALID_Msk   (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)

TPI FIFO0: ITM_ATVALID Mask

◆ TPI_FIFO0_ITM_ATVALID_Msk [3/4]

#define TPI_FIFO0_ITM_ATVALID_Msk   (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)

TPI FIFO0: ITM_ATVALID Mask

◆ TPI_FIFO0_ITM_ATVALID_Msk [4/4]

#define TPI_FIFO0_ITM_ATVALID_Msk   (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)

TPI FIFO0: ITM_ATVALID Mask

◆ TPI_FIFO0_ITM_ATVALID_Pos [1/4]

#define TPI_FIFO0_ITM_ATVALID_Pos   29U

TPI FIFO0: ITM_ATVALID Position

◆ TPI_FIFO0_ITM_ATVALID_Pos [2/4]

#define TPI_FIFO0_ITM_ATVALID_Pos   29U

TPI FIFO0: ITM_ATVALID Position

◆ TPI_FIFO0_ITM_ATVALID_Pos [3/4]

#define TPI_FIFO0_ITM_ATVALID_Pos   29U

TPI FIFO0: ITM_ATVALID Position

◆ TPI_FIFO0_ITM_ATVALID_Pos [4/4]

#define TPI_FIFO0_ITM_ATVALID_Pos   29U

TPI FIFO0: ITM_ATVALID Position

◆ TPI_FIFO0_ITM_bytecount_Msk [1/4]

#define TPI_FIFO0_ITM_bytecount_Msk   (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)

TPI FIFO0: ITM_bytecount Mask

◆ TPI_FIFO0_ITM_bytecount_Msk [2/4]

#define TPI_FIFO0_ITM_bytecount_Msk   (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)

TPI FIFO0: ITM_bytecount Mask

◆ TPI_FIFO0_ITM_bytecount_Msk [3/4]

#define TPI_FIFO0_ITM_bytecount_Msk   (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)

TPI FIFO0: ITM_bytecount Mask

◆ TPI_FIFO0_ITM_bytecount_Msk [4/4]

#define TPI_FIFO0_ITM_bytecount_Msk   (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)

TPI FIFO0: ITM_bytecount Mask

◆ TPI_FIFO0_ITM_bytecount_Pos [1/4]

#define TPI_FIFO0_ITM_bytecount_Pos   27U

TPI FIFO0: ITM_bytecount Position

◆ TPI_FIFO0_ITM_bytecount_Pos [2/4]

#define TPI_FIFO0_ITM_bytecount_Pos   27U

TPI FIFO0: ITM_bytecount Position

◆ TPI_FIFO0_ITM_bytecount_Pos [3/4]

#define TPI_FIFO0_ITM_bytecount_Pos   27U

TPI FIFO0: ITM_bytecount Position

◆ TPI_FIFO0_ITM_bytecount_Pos [4/4]

#define TPI_FIFO0_ITM_bytecount_Pos   27U

TPI FIFO0: ITM_bytecount Position

◆ TPI_FIFO1_ETM_ATVALID_Msk [1/4]

#define TPI_FIFO1_ETM_ATVALID_Msk   (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)

TPI FIFO1: ETM_ATVALID Mask

◆ TPI_FIFO1_ETM_ATVALID_Msk [2/4]

#define TPI_FIFO1_ETM_ATVALID_Msk   (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)

TPI FIFO1: ETM_ATVALID Mask

◆ TPI_FIFO1_ETM_ATVALID_Msk [3/4]

#define TPI_FIFO1_ETM_ATVALID_Msk   (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)

TPI FIFO1: ETM_ATVALID Mask

◆ TPI_FIFO1_ETM_ATVALID_Msk [4/4]

#define TPI_FIFO1_ETM_ATVALID_Msk   (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)

TPI FIFO1: ETM_ATVALID Mask

◆ TPI_FIFO1_ETM_ATVALID_Pos [1/4]

#define TPI_FIFO1_ETM_ATVALID_Pos   26U

TPI FIFO1: ETM_ATVALID Position

◆ TPI_FIFO1_ETM_ATVALID_Pos [2/4]

#define TPI_FIFO1_ETM_ATVALID_Pos   26U

TPI FIFO1: ETM_ATVALID Position

◆ TPI_FIFO1_ETM_ATVALID_Pos [3/4]

#define TPI_FIFO1_ETM_ATVALID_Pos   26U

TPI FIFO1: ETM_ATVALID Position

◆ TPI_FIFO1_ETM_ATVALID_Pos [4/4]

#define TPI_FIFO1_ETM_ATVALID_Pos   26U

TPI FIFO1: ETM_ATVALID Position

◆ TPI_FIFO1_ETM_bytecount_Msk [1/4]

#define TPI_FIFO1_ETM_bytecount_Msk   (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)

TPI FIFO1: ETM_bytecount Mask

◆ TPI_FIFO1_ETM_bytecount_Msk [2/4]

#define TPI_FIFO1_ETM_bytecount_Msk   (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)

TPI FIFO1: ETM_bytecount Mask

◆ TPI_FIFO1_ETM_bytecount_Msk [3/4]

#define TPI_FIFO1_ETM_bytecount_Msk   (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)

TPI FIFO1: ETM_bytecount Mask

◆ TPI_FIFO1_ETM_bytecount_Msk [4/4]

#define TPI_FIFO1_ETM_bytecount_Msk   (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)

TPI FIFO1: ETM_bytecount Mask

◆ TPI_FIFO1_ETM_bytecount_Pos [1/4]

#define TPI_FIFO1_ETM_bytecount_Pos   24U

TPI FIFO1: ETM_bytecount Position

◆ TPI_FIFO1_ETM_bytecount_Pos [2/4]

#define TPI_FIFO1_ETM_bytecount_Pos   24U

TPI FIFO1: ETM_bytecount Position

◆ TPI_FIFO1_ETM_bytecount_Pos [3/4]

#define TPI_FIFO1_ETM_bytecount_Pos   24U

TPI FIFO1: ETM_bytecount Position

◆ TPI_FIFO1_ETM_bytecount_Pos [4/4]

#define TPI_FIFO1_ETM_bytecount_Pos   24U

TPI FIFO1: ETM_bytecount Position

◆ TPI_FIFO1_ITM0_Msk [1/4]

#define TPI_FIFO1_ITM0_Msk   (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)

TPI FIFO1: ITM0 Mask

◆ TPI_FIFO1_ITM0_Msk [2/4]

#define TPI_FIFO1_ITM0_Msk   (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)

TPI FIFO1: ITM0 Mask

◆ TPI_FIFO1_ITM0_Msk [3/4]

#define TPI_FIFO1_ITM0_Msk   (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)

TPI FIFO1: ITM0 Mask

◆ TPI_FIFO1_ITM0_Msk [4/4]

#define TPI_FIFO1_ITM0_Msk   (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)

TPI FIFO1: ITM0 Mask

◆ TPI_FIFO1_ITM0_Pos [1/4]

#define TPI_FIFO1_ITM0_Pos   0U

TPI FIFO1: ITM0 Position

◆ TPI_FIFO1_ITM0_Pos [2/4]

#define TPI_FIFO1_ITM0_Pos   0U

TPI FIFO1: ITM0 Position

◆ TPI_FIFO1_ITM0_Pos [3/4]

#define TPI_FIFO1_ITM0_Pos   0U

TPI FIFO1: ITM0 Position

◆ TPI_FIFO1_ITM0_Pos [4/4]

#define TPI_FIFO1_ITM0_Pos   0U

TPI FIFO1: ITM0 Position

◆ TPI_FIFO1_ITM1_Msk [1/4]

#define TPI_FIFO1_ITM1_Msk   (0xFFUL << TPI_FIFO1_ITM1_Pos)

TPI FIFO1: ITM1 Mask

◆ TPI_FIFO1_ITM1_Msk [2/4]

#define TPI_FIFO1_ITM1_Msk   (0xFFUL << TPI_FIFO1_ITM1_Pos)

TPI FIFO1: ITM1 Mask

◆ TPI_FIFO1_ITM1_Msk [3/4]

#define TPI_FIFO1_ITM1_Msk   (0xFFUL << TPI_FIFO1_ITM1_Pos)

TPI FIFO1: ITM1 Mask

◆ TPI_FIFO1_ITM1_Msk [4/4]

#define TPI_FIFO1_ITM1_Msk   (0xFFUL << TPI_FIFO1_ITM1_Pos)

TPI FIFO1: ITM1 Mask

◆ TPI_FIFO1_ITM1_Pos [1/4]

#define TPI_FIFO1_ITM1_Pos   8U

TPI FIFO1: ITM1 Position

◆ TPI_FIFO1_ITM1_Pos [2/4]

#define TPI_FIFO1_ITM1_Pos   8U

TPI FIFO1: ITM1 Position

◆ TPI_FIFO1_ITM1_Pos [3/4]

#define TPI_FIFO1_ITM1_Pos   8U

TPI FIFO1: ITM1 Position

◆ TPI_FIFO1_ITM1_Pos [4/4]

#define TPI_FIFO1_ITM1_Pos   8U

TPI FIFO1: ITM1 Position

◆ TPI_FIFO1_ITM2_Msk [1/4]

#define TPI_FIFO1_ITM2_Msk   (0xFFUL << TPI_FIFO1_ITM2_Pos)

TPI FIFO1: ITM2 Mask

◆ TPI_FIFO1_ITM2_Msk [2/4]

#define TPI_FIFO1_ITM2_Msk   (0xFFUL << TPI_FIFO1_ITM2_Pos)

TPI FIFO1: ITM2 Mask

◆ TPI_FIFO1_ITM2_Msk [3/4]

#define TPI_FIFO1_ITM2_Msk   (0xFFUL << TPI_FIFO1_ITM2_Pos)

TPI FIFO1: ITM2 Mask

◆ TPI_FIFO1_ITM2_Msk [4/4]

#define TPI_FIFO1_ITM2_Msk   (0xFFUL << TPI_FIFO1_ITM2_Pos)

TPI FIFO1: ITM2 Mask

◆ TPI_FIFO1_ITM2_Pos [1/4]

#define TPI_FIFO1_ITM2_Pos   16U

TPI FIFO1: ITM2 Position

◆ TPI_FIFO1_ITM2_Pos [2/4]

#define TPI_FIFO1_ITM2_Pos   16U

TPI FIFO1: ITM2 Position

◆ TPI_FIFO1_ITM2_Pos [3/4]

#define TPI_FIFO1_ITM2_Pos   16U

TPI FIFO1: ITM2 Position

◆ TPI_FIFO1_ITM2_Pos [4/4]

#define TPI_FIFO1_ITM2_Pos   16U

TPI FIFO1: ITM2 Position

◆ TPI_FIFO1_ITM_ATVALID_Msk [1/4]

#define TPI_FIFO1_ITM_ATVALID_Msk   (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)

TPI FIFO1: ITM_ATVALID Mask

◆ TPI_FIFO1_ITM_ATVALID_Msk [2/4]

#define TPI_FIFO1_ITM_ATVALID_Msk   (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)

TPI FIFO1: ITM_ATVALID Mask

◆ TPI_FIFO1_ITM_ATVALID_Msk [3/4]

#define TPI_FIFO1_ITM_ATVALID_Msk   (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)

TPI FIFO1: ITM_ATVALID Mask

◆ TPI_FIFO1_ITM_ATVALID_Msk [4/4]

#define TPI_FIFO1_ITM_ATVALID_Msk   (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)

TPI FIFO1: ITM_ATVALID Mask

◆ TPI_FIFO1_ITM_ATVALID_Pos [1/4]

#define TPI_FIFO1_ITM_ATVALID_Pos   29U

TPI FIFO1: ITM_ATVALID Position

◆ TPI_FIFO1_ITM_ATVALID_Pos [2/4]

#define TPI_FIFO1_ITM_ATVALID_Pos   29U

TPI FIFO1: ITM_ATVALID Position

◆ TPI_FIFO1_ITM_ATVALID_Pos [3/4]

#define TPI_FIFO1_ITM_ATVALID_Pos   29U

TPI FIFO1: ITM_ATVALID Position

◆ TPI_FIFO1_ITM_ATVALID_Pos [4/4]

#define TPI_FIFO1_ITM_ATVALID_Pos   29U

TPI FIFO1: ITM_ATVALID Position

◆ TPI_FIFO1_ITM_bytecount_Msk [1/4]

#define TPI_FIFO1_ITM_bytecount_Msk   (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)

TPI FIFO1: ITM_bytecount Mask

◆ TPI_FIFO1_ITM_bytecount_Msk [2/4]

#define TPI_FIFO1_ITM_bytecount_Msk   (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)

TPI FIFO1: ITM_bytecount Mask

◆ TPI_FIFO1_ITM_bytecount_Msk [3/4]

#define TPI_FIFO1_ITM_bytecount_Msk   (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)

TPI FIFO1: ITM_bytecount Mask

◆ TPI_FIFO1_ITM_bytecount_Msk [4/4]

#define TPI_FIFO1_ITM_bytecount_Msk   (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)

TPI FIFO1: ITM_bytecount Mask

◆ TPI_FIFO1_ITM_bytecount_Pos [1/4]

#define TPI_FIFO1_ITM_bytecount_Pos   27U

TPI FIFO1: ITM_bytecount Position

◆ TPI_FIFO1_ITM_bytecount_Pos [2/4]

#define TPI_FIFO1_ITM_bytecount_Pos   27U

TPI FIFO1: ITM_bytecount Position

◆ TPI_FIFO1_ITM_bytecount_Pos [3/4]

#define TPI_FIFO1_ITM_bytecount_Pos   27U

TPI FIFO1: ITM_bytecount Position

◆ TPI_FIFO1_ITM_bytecount_Pos [4/4]

#define TPI_FIFO1_ITM_bytecount_Pos   27U

TPI FIFO1: ITM_bytecount Position

◆ TPI_ITATBCTR0_ATREADY1_Msk [1/4]

#define TPI_ITATBCTR0_ATREADY1_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)

TPI ITATBCTR0: ATREADY1 Mask

◆ TPI_ITATBCTR0_ATREADY1_Msk [2/4]

#define TPI_ITATBCTR0_ATREADY1_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)

TPI ITATBCTR0: ATREADY1 Mask

◆ TPI_ITATBCTR0_ATREADY1_Msk [3/4]

#define TPI_ITATBCTR0_ATREADY1_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)

TPI ITATBCTR0: ATREADY1 Mask

◆ TPI_ITATBCTR0_ATREADY1_Msk [4/4]

#define TPI_ITATBCTR0_ATREADY1_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)

TPI ITATBCTR0: ATREADY1 Mask

◆ TPI_ITATBCTR0_ATREADY1_Pos [1/4]

#define TPI_ITATBCTR0_ATREADY1_Pos   0U

TPI ITATBCTR0: ATREADY1 Position

◆ TPI_ITATBCTR0_ATREADY1_Pos [2/4]

#define TPI_ITATBCTR0_ATREADY1_Pos   0U

TPI ITATBCTR0: ATREADY1 Position

◆ TPI_ITATBCTR0_ATREADY1_Pos [3/4]

#define TPI_ITATBCTR0_ATREADY1_Pos   0U

TPI ITATBCTR0: ATREADY1 Position

◆ TPI_ITATBCTR0_ATREADY1_Pos [4/4]

#define TPI_ITATBCTR0_ATREADY1_Pos   0U

TPI ITATBCTR0: ATREADY1 Position

◆ TPI_ITATBCTR0_ATREADY2_Msk [1/4]

#define TPI_ITATBCTR0_ATREADY2_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)

TPI ITATBCTR0: ATREADY2 Mask

◆ TPI_ITATBCTR0_ATREADY2_Msk [2/4]

#define TPI_ITATBCTR0_ATREADY2_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)

TPI ITATBCTR0: ATREADY2 Mask

◆ TPI_ITATBCTR0_ATREADY2_Msk [3/4]

#define TPI_ITATBCTR0_ATREADY2_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)

TPI ITATBCTR0: ATREADY2 Mask

◆ TPI_ITATBCTR0_ATREADY2_Msk [4/4]

#define TPI_ITATBCTR0_ATREADY2_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)

TPI ITATBCTR0: ATREADY2 Mask

◆ TPI_ITATBCTR0_ATREADY2_Pos [1/4]

#define TPI_ITATBCTR0_ATREADY2_Pos   0U

TPI ITATBCTR0: ATREADY2 Position

◆ TPI_ITATBCTR0_ATREADY2_Pos [2/4]

#define TPI_ITATBCTR0_ATREADY2_Pos   0U

TPI ITATBCTR0: ATREADY2 Position

◆ TPI_ITATBCTR0_ATREADY2_Pos [3/4]

#define TPI_ITATBCTR0_ATREADY2_Pos   0U

TPI ITATBCTR0: ATREADY2 Position

◆ TPI_ITATBCTR0_ATREADY2_Pos [4/4]

#define TPI_ITATBCTR0_ATREADY2_Pos   0U

TPI ITATBCTR0: ATREADY2 Position

◆ TPI_ITATBCTR2_ATREADY1_Msk [1/4]

#define TPI_ITATBCTR2_ATREADY1_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)

TPI ITATBCTR2: ATREADY1 Mask

◆ TPI_ITATBCTR2_ATREADY1_Msk [2/4]

#define TPI_ITATBCTR2_ATREADY1_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)

TPI ITATBCTR2: ATREADY1 Mask

◆ TPI_ITATBCTR2_ATREADY1_Msk [3/4]

#define TPI_ITATBCTR2_ATREADY1_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)

TPI ITATBCTR2: ATREADY1 Mask

◆ TPI_ITATBCTR2_ATREADY1_Msk [4/4]

#define TPI_ITATBCTR2_ATREADY1_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)

TPI ITATBCTR2: ATREADY1 Mask

◆ TPI_ITATBCTR2_ATREADY1_Pos [1/4]

#define TPI_ITATBCTR2_ATREADY1_Pos   0U

TPI ITATBCTR2: ATREADY1 Position

◆ TPI_ITATBCTR2_ATREADY1_Pos [2/4]

#define TPI_ITATBCTR2_ATREADY1_Pos   0U

TPI ITATBCTR2: ATREADY1 Position

◆ TPI_ITATBCTR2_ATREADY1_Pos [3/4]

#define TPI_ITATBCTR2_ATREADY1_Pos   0U

TPI ITATBCTR2: ATREADY1 Position

◆ TPI_ITATBCTR2_ATREADY1_Pos [4/4]

#define TPI_ITATBCTR2_ATREADY1_Pos   0U

TPI ITATBCTR2: ATREADY1 Position

◆ TPI_ITATBCTR2_ATREADY2_Msk [1/4]

#define TPI_ITATBCTR2_ATREADY2_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)

TPI ITATBCTR2: ATREADY2 Mask

◆ TPI_ITATBCTR2_ATREADY2_Msk [2/4]

#define TPI_ITATBCTR2_ATREADY2_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)

TPI ITATBCTR2: ATREADY2 Mask

◆ TPI_ITATBCTR2_ATREADY2_Msk [3/4]

#define TPI_ITATBCTR2_ATREADY2_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)

TPI ITATBCTR2: ATREADY2 Mask

◆ TPI_ITATBCTR2_ATREADY2_Msk [4/4]

#define TPI_ITATBCTR2_ATREADY2_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)

TPI ITATBCTR2: ATREADY2 Mask

◆ TPI_ITATBCTR2_ATREADY2_Pos [1/4]

#define TPI_ITATBCTR2_ATREADY2_Pos   0U

TPI ITATBCTR2: ATREADY2 Position

◆ TPI_ITATBCTR2_ATREADY2_Pos [2/4]

#define TPI_ITATBCTR2_ATREADY2_Pos   0U

TPI ITATBCTR2: ATREADY2 Position

◆ TPI_ITATBCTR2_ATREADY2_Pos [3/4]

#define TPI_ITATBCTR2_ATREADY2_Pos   0U

TPI ITATBCTR2: ATREADY2 Position

◆ TPI_ITATBCTR2_ATREADY2_Pos [4/4]

#define TPI_ITATBCTR2_ATREADY2_Pos   0U

TPI ITATBCTR2: ATREADY2 Position

◆ TPI_ITCTRL_Mode_Msk [1/6]

#define TPI_ITCTRL_Mode_Msk   (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)

TPI ITCTRL: Mode Mask

◆ TPI_ITCTRL_Mode_Msk [2/6]

#define TPI_ITCTRL_Mode_Msk   (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)

TPI ITCTRL: Mode Mask

◆ TPI_ITCTRL_Mode_Msk [3/6]

#define TPI_ITCTRL_Mode_Msk   (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)

TPI ITCTRL: Mode Mask

◆ TPI_ITCTRL_Mode_Msk [4/6]

#define TPI_ITCTRL_Mode_Msk   (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)

TPI ITCTRL: Mode Mask

◆ TPI_ITCTRL_Mode_Msk [5/6]

#define TPI_ITCTRL_Mode_Msk   (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)

TPI ITCTRL: Mode Mask

◆ TPI_ITCTRL_Mode_Msk [6/6]

#define TPI_ITCTRL_Mode_Msk   (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)

TPI ITCTRL: Mode Mask

◆ TPI_ITCTRL_Mode_Pos [1/6]

#define TPI_ITCTRL_Mode_Pos   0U

TPI ITCTRL: Mode Position

◆ TPI_ITCTRL_Mode_Pos [2/6]

#define TPI_ITCTRL_Mode_Pos   0U

TPI ITCTRL: Mode Position

◆ TPI_ITCTRL_Mode_Pos [3/6]

#define TPI_ITCTRL_Mode_Pos   0U

TPI ITCTRL: Mode Position

◆ TPI_ITCTRL_Mode_Pos [4/6]

#define TPI_ITCTRL_Mode_Pos   0U

TPI ITCTRL: Mode Position

◆ TPI_ITCTRL_Mode_Pos [5/6]

#define TPI_ITCTRL_Mode_Pos   0U

TPI ITCTRL: Mode Position

◆ TPI_ITCTRL_Mode_Pos [6/6]

#define TPI_ITCTRL_Mode_Pos   0U

TPI ITCTRL: Mode Position

◆ TPI_SPPR_TXMODE_Msk [1/8]

#define TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)

TPI SPPR: TXMODE Mask

◆ TPI_SPPR_TXMODE_Msk [2/8]

#define TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)

TPI SPPR: TXMODE Mask

◆ TPI_SPPR_TXMODE_Msk [3/8]

#define TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)

TPI SPPR: TXMODE Mask

◆ TPI_SPPR_TXMODE_Msk [4/8]

#define TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)

TPI SPPR: TXMODE Mask

◆ TPI_SPPR_TXMODE_Msk [5/8]

#define TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)

TPI SPPR: TXMODE Mask

◆ TPI_SPPR_TXMODE_Msk [6/8]

#define TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)

TPI SPPR: TXMODE Mask

◆ TPI_SPPR_TXMODE_Msk [7/8]

#define TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)

TPI SPPR: TXMODE Mask

◆ TPI_SPPR_TXMODE_Msk [8/8]

#define TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)

TPI SPPR: TXMODE Mask

◆ TPI_SPPR_TXMODE_Pos [1/8]

#define TPI_SPPR_TXMODE_Pos   0U

TPI SPPR: TXMODE Position

◆ TPI_SPPR_TXMODE_Pos [2/8]

#define TPI_SPPR_TXMODE_Pos   0U

TPI SPPR: TXMODE Position

◆ TPI_SPPR_TXMODE_Pos [3/8]

#define TPI_SPPR_TXMODE_Pos   0U

TPI SPPR: TXMODE Position

◆ TPI_SPPR_TXMODE_Pos [4/8]

#define TPI_SPPR_TXMODE_Pos   0U

TPI SPPR: TXMODE Position

◆ TPI_SPPR_TXMODE_Pos [5/8]

#define TPI_SPPR_TXMODE_Pos   0U

TPI SPPR: TXMODE Position

◆ TPI_SPPR_TXMODE_Pos [6/8]

#define TPI_SPPR_TXMODE_Pos   0U

TPI SPPR: TXMODE Position

◆ TPI_SPPR_TXMODE_Pos [7/8]

#define TPI_SPPR_TXMODE_Pos   0U

TPI SPPR: TXMODE Position

◆ TPI_SPPR_TXMODE_Pos [8/8]

#define TPI_SPPR_TXMODE_Pos   0U

TPI SPPR: TXMODE Position

◆ TPI_TRIGGER_TRIGGER_Msk [1/6]

#define TPI_TRIGGER_TRIGGER_Msk   (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)

TPI TRIGGER: TRIGGER Mask

◆ TPI_TRIGGER_TRIGGER_Msk [2/6]

#define TPI_TRIGGER_TRIGGER_Msk   (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)

TPI TRIGGER: TRIGGER Mask

◆ TPI_TRIGGER_TRIGGER_Msk [3/6]

#define TPI_TRIGGER_TRIGGER_Msk   (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)

TPI TRIGGER: TRIGGER Mask

◆ TPI_TRIGGER_TRIGGER_Msk [4/6]

#define TPI_TRIGGER_TRIGGER_Msk   (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)

TPI TRIGGER: TRIGGER Mask

◆ TPI_TRIGGER_TRIGGER_Msk [5/6]

#define TPI_TRIGGER_TRIGGER_Msk   (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)

TPI TRIGGER: TRIGGER Mask

◆ TPI_TRIGGER_TRIGGER_Msk [6/6]

#define TPI_TRIGGER_TRIGGER_Msk   (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)

TPI TRIGGER: TRIGGER Mask

◆ TPI_TRIGGER_TRIGGER_Pos [1/6]

#define TPI_TRIGGER_TRIGGER_Pos   0U

TPI TRIGGER: TRIGGER Position

◆ TPI_TRIGGER_TRIGGER_Pos [2/6]

#define TPI_TRIGGER_TRIGGER_Pos   0U

TPI TRIGGER: TRIGGER Position

◆ TPI_TRIGGER_TRIGGER_Pos [3/6]

#define TPI_TRIGGER_TRIGGER_Pos   0U

TPI TRIGGER: TRIGGER Position

◆ TPI_TRIGGER_TRIGGER_Pos [4/6]

#define TPI_TRIGGER_TRIGGER_Pos   0U

TPI TRIGGER: TRIGGER Position

◆ TPI_TRIGGER_TRIGGER_Pos [5/6]

#define TPI_TRIGGER_TRIGGER_Pos   0U

TPI TRIGGER: TRIGGER Position

◆ TPI_TRIGGER_TRIGGER_Pos [6/6]

#define TPI_TRIGGER_TRIGGER_Pos   0U

TPI TRIGGER: TRIGGER Position

◆ xPSR_C_Msk [1/12]

#define xPSR_C_Msk   (1UL << xPSR_C_Pos)

xPSR: C Mask

◆ xPSR_C_Msk [2/12]

#define xPSR_C_Msk   (1UL << xPSR_C_Pos)

xPSR: C Mask

◆ xPSR_C_Msk [3/12]

#define xPSR_C_Msk   (1UL << xPSR_C_Pos)

xPSR: C Mask

◆ xPSR_C_Msk [4/12]

#define xPSR_C_Msk   (1UL << xPSR_C_Pos)

xPSR: C Mask

◆ xPSR_C_Msk [5/12]

#define xPSR_C_Msk   (1UL << xPSR_C_Pos)

xPSR: C Mask

◆ xPSR_C_Msk [6/12]

#define xPSR_C_Msk   (1UL << xPSR_C_Pos)

xPSR: C Mask

◆ xPSR_C_Msk [7/12]

#define xPSR_C_Msk   (1UL << xPSR_C_Pos)

xPSR: C Mask

◆ xPSR_C_Msk [8/12]

#define xPSR_C_Msk   (1UL << xPSR_C_Pos)

xPSR: C Mask

◆ xPSR_C_Msk [9/12]

#define xPSR_C_Msk   (1UL << xPSR_C_Pos)

xPSR: C Mask

◆ xPSR_C_Msk [10/12]

#define xPSR_C_Msk   (1UL << xPSR_C_Pos)

xPSR: C Mask

◆ xPSR_C_Msk [11/12]

#define xPSR_C_Msk   (1UL << xPSR_C_Pos)

xPSR: C Mask

◆ xPSR_C_Msk [12/12]

#define xPSR_C_Msk   (1UL << xPSR_C_Pos)

xPSR: C Mask

◆ xPSR_C_Pos [1/12]

#define xPSR_C_Pos   29U

xPSR: C Position

◆ xPSR_C_Pos [2/12]

#define xPSR_C_Pos   29U

xPSR: C Position

◆ xPSR_C_Pos [3/12]

#define xPSR_C_Pos   29U

xPSR: C Position

◆ xPSR_C_Pos [4/12]

#define xPSR_C_Pos   29U

xPSR: C Position

◆ xPSR_C_Pos [5/12]

#define xPSR_C_Pos   29U

xPSR: C Position

◆ xPSR_C_Pos [6/12]

#define xPSR_C_Pos   29U

xPSR: C Position

◆ xPSR_C_Pos [7/12]

#define xPSR_C_Pos   29U

xPSR: C Position

◆ xPSR_C_Pos [8/12]

#define xPSR_C_Pos   29U

xPSR: C Position

◆ xPSR_C_Pos [9/12]

#define xPSR_C_Pos   29U

xPSR: C Position

◆ xPSR_C_Pos [10/12]

#define xPSR_C_Pos   29U

xPSR: C Position

◆ xPSR_C_Pos [11/12]

#define xPSR_C_Pos   29U

xPSR: C Position

◆ xPSR_C_Pos [12/12]

#define xPSR_C_Pos   29U

xPSR: C Position

◆ xPSR_GE_Msk [1/4]

#define xPSR_GE_Msk   (0xFUL << xPSR_GE_Pos)

xPSR: GE Mask

◆ xPSR_GE_Msk [2/4]

#define xPSR_GE_Msk   (0xFUL << xPSR_GE_Pos)

xPSR: GE Mask

◆ xPSR_GE_Msk [3/4]

#define xPSR_GE_Msk   (0xFUL << xPSR_GE_Pos)

xPSR: GE Mask

◆ xPSR_GE_Msk [4/4]

#define xPSR_GE_Msk   (0xFUL << xPSR_GE_Pos)

xPSR: GE Mask

◆ xPSR_GE_Pos [1/4]

#define xPSR_GE_Pos   16U

xPSR: GE Position

◆ xPSR_GE_Pos [2/4]

#define xPSR_GE_Pos   16U

xPSR: GE Position

◆ xPSR_GE_Pos [3/4]

#define xPSR_GE_Pos   16U

xPSR: GE Position

◆ xPSR_GE_Pos [4/4]

#define xPSR_GE_Pos   16U

xPSR: GE Position

◆ xPSR_ICI_IT_1_Msk [1/4]

#define xPSR_ICI_IT_1_Msk   (0x3FUL << xPSR_ICI_IT_1_Pos)

xPSR: ICI/IT part 1 Mask

◆ xPSR_ICI_IT_1_Msk [2/4]

#define xPSR_ICI_IT_1_Msk   (0x3FUL << xPSR_ICI_IT_1_Pos)

xPSR: ICI/IT part 1 Mask

◆ xPSR_ICI_IT_1_Msk [3/4]

#define xPSR_ICI_IT_1_Msk   (0x3FUL << xPSR_ICI_IT_1_Pos)

xPSR: ICI/IT part 1 Mask

◆ xPSR_ICI_IT_1_Msk [4/4]

#define xPSR_ICI_IT_1_Msk   (0x3FUL << xPSR_ICI_IT_1_Pos)

xPSR: ICI/IT part 1 Mask

◆ xPSR_ICI_IT_1_Pos [1/4]

#define xPSR_ICI_IT_1_Pos   10U

xPSR: ICI/IT part 1 Position

◆ xPSR_ICI_IT_1_Pos [2/4]

#define xPSR_ICI_IT_1_Pos   10U

xPSR: ICI/IT part 1 Position

◆ xPSR_ICI_IT_1_Pos [3/4]

#define xPSR_ICI_IT_1_Pos   10U

xPSR: ICI/IT part 1 Position

◆ xPSR_ICI_IT_1_Pos [4/4]

#define xPSR_ICI_IT_1_Pos   10U

xPSR: ICI/IT part 1 Position

◆ xPSR_ICI_IT_2_Msk [1/4]

#define xPSR_ICI_IT_2_Msk   (3UL << xPSR_ICI_IT_2_Pos)

xPSR: ICI/IT part 2 Mask

◆ xPSR_ICI_IT_2_Msk [2/4]

#define xPSR_ICI_IT_2_Msk   (3UL << xPSR_ICI_IT_2_Pos)

xPSR: ICI/IT part 2 Mask

◆ xPSR_ICI_IT_2_Msk [3/4]

#define xPSR_ICI_IT_2_Msk   (3UL << xPSR_ICI_IT_2_Pos)

xPSR: ICI/IT part 2 Mask

◆ xPSR_ICI_IT_2_Msk [4/4]

#define xPSR_ICI_IT_2_Msk   (3UL << xPSR_ICI_IT_2_Pos)

xPSR: ICI/IT part 2 Mask

◆ xPSR_ICI_IT_2_Pos [1/4]

#define xPSR_ICI_IT_2_Pos   25U

xPSR: ICI/IT part 2 Position

◆ xPSR_ICI_IT_2_Pos [2/4]

#define xPSR_ICI_IT_2_Pos   25U

xPSR: ICI/IT part 2 Position

◆ xPSR_ICI_IT_2_Pos [3/4]

#define xPSR_ICI_IT_2_Pos   25U

xPSR: ICI/IT part 2 Position

◆ xPSR_ICI_IT_2_Pos [4/4]

#define xPSR_ICI_IT_2_Pos   25U

xPSR: ICI/IT part 2 Position

◆ xPSR_ISR_Msk [1/12]

#define xPSR_ISR_Msk   (0x1FFUL /*<< xPSR_ISR_Pos*/)

xPSR: ISR Mask

◆ xPSR_ISR_Msk [2/12]

#define xPSR_ISR_Msk   (0x1FFUL /*<< xPSR_ISR_Pos*/)

xPSR: ISR Mask

◆ xPSR_ISR_Msk [3/12]

#define xPSR_ISR_Msk   (0x1FFUL /*<< xPSR_ISR_Pos*/)

xPSR: ISR Mask

◆ xPSR_ISR_Msk [4/12]

#define xPSR_ISR_Msk   (0x1FFUL /*<< xPSR_ISR_Pos*/)

xPSR: ISR Mask

◆ xPSR_ISR_Msk [5/12]

#define xPSR_ISR_Msk   (0x1FFUL /*<< xPSR_ISR_Pos*/)

xPSR: ISR Mask

◆ xPSR_ISR_Msk [6/12]

#define xPSR_ISR_Msk   (0x1FFUL /*<< xPSR_ISR_Pos*/)

xPSR: ISR Mask

◆ xPSR_ISR_Msk [7/12]

#define xPSR_ISR_Msk   (0x1FFUL /*<< xPSR_ISR_Pos*/)

xPSR: ISR Mask

◆ xPSR_ISR_Msk [8/12]

#define xPSR_ISR_Msk   (0x1FFUL /*<< xPSR_ISR_Pos*/)

xPSR: ISR Mask

◆ xPSR_ISR_Msk [9/12]

#define xPSR_ISR_Msk   (0x1FFUL /*<< xPSR_ISR_Pos*/)

xPSR: ISR Mask

◆ xPSR_ISR_Msk [10/12]

#define xPSR_ISR_Msk   (0x1FFUL /*<< xPSR_ISR_Pos*/)

xPSR: ISR Mask

◆ xPSR_ISR_Msk [11/12]

#define xPSR_ISR_Msk   (0x1FFUL /*<< xPSR_ISR_Pos*/)

xPSR: ISR Mask

◆ xPSR_ISR_Msk [12/12]

#define xPSR_ISR_Msk   (0x1FFUL /*<< xPSR_ISR_Pos*/)

xPSR: ISR Mask

◆ xPSR_ISR_Pos [1/12]

#define xPSR_ISR_Pos   0U

xPSR: ISR Position

◆ xPSR_ISR_Pos [2/12]

#define xPSR_ISR_Pos   0U

xPSR: ISR Position

◆ xPSR_ISR_Pos [3/12]

#define xPSR_ISR_Pos   0U

xPSR: ISR Position

◆ xPSR_ISR_Pos [4/12]

#define xPSR_ISR_Pos   0U

xPSR: ISR Position

◆ xPSR_ISR_Pos [5/12]

#define xPSR_ISR_Pos   0U

xPSR: ISR Position

◆ xPSR_ISR_Pos [6/12]

#define xPSR_ISR_Pos   0U

xPSR: ISR Position

◆ xPSR_ISR_Pos [7/12]

#define xPSR_ISR_Pos   0U

xPSR: ISR Position

◆ xPSR_ISR_Pos [8/12]

#define xPSR_ISR_Pos   0U

xPSR: ISR Position

◆ xPSR_ISR_Pos [9/12]

#define xPSR_ISR_Pos   0U

xPSR: ISR Position

◆ xPSR_ISR_Pos [10/12]

#define xPSR_ISR_Pos   0U

xPSR: ISR Position

◆ xPSR_ISR_Pos [11/12]

#define xPSR_ISR_Pos   0U

xPSR: ISR Position

◆ xPSR_ISR_Pos [12/12]

#define xPSR_ISR_Pos   0U

xPSR: ISR Position

◆ xPSR_IT_Msk [1/2]

#define xPSR_IT_Msk   (3UL << xPSR_IT_Pos)

xPSR: IT Mask

◆ xPSR_IT_Msk [2/2]

#define xPSR_IT_Msk   (3UL << xPSR_IT_Pos)

xPSR: IT Mask

◆ xPSR_IT_Pos [1/2]

#define xPSR_IT_Pos   25U

xPSR: IT Position

◆ xPSR_IT_Pos [2/2]

#define xPSR_IT_Pos   25U

xPSR: IT Position

◆ xPSR_N_Msk [1/12]

#define xPSR_N_Msk   (1UL << xPSR_N_Pos)

xPSR: N Mask

◆ xPSR_N_Msk [2/12]

#define xPSR_N_Msk   (1UL << xPSR_N_Pos)

xPSR: N Mask

◆ xPSR_N_Msk [3/12]

#define xPSR_N_Msk   (1UL << xPSR_N_Pos)

xPSR: N Mask

◆ xPSR_N_Msk [4/12]

#define xPSR_N_Msk   (1UL << xPSR_N_Pos)

xPSR: N Mask

◆ xPSR_N_Msk [5/12]

#define xPSR_N_Msk   (1UL << xPSR_N_Pos)

xPSR: N Mask

◆ xPSR_N_Msk [6/12]

#define xPSR_N_Msk   (1UL << xPSR_N_Pos)

xPSR: N Mask

◆ xPSR_N_Msk [7/12]

#define xPSR_N_Msk   (1UL << xPSR_N_Pos)

xPSR: N Mask

◆ xPSR_N_Msk [8/12]

#define xPSR_N_Msk   (1UL << xPSR_N_Pos)

xPSR: N Mask

◆ xPSR_N_Msk [9/12]

#define xPSR_N_Msk   (1UL << xPSR_N_Pos)

xPSR: N Mask

◆ xPSR_N_Msk [10/12]

#define xPSR_N_Msk   (1UL << xPSR_N_Pos)

xPSR: N Mask

◆ xPSR_N_Msk [11/12]

#define xPSR_N_Msk   (1UL << xPSR_N_Pos)

xPSR: N Mask

◆ xPSR_N_Msk [12/12]

#define xPSR_N_Msk   (1UL << xPSR_N_Pos)

xPSR: N Mask

◆ xPSR_N_Pos [1/12]

#define xPSR_N_Pos   31U

xPSR: N Position

◆ xPSR_N_Pos [2/12]

#define xPSR_N_Pos   31U

xPSR: N Position

◆ xPSR_N_Pos [3/12]

#define xPSR_N_Pos   31U

xPSR: N Position

◆ xPSR_N_Pos [4/12]

#define xPSR_N_Pos   31U

xPSR: N Position

◆ xPSR_N_Pos [5/12]

#define xPSR_N_Pos   31U

xPSR: N Position

◆ xPSR_N_Pos [6/12]

#define xPSR_N_Pos   31U

xPSR: N Position

◆ xPSR_N_Pos [7/12]

#define xPSR_N_Pos   31U

xPSR: N Position

◆ xPSR_N_Pos [8/12]

#define xPSR_N_Pos   31U

xPSR: N Position

◆ xPSR_N_Pos [9/12]

#define xPSR_N_Pos   31U

xPSR: N Position

◆ xPSR_N_Pos [10/12]

#define xPSR_N_Pos   31U

xPSR: N Position

◆ xPSR_N_Pos [11/12]

#define xPSR_N_Pos   31U

xPSR: N Position

◆ xPSR_N_Pos [12/12]

#define xPSR_N_Pos   31U

xPSR: N Position

◆ xPSR_Q_Msk [1/6]

#define xPSR_Q_Msk   (1UL << xPSR_Q_Pos)

xPSR: Q Mask

◆ xPSR_Q_Msk [2/6]

#define xPSR_Q_Msk   (1UL << xPSR_Q_Pos)

xPSR: Q Mask

◆ xPSR_Q_Msk [3/6]

#define xPSR_Q_Msk   (1UL << xPSR_Q_Pos)

xPSR: Q Mask

◆ xPSR_Q_Msk [4/6]

#define xPSR_Q_Msk   (1UL << xPSR_Q_Pos)

xPSR: Q Mask

◆ xPSR_Q_Msk [5/6]

#define xPSR_Q_Msk   (1UL << xPSR_Q_Pos)

xPSR: Q Mask

◆ xPSR_Q_Msk [6/6]

#define xPSR_Q_Msk   (1UL << xPSR_Q_Pos)

xPSR: Q Mask

◆ xPSR_Q_Pos [1/6]

#define xPSR_Q_Pos   27U

xPSR: Q Position

◆ xPSR_Q_Pos [2/6]

#define xPSR_Q_Pos   27U

xPSR: Q Position

◆ xPSR_Q_Pos [3/6]

#define xPSR_Q_Pos   27U

xPSR: Q Position

◆ xPSR_Q_Pos [4/6]

#define xPSR_Q_Pos   27U

xPSR: Q Position

◆ xPSR_Q_Pos [5/6]

#define xPSR_Q_Pos   27U

xPSR: Q Position

◆ xPSR_Q_Pos [6/6]

#define xPSR_Q_Pos   27U

xPSR: Q Position

◆ xPSR_T_Msk [1/12]

#define xPSR_T_Msk   (1UL << xPSR_T_Pos)

xPSR: T Mask

◆ xPSR_T_Msk [2/12]

#define xPSR_T_Msk   (1UL << xPSR_T_Pos)

xPSR: T Mask

◆ xPSR_T_Msk [3/12]

#define xPSR_T_Msk   (1UL << xPSR_T_Pos)

xPSR: T Mask

◆ xPSR_T_Msk [4/12]

#define xPSR_T_Msk   (1UL << xPSR_T_Pos)

xPSR: T Mask

◆ xPSR_T_Msk [5/12]

#define xPSR_T_Msk   (1UL << xPSR_T_Pos)

xPSR: T Mask

◆ xPSR_T_Msk [6/12]

#define xPSR_T_Msk   (1UL << xPSR_T_Pos)

xPSR: T Mask

◆ xPSR_T_Msk [7/12]

#define xPSR_T_Msk   (1UL << xPSR_T_Pos)

xPSR: T Mask

◆ xPSR_T_Msk [8/12]

#define xPSR_T_Msk   (1UL << xPSR_T_Pos)

xPSR: T Mask

◆ xPSR_T_Msk [9/12]

#define xPSR_T_Msk   (1UL << xPSR_T_Pos)

xPSR: T Mask

◆ xPSR_T_Msk [10/12]

#define xPSR_T_Msk   (1UL << xPSR_T_Pos)

xPSR: T Mask

◆ xPSR_T_Msk [11/12]

#define xPSR_T_Msk   (1UL << xPSR_T_Pos)

xPSR: T Mask

◆ xPSR_T_Msk [12/12]

#define xPSR_T_Msk   (1UL << xPSR_T_Pos)

xPSR: T Mask

◆ xPSR_T_Pos [1/12]

#define xPSR_T_Pos   24U

xPSR: T Position

◆ xPSR_T_Pos [2/12]

#define xPSR_T_Pos   24U

xPSR: T Position

◆ xPSR_T_Pos [3/12]

#define xPSR_T_Pos   24U

xPSR: T Position

◆ xPSR_T_Pos [4/12]

#define xPSR_T_Pos   24U

xPSR: T Position

◆ xPSR_T_Pos [5/12]

#define xPSR_T_Pos   24U

xPSR: T Position

◆ xPSR_T_Pos [6/12]

#define xPSR_T_Pos   24U

xPSR: T Position

◆ xPSR_T_Pos [7/12]

#define xPSR_T_Pos   24U

xPSR: T Position

◆ xPSR_T_Pos [8/12]

#define xPSR_T_Pos   24U

xPSR: T Position

◆ xPSR_T_Pos [9/12]

#define xPSR_T_Pos   24U

xPSR: T Position

◆ xPSR_T_Pos [10/12]

#define xPSR_T_Pos   24U

xPSR: T Position

◆ xPSR_T_Pos [11/12]

#define xPSR_T_Pos   24U

xPSR: T Position

◆ xPSR_T_Pos [12/12]

#define xPSR_T_Pos   24U

xPSR: T Position

◆ xPSR_V_Msk [1/12]

#define xPSR_V_Msk   (1UL << xPSR_V_Pos)

xPSR: V Mask

◆ xPSR_V_Msk [2/12]

#define xPSR_V_Msk   (1UL << xPSR_V_Pos)

xPSR: V Mask

◆ xPSR_V_Msk [3/12]

#define xPSR_V_Msk   (1UL << xPSR_V_Pos)

xPSR: V Mask

◆ xPSR_V_Msk [4/12]

#define xPSR_V_Msk   (1UL << xPSR_V_Pos)

xPSR: V Mask

◆ xPSR_V_Msk [5/12]

#define xPSR_V_Msk   (1UL << xPSR_V_Pos)

xPSR: V Mask

◆ xPSR_V_Msk [6/12]

#define xPSR_V_Msk   (1UL << xPSR_V_Pos)

xPSR: V Mask

◆ xPSR_V_Msk [7/12]

#define xPSR_V_Msk   (1UL << xPSR_V_Pos)

xPSR: V Mask

◆ xPSR_V_Msk [8/12]

#define xPSR_V_Msk   (1UL << xPSR_V_Pos)

xPSR: V Mask

◆ xPSR_V_Msk [9/12]

#define xPSR_V_Msk   (1UL << xPSR_V_Pos)

xPSR: V Mask

◆ xPSR_V_Msk [10/12]

#define xPSR_V_Msk   (1UL << xPSR_V_Pos)

xPSR: V Mask

◆ xPSR_V_Msk [11/12]

#define xPSR_V_Msk   (1UL << xPSR_V_Pos)

xPSR: V Mask

◆ xPSR_V_Msk [12/12]

#define xPSR_V_Msk   (1UL << xPSR_V_Pos)

xPSR: V Mask

◆ xPSR_V_Pos [1/12]

#define xPSR_V_Pos   28U

xPSR: V Position

◆ xPSR_V_Pos [2/12]

#define xPSR_V_Pos   28U

xPSR: V Position

◆ xPSR_V_Pos [3/12]

#define xPSR_V_Pos   28U

xPSR: V Position

◆ xPSR_V_Pos [4/12]

#define xPSR_V_Pos   28U

xPSR: V Position

◆ xPSR_V_Pos [5/12]

#define xPSR_V_Pos   28U

xPSR: V Position

◆ xPSR_V_Pos [6/12]

#define xPSR_V_Pos   28U

xPSR: V Position

◆ xPSR_V_Pos [7/12]

#define xPSR_V_Pos   28U

xPSR: V Position

◆ xPSR_V_Pos [8/12]

#define xPSR_V_Pos   28U

xPSR: V Position

◆ xPSR_V_Pos [9/12]

#define xPSR_V_Pos   28U

xPSR: V Position

◆ xPSR_V_Pos [10/12]

#define xPSR_V_Pos   28U

xPSR: V Position

◆ xPSR_V_Pos [11/12]

#define xPSR_V_Pos   28U

xPSR: V Position

◆ xPSR_V_Pos [12/12]

#define xPSR_V_Pos   28U

xPSR: V Position

◆ xPSR_Z_Msk [1/12]

#define xPSR_Z_Msk   (1UL << xPSR_Z_Pos)

xPSR: Z Mask

◆ xPSR_Z_Msk [2/12]

#define xPSR_Z_Msk   (1UL << xPSR_Z_Pos)

xPSR: Z Mask

◆ xPSR_Z_Msk [3/12]

#define xPSR_Z_Msk   (1UL << xPSR_Z_Pos)

xPSR: Z Mask

◆ xPSR_Z_Msk [4/12]

#define xPSR_Z_Msk   (1UL << xPSR_Z_Pos)

xPSR: Z Mask

◆ xPSR_Z_Msk [5/12]

#define xPSR_Z_Msk   (1UL << xPSR_Z_Pos)

xPSR: Z Mask

◆ xPSR_Z_Msk [6/12]

#define xPSR_Z_Msk   (1UL << xPSR_Z_Pos)

xPSR: Z Mask

◆ xPSR_Z_Msk [7/12]

#define xPSR_Z_Msk   (1UL << xPSR_Z_Pos)

xPSR: Z Mask

◆ xPSR_Z_Msk [8/12]

#define xPSR_Z_Msk   (1UL << xPSR_Z_Pos)

xPSR: Z Mask

◆ xPSR_Z_Msk [9/12]

#define xPSR_Z_Msk   (1UL << xPSR_Z_Pos)

xPSR: Z Mask

◆ xPSR_Z_Msk [10/12]

#define xPSR_Z_Msk   (1UL << xPSR_Z_Pos)

xPSR: Z Mask

◆ xPSR_Z_Msk [11/12]

#define xPSR_Z_Msk   (1UL << xPSR_Z_Pos)

xPSR: Z Mask

◆ xPSR_Z_Msk [12/12]

#define xPSR_Z_Msk   (1UL << xPSR_Z_Pos)

xPSR: Z Mask

◆ xPSR_Z_Pos [1/12]

#define xPSR_Z_Pos   30U

xPSR: Z Position

◆ xPSR_Z_Pos [2/12]

#define xPSR_Z_Pos   30U

xPSR: Z Position

◆ xPSR_Z_Pos [3/12]

#define xPSR_Z_Pos   30U

xPSR: Z Position

◆ xPSR_Z_Pos [4/12]

#define xPSR_Z_Pos   30U

xPSR: Z Position

◆ xPSR_Z_Pos [5/12]

#define xPSR_Z_Pos   30U

xPSR: Z Position

◆ xPSR_Z_Pos [6/12]

#define xPSR_Z_Pos   30U

xPSR: Z Position

◆ xPSR_Z_Pos [7/12]

#define xPSR_Z_Pos   30U

xPSR: Z Position

◆ xPSR_Z_Pos [8/12]

#define xPSR_Z_Pos   30U

xPSR: Z Position

◆ xPSR_Z_Pos [9/12]

#define xPSR_Z_Pos   30U

xPSR: Z Position

◆ xPSR_Z_Pos [10/12]

#define xPSR_Z_Pos   30U

xPSR: Z Position

◆ xPSR_Z_Pos [11/12]

#define xPSR_Z_Pos   30U

xPSR: Z Position

◆ xPSR_Z_Pos [12/12]

#define xPSR_Z_Pos   30U

xPSR: Z Position

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